K4T51083QC-ZCD5 Samsung, K4T51083QC-ZCD5 Datasheet

Page 1

... ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply ...

Page 2

C-die DDR2 SDRAM Contents 0. Ordering Information 1. Key Feature 2. Package Pinout/Mechanical Dimension & Addressing 2.1 Package Pinout & Mechanical Dimension 2.2 Input/Output Function Description 2.3 Addressing 3. Absolute Maximum Rating 4. AC & DC Operating Conditions & ...

Page 3

... The 512Mb DDR2 device is available in 60ball FBGAs(x4/x8) and in 84ball FBGAs(x16). Note: The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of oper- ation. 85qC, CASE Page DDR2 SDRAM DDR2-400 3-3-3 Package K4T51043QC-ZC(L)CC 60 FBGA K4T51083QC-ZC(L)CC 60 FBGA K4T51163QC-ZC(L)CC 84 FBGA DDR2-400 3-3 Rev ...

Page 4

C-die DDR2 SDRAM 2. Package Pinout/Mechanical Dimension & Addressing 2.1 Package Pinout x4 package pinout (Top View) : 60ball FBGA Package Notes : 1. Pin B3 has identical capacitance as pin B7. 2. VDDL and VSSDL are power and ...

Page 5

C-die DDR2 SDRAM x8 package pinout (Top View) : 60ball FBGA Package 1 VDD DQ6 VDDQ DQ4 VDDL NC VSS VDD Notes Ball Locations (x8 NU/ VSSQ VSS A DQS RDQS ...

Page 6

C-die DDR2 SDRAM x16 package pinout (Top View) : 84ball FBGA Package 1 2 VDD NC DQ14 VSSQ VDDQ DQ9 DQ12 VSSQ VDD NC DQ6 VSSQ DQ1 VDDQ VSSQ DQ4 VREF VDDL CKE NC BA0 A10/AP VSS A3 A7 ...

Page 7

C-die DDR2 SDRAM FBGA Package Dimension(x4/x8 60- 0.45r  ‡ 0.05 ‡0.2 #A1  10. INDEX MARK 6.40 0.80 1. ...

Page 8

C-die DDR2 SDRAM FBGA Package Dimension(x16 84- 0.45r  ‡ 0.05 ‡0.2 #A1  11. INDEX MARK 6.40 ...

Page 9

C-die DDR2 SDRAM 2.2 Input/Output Functional Description Symbol Type Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK, CK Input CK and negative ...

Page 10

C-die DDR2 SDRAM 2.3 512Mb Addressing Configuration # of Banks Bank Address Auto precharge Row Address Column Address * Reference information: The following tables are address mapping information for other densities. 256Mb Configuration # of Banks Bank Address Auto ...

Page 11

C-die DDR2 SDRAM 3. Absolute Maximum DC Ratings Symbol Parameter Voltage on V pin relative Voltage on V pin relative DDQ DDQ Voltage on V pin relative DDL ...

Page 12

C-die DDR2 SDRAM Operating Temperature Condition Symbol Parameter TOPER Operating Temperature 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard ...

Page 13

C-die DDR2 SDRAM Differential input AC logic Level Symbol Parameter V ID(AC) AC differential input voltage V IX(AC) AC differential cross point voltage Notes (AC) specifies the input differential voltage |V ID and V is the complementary ...

Page 14

C-die DDR2 SDRAM OCD default characteristics Description Output impedance Output impedance step size for OCD calibration Pull-up and pull-down mismatch Output slew rate Notes: 1. Absolute Specifications (0°C dT d+95°C; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V) CASE ...

Page 15

C-die DDR2 SDRAM IDD Specification Parameters and Test Conditions (IDD values are for full operating range of Voltage and Temperature, Notes Symbol Operating one bank active-precharge current CK(IDD ...

Page 16

C-die DDR2 SDRAM Notes : 1. IDD specifications are tested after the device is properly initialized 2. Input slew rate is specified by AC Parametric Test Condition 3. IDD parameters are specified with ODT disabled. 4. Data bus consists ...

Page 17

... CE6 LE6 CD5 LD5 100 4 ...

Page 18

C-die DDR2 SDRAM DDR2 SDRAM IDD Spec Table(2) Symbol 800@CL=5 CE7 LE7 IDD0 tbd IDD1 tbd IDD2P tbd IDD2Q tbd IDD2N tbd IDD3P-F tbd IDD3P-S tbd IDD3N tbd IDD4W tbd IDD4R tbd IDD5 tbd IDD6 tbd IDD7 tbd 32Mx16(K4T51163QC) ...

Page 19

C-die DDR2 SDRAM Input/Output capacitance Parameter Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS Input/output capacitance delta, ...

Page 20

C-die DDR2 SDRAM Timing Parameters by Speed Grade (Refer to notes for informations related to this table at the bottom) Symbol Parameter DQ output access time from CK/CK tAC DQS output access time from CK/CK tDQSCK CK high-level width ...

Page 21

C-die DDR2 SDRAM Symbol Parameter Exit self refresh to a read command tXSRD Exit precharge power down to any non-read tXP command Exit active power down to read command tXARD Exit active power down to read command tXARDS (slow ...

Page 22

C-die DDR2 SDRAM General notes, which may apply for all AC parameters 1. Slew Rate Measurement Levels a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for ...

Page 23

C-die DDR2 SDRAM 4. Differential data strobe DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized ...

Page 24

C-die DDR2 SDRAM Specific Notes for dedicated AC parameters 9. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be used for fast active power down exit timing. tXARDS is ...

Page 25

C-die DDR2 SDRAM 18. tIS and tIH (input setup and hold) derating. 2.0 V/ns 'tIS 4.0 +187 3.5 +179 3.0 +167 2.5 +150 2.0 +125 1.5 +83 1.0 0 0.9 -11 Command/Ad- dress Slew 0.8 -25 rate (V/ns) 0.7 ...

Page 26

C-die DDR2 SDRAM For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the datasheet tIS(base) and tIH(base) value to the delta tIS and delta tIH derating value respectively. Example: tIS ...

Page 27

C-die DDR2 SDRAM tHZ tRPST end point T1 tHZ,tRPST end point = 2*T1-T2 29. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the V tial data strobe crosspoint for a ...

Page 28

C-die DDR2 SDRAM 31. Input waveform timing is referenced from the input signal crossing at the V device under test. 32. Input waveform timing is referenced from the input signal crossing at the V device under test ...

Page 29

C-die DDR2 SDRAM Revision History Version 1.0 (Feb. 2005) - Initial Release Version 1.1 (Mar. 2005) - Added Low power current values for 533&400 speed - Changed IDD3N/2Q normal current values for x16 org. Version 1.2 (May 2005) - ...