GD82559ER Intel Corporation, GD82559ER Datasheet
GD82559ER
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GD82559ER Summary of contents
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... GD82559ER Fast Ethernet** PCI Controller Networking Silicon Product Features Optimum Integration for Lowest Cost Solution — Integrated IEEE 802.3 10BASE-T and 100BASE-TX compatible PHY — Glueless 32-bit PCI master interface — 128 Kbyte Flash interface 2 — Thin BGA 15mm package — ACPI and PCI Power Management — ...
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... GD82559ER - Networking Silicon Revision History Revision Revision Date Mar. 1999 1.0 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right ...
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... Address and Data Signals .................................................................................. 7 3.2.2 Interface Control Signals ....................................................................................8 3.2.3 System and Power Management Signals........................................................... 9 3.3 Local Memory Interface Signals ......................................................................................... 9 3.4 Testability Port Signals .....................................................................................................10 3.5 PHY Signals .....................................................................................................................11 4. GD82559ER MEDIA ACCESS CONTROL FUNCTIONAL DESCRIPTION .................................13 4.1 82559ER Initialization .......................................................................................................13 4.1.1 Initialization Effects on 82559ER Units ............................................................13 4.2 PCI Interface.....................................................................................................................14 4.2.1 82559ER Bus Operations.................................................................................14 4.2.2 Clockrun Signal ................................................................................................22 4.2.3 Power Management Event Signal ...
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... GD82559ER — Networking Silicon 6.1.2 100BASE-TX Transmit Blocks ......................................................................... 37 6.1.3 100BASE-TX Receive Blocks .......................................................................... 40 6.1.4 100BASE-TX Collision Detection ..................................................................... 41 6.1.5 100BASE-TX Link Integrity and Auto-Negotiation Solution.............................. 41 6.1.6 Auto 10/100 Mbps Speed Selection ................................................................. 41 6.2 10BASE-T Functionality ................................................................................................... 41 6.2.1 10BASE-T Transmit Clock Generation............................................................. 41 6.2.2 10BASE-T Transmit Blocks.............................................................................. 42 6.2.3 10BASE-T Receive Blocks............................................................................... 42 6.2.4 10BASE-T Collision Detection.......................................................................... 43 6.2.5 10BASE-T Link Integrity ................................................................................... 43 6 ...
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... Register 27: PHY Unit Special Control Bit Definitions .....................................71 10. ELECTRICAL AND TIMING SPECIFICATIONS ..........................................................................73 10.1 Absolute Maximum Ratings ..............................................................................................73 10.2 DC Specifications ............................................................................................................73 10.3 AC Specifications .............................................................................................................76 10.4 Timing Specifications........................................................................................................77 10.4.1 Clocks Specifications .......................................................................................77 10.4.2 Timing Parameters ...........................................................................................78 12. PACKAGE AND PINOUT INFORMATION ...................................................................................85 12.1 Package Information.........................................................................................................85 12.2 Pinout Information ............................................................................................................86 12.2.1 GD82559ER Pin Assignments ........................................................................86 12.2.2 GD82559ER Ball Grid Array Diagram .............................................................88 Datasheet Networking Silicon — GD82559ER v ...
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... GD82559ER — Networking Silicon vi Datasheet ...
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... Advanced Power Management (APM) Specification, Intel Corporation and Microsoft Corporation. • 82559 Fast Ethernet Multifunction PCI/CardBus Controller Datasheet, Intel Corporation. • LAN On Motherboard (LOM) Design Guide Application Note (AP-391), Intel Corporation. • Test Access Port Applications Note (AP-393), Intel Corporation. Datasheet Networking Silicon — GD82559ER 1 ...
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... GD82559ER — Networking Silicon 2 Datasheet ...
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... Receive Unit and Command Unit which includes transmit functions. These two units Datasheet Local Memory Interface PCI Target and 3 Kbyte Flash/EEPROM Tx FIFO Interface FIFO Control Micro- machine 3 Kbyte Dual Rx FIFO Ported FIFO Figure 1. 82559ER Block Diagram Networking Silicon — GD82559ER 100BASE-TX/ 10/100 Mbps 10BASE-T CSMA/CD Interface PHY 3 ...
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... GD82559ER — Networking Silicon operate independently. Control is switched between the two units according to the microcode instruction flow. The independence of the Receive and Command units in the micromachine allows the 82559ER to interleave commands and receive incoming frames, with no real-time CPU intervention. The 82559ER contains an interface to an external Flash memory, and external serial EEPROM. ...
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... Half Duplex, 10BASE-T Full Duplex, and 10BASE-T Half Duplex. It also supports three LED pins to indicate link status, network activity, and speed.The 82559ER does not support external PHY devices and does not expose its internal MII bus. Datasheet Networking Silicon — GD82559ER 5 ...
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... GD82559ER — Networking Silicon 6 Datasheet ...
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... TRDY# is asserted on a read transaction.Once PAR is valid, it remains valid until one clock after the completion of the current data phase. The master drives PAR for address and write data phases; and the target, for read data phases. Networking Silicon —GD82559ER Description 7 ...
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... GD82559ER — Networking Silicon 3.2.2 Interface Control Signals Symbol FRAME# IRDY# TRDY# STOP# IDSEL DEVSEL# REQ# GNT# INTA# SERR# PERR# 8 Type Name and Function Cycle Frame. The cycle frame signal is driven by the current master to indicate the beginning and duration of a transaction. FRAME# is ...
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... During EEPROM accesses, it acts as the serial shift clock output to the EEPROM. Flash Address[14]/EEPROM Data Output. During Flash accesses, this multiplexed pin acts as the Flash Address [14] output signal. IN/OUT During EEPROM accesses, it acts as serial input data to the EEPROM Data Output signal. Networking Silicon —GD82559ER . cc 9 ...
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... GD82559ER — Networking Silicon Symbol FLA[13]/ EEDI FLA[12:8] FLA[7]/ CLKENB FLA[6:2] FLA[1]/ AUXPWR FLA[0] EECS FLCS# FLOE# FLWE# 3.4 Testability Port Signals Symbol TEST TCK TI TEXEC TO 10 Type Name and Function Flash Address[13]/EEPROM Data Input. During Flash accesses, this multiplexed pin acts as the Flash Address [13] output signal. ...
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... Voltage Reference. This pin is connected to a 1.25 V ± 1% external B voltage reference generator. To use the internal voltage reference source, this pin should be left floating. for the RBIAS100 and RBIAS10, respectively, are only a recommended values and Networking Silicon —GD82559ER pull- pull-down 11 ...
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... GD82559ER — Networking Silicon 12 Datasheet ...
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... GD82559ER Media Access Control Functional Description 4.1 82559ER Initialization The 82559ER has four sources for initialization. They are listed according to their precedence: 1. ALTRST# Signal 2. PCI RST# Signal 3. Software Reset (Software Command) 4. Selective Reset (Software Command) 4.1.1 Initialization Effects on 82559ER Units The following table shows the effect of each of the different initialization sources on major portions of the 82559ER ...
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... GD82559ER — Networking Silicon 4.2 PCI Interface 4.2.1 82559ER Bus Operations After configuration, the 82559ER is ready for normal operation Fast Ethernet controller, the role of the 82559ER is to access transmitted data or deposit received data. In both cases the 82559ER bus master device, will initiate memory cycles via the PCI bus to fetch or deposit the required data ...
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... IRDY#. The 82559ER Datasheet CLK FRAME# AD ADDR DATA C/BE# I/O RD BE# IRDY# TRDY# DEVSEL# STOP# Figure 2. CSR I/O Read Cycle CLK FRAME# AD ADDR DATA C/BE# I/O WR BE# IRDY# TRDY# DEVSEL# STOP# Figure 3. CSR I/O Write Cycle Networking Silicon — GD82559ER ...
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... GD82559ER — Networking Silicon controls the TRDY# signal and asserts it from the data access. The 82559ER allows the CPU to issue only one I/O write cycle to the Control/Status Registers, generating a disconnect by asserting the STOP# signal. This is true for both memory mapped and I/O mapped accesses. ...
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... MEM WR BE# Figure 5. Flash Buffer Write Cycle the control lines and IRDY# IRDY# , the 82559ER signals the CPU that the current data access has completed. Networking Silicon — GD82559ER the command and AD[31:0 also provides the FRAME# . The 82559ER controls the TRDY# 17 ...
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... GD82559ER — Networking Silicon Note: The 82559ER is considered the target in the above diagram; thus, TRDY# is not asserted. 4.2.1.1.4 Error Handling Data Parity Errors: The 82559ER checks for data parity errors while it is the target of the transaction error was detected, the 82559ER always sets the Detected Parity Error bit in the PCI Configuration Status register, bit 15 ...
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... The length of a burst is bounded by the system and the 82559ER’s internal FIFO. The length of a read burst may also be bounded by the value of the Transmit DMA Maximum Byte Count in the Configure command. The Transmit DMA Maximum Datasheet Networking Silicon — GD82559ER ...
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... GD82559ER — Networking Silicon Byte Count value indicates the maximum number of transmit DMA PCI cycles that will be completed after an 82559ER internal arbitration. (Details on the Configure command are described in the Software Developer’s Manual.) The 82559ER, as the initiator, drives the address lines AD[31:0], the command and byte enable lines C/BE#[3:0] and the control lines IRDY# and FRAME# ...
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... When the arbitration counter’s feature is enabled (in other words, the Transmit DMA Maximum Byte Count value is set in the Configure command), the 82559ER switches to other pending DMAs on the cache line boundary only. Note the following: Datasheet Networking Silicon — GD82559ER 21 ...
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... GD82559ER — Networking Silicon • This feature is not recommended for use in non-cache line oriented systems since it may cause shorter bursts and lower performance. • This feature should be used only when the CLS register in PCI Configuration space is set Dwords. • ...
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... The 82559ER will not attempt to keep the link alive by transmitting idle symbols or link 1 integrity pulses. The sub-10 mA state due to an invalid link can be enabled or disabled by a configuration bit in the Power Management Driver Register (PMDR). Datasheet Networking Silicon — GD82559ER state, cold Section 4.2.5, “Wake-up Events” 23 ...
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... GD82559ER — Networking Silicon 4.2.4.4 D3 Power State In the D3 power state, the 82559ER has the same capabilities and consumes the same amount of power as it does in the D2 state. However, it enables the PCI system the B3 state. If the PCI system is in the B3 state (in other words, no PCI power is present), the 82559ER provides wake-up capabilities connected to an auxiliary power source in the system ...
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... RST# and CLK signals. It also tri-states all PCI outputs, except the PME# signal. In the transition to an active PCI power state (in other words, from B3 power state to B0 power state), the PCI power good signal shifts high. Datasheet Networking Silicon — GD82559ER Link 82559ER Functionality • ...
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... GD82559ER — Networking Silicon In a LAN on Motherboard solution, the PCI power good signal is supplied by the system. In network adapter implementations, the PCI power good signal can be either generated locally using an external analog device, or connected directly to the PCI reset signal. In designs, that use both the ISOLATE# and RST# pins of the 82559ER, the PCI power good signal should envelope ISOLATE#, as shown below ...
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... This allows the 82559ER to handle various packet types. In general, the 82559ER supports programmable filtering of any packet in the first 128 bytes. Datasheet power state D3 power state Internal reset due to ISOLATE# Figure 10. 82559ER Initialization upon PCI RST# and ISOLATE# 55.) Networking Silicon — GD82559ER 640 ns 640 ns Section 7.1.19, “Power Management 27 ...
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... GD82559ER — Networking Silicon 4.2.5.2 Link Status Change Event The 82559ER link status indication circuit is capable of issuing a PME on a link status change from a valid link to an invalid link condition or vice versa. The 82559ER reports a PME link status event in all power states. The PME# signal is gated by the PME Enable bit in the PMCSR and the CSMA Configure command, which is described in the Software Developer’ ...
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... Figure 11. 64 Word EEPROM Read Instruction Waveform Figure Byte 2 IA Byte 4 IA Byte Rev ID 1b Subsystem ID Subsystem Vendor ID Reserved Figure 12. 82559ER EEPROM Format Networking Silicon — GD82559ER 12 Byte 1 ...
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... GD82559ER — Networking Silicon Note that word 0Ah contains several configuration bits. Bits from word 0Ah, FBh through FEh, and certain bits from word 0Dh are described as follows: Word Bits 5:14 Signature 13 Reserved 12 Reserved 11 Boot Disable 10:8 Revision ID 7 Reserved 6 Deep Power Down ...
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... The 82559ER supports the reception of long frames, specifically frames longer than 1518 bytes, including the CRC, if software sets the Long Receive OK bit in the Configuration command (described in the Software Developer’s Manual). Otherwise, “long” frames are discarded. Datasheet Networking Silicon — GD82559ER 31 ...
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... GD82559ER — Networking Silicon 4.6 Media Independent Interface (MII) Management Interface The MII management interface allows the CPU to control the PHY unit via a control register in the 82559ER. This allows the software driver to place the PHY in specific modes such as full duplex, loopback, power down, etc., without the need for specific hardware pins to select the desired mode. ...
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... The 85/85 test provides the same functionality to the board level designer as the Tristate mode. This mode is normal used during chip the chip burn-in cycling. The 82559ER is placed in this o mode during the 85 TEXEC = ‘ ‘1 Datasheet /85% humidity test cycling. Test Pin Combinations: TEST = ‘1, TCK = ‘0, Networking Silicon — GD82559ER 33 ...
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... GD82559ER — Networking Silicon 5.5 TriState This command set all 82559ER Input and Output pins into a TRI-state (HIGH-Z) mode, all internal pull-ups and pull-downs are disabled. This mode is entered by setting the following Test Pin Com- binations: TEST = ‘1, TCK = ‘0, TEXEC = ‘0, 5 ...
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... NAND-Tree Output Datasheet Networking Silicon — GD82559ER Table 2. Nand - Tree Chains Chain 1 STOP# GNT# PERR# PAR AD16 C/BE1# AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 C/BE0# AD7 AD6 AD5 AD4 ...
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... GD82559ER — Networking Silicon 36 Datasheet ...
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... GD82559ER Physical Layer Functional Description 6.1 100BASE-TX PHY Unit 6.1.1 100BASE-TX Transmit Clock Generation A 25 MHz crystal MHz oscillator is used to drive the PHY unit’s X1 and X2 pins. The PHY unit derives its internal transmit digital clocks from this crystal or oscillator input. The internal Transmit Clock signal is a derivative of the 25 MHz internal clock. The accuracy of the external crystal or oscillator must be ± ...
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... GD82559ER — Networking Silicon Symbol 6.1.2.2 100BASE-TX Scrambler and MLT-3 Encoder Data is scrambled in 100BASE-TX to reduce electromagnetic emissions during long transmissions of high-frequency data codes. The scrambler logic accepts 5 bits from the 4B/5B encoder block and presents the scrambled data to the MLT-3 encoder. The PHY unit implements the 11-bit stream cipher scrambler as adopted by the ANSI XT3T9 ...
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... TP-PMD specification. The same magnetics used for 100BASE-TX mode should also work in 10BASE-T mode. The following is a list of current magnetics modules available from several vendors: Vendor Delta Pulse Engineering Pulse Engineering Datasheet Networking Silicon — GD82559ER ...
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... GD82559ER — Networking Silicon 6.1.3 100BASE-TX Receive Blocks The receive subsection of the PHY unit accepts 100BASE-TX MLT-3 data on the receive differential pair. Due to the advanced digital signal processing design techniques employed, the PHY unit will accurately receive valid data from Category-5 (CAT5) UTP and Type 1 STP cable of length well in excess of 100 meters ...
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... Functionality 6.2.1 10BASE-T Transmit Clock Generation The 20 MHz and 10 MHz clocks needed for 10BASE-T are synthesized from the external 25 MHz crystal or oscillator. The PHY unit provides the transmit clock and receive clock to the internal MAC at 2.5 MHz. Datasheet Networking Silicon — GD82559ER 41 ...
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... GD82559ER — Networking Silicon 6.2.2 10BASE-T Transmit Blocks 6.2.2.1 10BASE-T Manchester Encoder After the 2.5 MHz clocked data is serialized Mbps serial stream, the 20 MHz clock performs the Manchester encoding. The Manchester code always has a mid-bit transition. If the value is 1b then the transition is from low to high. If the value is 0b then the transition is from high to low. The boundary transition occurs only when the data changes from bit to bit. For example, if the value is 10b, then the change is from high to low ...
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... An Auto-Negotiation capable device can detect and automatically configure its port to take maximum advantage of common modes of operation without user intervention or prior knowledge by either station. The possible common modes of operation are: 100BASE-TX, 100BASE-TX Full Duplex, 10BASE-T, and 10BASE-T Full Duplex. Datasheet Networking Silicon — GD82559ER 43 ...
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... GD82559ER — Networking Silicon 6.3.1 Description Auto-Negotiation selects the fastest operating mode (in other words, the highest common denominator) available to hardware at both ends of the cable. A PHY’s capability is encoded by bursts of link pulses called Fast Link Pulses (FLPs). Connection is established by FLP exchange and handshake during link initialization time. Once the link is established by this handshake, the native link pulse scheme resumes (that is, 10BASE-T or 100BASE-TX link pulses) ...
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... Parallel Detection 10Base-T or 100Base-TX Link Ready Look at Link Pulse; LINK PASS Auto-Negotiation Complete bit set Figure 15. Auto-Negotiation and Parallel Detect provides possible schematic diagrams for configurations using two and three Networking Silicon — GD82559ER Auto-Negotiation FLP capable Auto-Negotiation capable = 1 Ability Match 45 ...
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... GD82559ER — Networking Silicon 82559ER SpeedLED 46 LILED LILED Figure 16. Two and Three LED Schematic Diagram Datasheet ...
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... Reserved Base Address Register Reserved Expansion ROM Base Address Register Reserved Reserved Min_Gnt Interrupt Pin Next Item Ptr Data Power Management CSR Figure 17. PCI Configuration Registers Networking Silicon — GD82559ER Vendor ID 00H Command 04H Revision ID 08H Cache Line Size 0CH 10H 14H ...
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... GD82559ER — Networking Silicon 7.1.2 PCI Command Register The 82559ER Command register at word address 04h in the PCI configuration space provides control over the 82559ER’s ability to generate and respond to PCI cycles register, the 82559ER is logically disconnected from the PCI bus for all accesses except ...
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... Bits Name 31 Detected Parity Error 30 Signaled System Error Received Master 29 Abort 28 Received Target Abort 27 Signaled Target Abort 26:25 DEVSEL# Timing Datasheet Networking Silicon — GD82559ER Figure 19. PCI Status Register Table 6 ...
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... GD82559ER — Networking Silicon Bits Name 24 Parity Error Detected 23 Fast Back-to-Back 20 Capabilities List 19:16 Reserved 7.1.4 PCI Revision ID Register The Revision 8-bit read only register with a default value of 08h for the 82559ER. The three least significant bits of the Revision ID can be overridden by the ID and Revision ID fields in the EEPROM (Section 4.4, “ ...
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... Prefetchable Set 82559ER Type 00 - locate anywhere in 32-bit address space 01 - locate below 1 Mbyte 10 - locate anywhere in 64-bit address space 11 - reserved Memory space indicator Datasheet Networking Silicon — GD82559ER Base Address Figure 21. Base Address Register for Memory Mapping ...
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... GD82559ER — Networking Silicon 31 Reserved I/O space indicator Note: Bit 0 in all base registers is read only and used to determine whether the register maps into memory or I/O space. Base registers that map to memory space must return bit 0. Base registers that map to I/O space must return 1b in bit 0. ...
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... PCI interrupt request pin (as defined in the Interrupt Pin register) is routed to. Datasheet below. Table 7. 82559ER ID Fields Programming Device ID Vendor ID Revision ID 1209H 8086H 09H 1209H 8086H 09H 1209H 8086H Word AH, bits 10:8 17. Networking Silicon — GD82559ER Subsystem Subsystem ID Vendor ID 0000H 0000H (Default) (Default) Word BH Word CH Word BH Word CH Section 53 ...
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... GD82559ER — Networking Silicon 7.1.13 Interrupt Pin Register The Interrupt Pin register is read only and defines which of the four PCI interrupt request pins, INTA# through INTD#, a PCI device is connected to. The 82559ER is connected the INTA# pin. 7.1.14 Minimum Grant Register The Minimum Grant (Min_Gnt) register is an optional read only register for bus masters and is not applicable to non-master devices ...
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... Reserved. These bits are reserved and should be set to 00b. Read/Write Power State. This 2-bit field is used to determine the current power state of the 82559ER and to set the 82559ER into a new power state. The definition of the field values is as follows Networking Silicon — GD82559ER Description Description 55 ...
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... GD82559ER — Networking Silicon 7.1.20 Data Register The data register is an 8-bit read only register that provides a mechanism for the 82559ER to report state dependent maximum power consumption and heat dissipation. The value reported in this register depends on the value written to the Data Select field in the PMCSR register. The power measurements defined in this register have a dynamic range ...
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... The PORT interface allows the CPU to reset the 82559ER, force the 82559ER to dump information to main memory, or perform an internal self test. The Flash Control register allows the CPU to enable writes to an external Flash. an external EEPROM. Networking Silicon — GD82559ER Lower Word D0 Offset SCB Status Word 00H ...
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... GD82559ER — Networking Silicon MDI Control Register: Receive DMA Byte Count: Flow Control Register: PMDR: General Control: General Status: 8.1.1 System Control Block Status Word The System Control Block (SCB) Status Word contains status information relating to the 82559ER’s Command and Receive units. ...
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... MDI. Bits 31:30 These bits are reserved and should be set to 00b. Datasheet Networking Silicon — GD82559ER Description Specific Interrupt Mask. Setting this bit to 1b causes the 82559ER to stop generating an interrupt (in other words, de-assert the INTA# signal) on the corresponding event. ...
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... GD82559ER — Networking Silicon Bits Interrupt Enable. When this bit is set software, the 82559ER asserts an interrupt to 29 indicate the end of an MDI cycle. Ready. This bit is set the 82559ER at the end of an MDI transaction. It should be 28 reset software at the same time the command is written. ...
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... Duplex Mode. This bit indicates the wire duplex mode: full duplex (1b) or half duplex (0b). Read Only Speed. This bit indicates the wire speed: 100 Mbps (1b Mbps (0b). Read Only Link Status Indication. This bit indicates the status of the link: valid (1b) or invalid (0b). Networking Silicon — GD82559ER Description Description Description 61 ...
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... GD82559ER — Networking Silicon 8.2 Statistical Counters The 82559ER provides information for network management statistics by providing on-chip statistical counters that count a variety of events associated with both transmit and receive. The counters are updated by the 82559ER when it completes the processing of a frame (that is, when it has completed transmitting a frame on the link or when it has completed receiving a frame) ...
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... This counter contains the number of MAC Control frames received by the 82559ER that are not Flow Control Pause frames. These frames are valid MAC control frames that have the predefined MAC control Type value and a valid address but has an unsupported opcode. Networking Silicon — GD82559ER Description 63 ...
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... GD82559ER — Networking Silicon 64 Datasheet ...
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... Enable 11 Power-Down 10 Reserved Datasheet Networking Silicon — GD82559ER Description This bit sets the status and control register of the PHY to their default states and is self-clearing. The PHY returns a value of one until the reset process has completed and accepts a read or write transaction PHY Reset This bit enables loopback of transmit data nibbles from the TXD[3:0] signals to the receive data path ...
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... GD82559ER — Networking Silicon Bit(s) Name 9 Restart Auto- Negotiation 8 Duplex Mode 7 Collision Test 6:0 Reserved 9.1.2 Register 1: Status Register Bit Definitions Bit(s) Name 15 Reserved 14 100BASE-TX Full Duplex 13 100 Mbps Half Duplex 12 10 Mbps Full Duplex 11 10 Mbps Half Duplex 10:7 Reserved 6 Management Frames Preamble ...
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... Acknowledge 13 Remote Fault 12:5 Technology Ability Field 4:0 Selector Field Datasheet Networking Silicon — GD82559ER Description Value: 02A8H Description Value: 0154H Description Constant 0 = Transmitting primary capability data page This bit is reserved and should be set to 0b Indicate link partner’s remote fault remote fault ...
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... GD82559ER — Networking Silicon 9.1.7 Register 6: Auto-Negotiation Expansion Register Bit Definitions Bit(s) Name 15:5 Reserved 4 Parallel Detection Fault 3 Link Partner Next page Able 2 Next Page Able 1 Page Received 0 Link Partner Auto- Negotiation Able 9.2 MDI Registers Registers eight through fifteen are reserved for IEEE. ...
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... Squelch Disable 2 Extended Squelch 1 Link Integrity Disable Datasheet Networking Silicon — GD82559ER Description This bit indicates 10BASE-T polarity Reverse polarity 0 = Normal polarity These bits are reserved and should be set to 0B. This bit indicates the Auto-Negotiation result 100 Mbps Mbps This bit indicates the Auto-Negotiation result. ...
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... GD82559ER — Networking Silicon Bit(s) Name 0 Jabber Function Disable 9.3.3 Register 18: PHY Address Register Bit(s) Name 15:5 Reserved 4:0 PHY Address 9.3.4 Register 19: 100BASE-TX Receive False Carrier Counter Bit Definitions Bit(s) Name 15:0 Receive False Carrier 9.3.5 Register 20: 100BASE-TX Receive Disconnect Counter Bit Definitions Bit(s) Name 15:0 Disconnect Event 9 ...
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... Reserved 2:0 LED Switch Control Datasheet Networking Silicon — GD82559ER Description This field contains a 16-bit counter that increments for each premature end of frame event. The counter freezes when full and self-clears on read. Description This is a 16-bit counter that increments for each end of frame error event ...
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... GD82559ER — Networking Silicon 72 Datasheet ...
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... IPDP I Input Leakage Current ILP Datasheet Table 15. General DC Specifications Condition PCI and maximum link activity. CC Table 16. PCI Interface DC Specifications Parameter Condition 0 < V < Networking Silicon — GD82559ER Min Typical Max Units Notes 3.0 3.3 3.5 V 4.75 5.0 5.25 V 125 195 mA = 3.3 V) and average link activity. ...
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... GD82559ER — Networking Silicon V Output High Voltage OHP V Output Low Voltage OLP C Input Pin Capacitance INP C CLK Pin Capacitance CLKP C IDSEL Pin Capacitance IDSEL L Pin Inductance PINP NOTES: 1. These values are only applicable in 3.3 V signaling environments. Outside of this limit the input buffer must consume its minimum current ...
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... Figure 24. RBIAS100 Resistance Versus Transmitter Current pins (V = 3.3 V Table 20. 10BASE-T Voltage/Current Characteristics Condition Min 10 MHz 10 5 MHz f 10 MHz ±585 5 MHz f 10 MHz 100 2.2 RBIAS10 = 549 Networking Silicon — GD82559ER ±100 1.00 1. Icct100 21mA Typical Max Units Notes K ±440 ± ...
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... GD82559ER — Networking Silicon 10.3 AC Specifications Symbol Parameter Switching Current High I OH(AC) (Test Point) Switching Current Low I OL(AC) (Test Point) Low Clamp I CL Current High Clamp I CH Current PCI Output Rise slew RP Slew Rate PCI Output Fall slew FP Slew Rate NOTES: 1. Switching Current High specifications are not relevant to PME#, SERR#, or INTA#, which are open drain outputs ...
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... Table 22. PCI Clock Specifications Parameter Min CLK Cycle Time 30 CLK High Time 11 CLK Low Time 11 CLK Slew Rate 1 Table 23. X1 Clock Specifications Parameter Min X1 Duty Cycle 40% X1 Period Networking Silicon — GD82559ER shows the clock waveform and required 0.4V p-to-p CC (minimum) CC Max Units Notes V/ns 2 Figure 26 ...
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... GD82559ER — Networking Silicon 10.4.2 Timing Parameters 10.4.2.1 Measurement and Test Conditions Figure 27, Figure 28, and done. The component test guarantees that all timings are met with minimum clock slew rate (slowest edge) and voltage swing. The design must guarantee that minimum timings are also met with maximum clock slew rate (fastest edge) and voltage swing ...
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... PCI Input Setup Time to CLK (point-to- point) Input Hold Time from CLK Reset Active Time After Power Stable PCI Reset Active Time After CLK Stable Reset Active to Output Float Delay Figure 27. Figure 28. 29. Networking Silicon — GD82559ER 0.325V V Min Delay CC 0.475V V Max Delay CC 0.475V V Min Delay CC 0 ...
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... GD82559ER — Networking Silicon Symbol T35 t flrwc T36 t flacc T37 t flce T38 t floe T39 t fldf T40 t flas T41 t flah T42 t flcs T43 t flch T44 t flds T45 t fldh T46 t flwp T47 t flwph T48 t Mioha T49 t Miohi NOTES: 1. These timing specifications apply to Flash read cycles. The Flash timings referenced are 28F020-150 timings ...
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... Table 27. EEPROM Timing Parameters Parameter Serial Clock Frequency Delay from EECS High to EESK High Delay from EESK Low to EECS Low Setup Time of EEDI to EESK Hold Time of EEDI after EESK EECS Low Time Networking Silicon — GD82559ER Data In Table 27 Min Max Units Notes ...
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... GD82559ER — Networking Silicon 10.4.2.5 PHY Timings Symbol T56 T nlp_wid T57 T nlp_per Normal Link Pulse Symbol T58 T flp_wid T59 T flp_clk_clk T60 T flp_clk_dat T61 T flp_bur_num T62 T flp_bur_wid T63 T flp_bur_per Figure 30 ...
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... Fast Link Pulse FLP Bursts Symbol T64 T jit Datasheet Networking Silicon — GD82559ER T59 T60 T58 Clock Pulse Data Pulse T63 T62 Figure 32. Auto-Negotiation FLP Timings Table 30. 100Base-TX Transmitter AC Specification Parameter Condition TDP/TDN Differential HLS Data Output Peak Jitter Clock Pulse ...
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... GD82559ER — Networking Silicon 84 Datasheet ...
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... Package and Pinout Information 12.1 Package Information The GD82559ER is a 196-pin Ball Grid Array (BGA) package. Package dimensions are shown in Figure 24. More information on Intel device packaging is available in the Intel Packaging Handbook, which is available from the Intel Literature Center or your local Intel sales office. ...
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... B10 B13 C10 C13 D10 D13 E10 E13 F10 F13 G10 G13 86 Table 15. GD82559ER Pin Assignments Name Pin Name NC A2 SERR# IDSEL A5 AD25 VCC A8 AD30 NC A11 TEST A14 AD22 B2 AD23 AD24 B5 AD26 VSSPP B8 AD31 NC B11 SPEEDLED ...
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... K13 L10 L13 M10 FLA15/EESK M13 N10 FLA14/EEDO N13 P10 FLA13/EEDI P13 Datasheet Table 15. GD82559ER Pin Assignments Name Pin Name STOP# H2 INTA VCC VCC H8 VCC VSS H11 VSS FLD5 H14 FLD4 PAR J2 PERR VCC VCC ...
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... Figure 25. GD82559ER Ball Grid Array Diagram ...