MACH110-15JC Advanced Micro Devices, MACH110-15JC Datasheet

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MACH110-15JC

Manufacturer Part Number
MACH110-15JC
Description
High-density EE CMOS programmable logic, 32 macrocells, 32 flip-flops, 2 clock choices, 38 Inputs, 32 Outputs, 15ns
Manufacturer
Advanced Micro Devices
Datasheet

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MACH110-12/15/20
High-Density EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
The MACH110 is a member of AMD’s high-performance
EE CMOS MACH 1 family. This device has approxi-
mately three times the logic macrocell capability of the
popular PAL22V10 without loss of speed.
The MACH110 consists of two PAL blocks intercon-
nected by a programmable switch matrix. The two PAL
blocks are essentially “PAL22V16” structures complete
with product-term arrays and programmable macro-
cells. The switch matrix connects the PAL blocks to
each other and to all input pins, providing a high degree
of connectivity between the fully-connected PAL blocks.
This allows designs to be placed and routed efficiently.
44 Pins
32 Macrocells
12 ns t
14 ns t
77 MHz f
38 Inputs
PD
PD
CNT
FINAL
Commercial
Industrial
COM’L: -12/15/20
The MACH110 macrocell provides either registered or
combinatorial outputs with programmable polarity. If a
registered configuration is chosen, the register can be
configured as D-type or T-type to help reduce the
number of product terms. The register type decision can
be made by the designer or by the software. All
macrocells can be connected to an I/O cell. If a buried
macrocell is desired, the internal feedback path from the
macrocell can be used, which frees up the I/O pin for use
as an input.
32 Outputs
32 Flip-flops; 2 clock choices
2 “PAL22V16” Blocks
Pin-compatible with MACH111, MACH210,
MACH211, MACH215
IND: -14/18/24
Publication# 14127
Issue Date: May 1995
Rev. I
Advanced
Devices
Amendment /0
Micro

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MACH110-15JC Summary of contents

Page 1

... EE CMOS MACH 1 family. This device has approxi- mately three times the logic macrocell capability of the popular PAL22V10 without loss of speed. The MACH110 consists of two PAL blocks intercon- nected by a programmable switch matrix. The two PAL blocks are essentially “PAL22V16” structures complete with product-term arrays and programmable macro- cells ...

Page 2

... Cells 16 16 Macrocells AND Logic Array and Logic Allocator 22 Switch Matrix AND Logic Array and Logic Allocator OE 2 Macrocells 16 16 I/O Cells 16 16 CLK I/O – I CLK MACH110-12/15/20 – – 14127I-1 ...

Page 3

... CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V = Supply Voltage CC PLCC MACH110-12/15/20 AMD I CLK GND 14127I-2 3 ...

Page 4

... The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. MACH110-12/15/20 (Com’l) OPTIONAL PROCESSING Blank = Standard Processing OPERATING CONDITIONS C = Commercial ( +70 C) ...

Page 5

... The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. MACH110-14/18/25 (Ind) AMD OPTIONAL PROCESSING Blank = Standard Processing OPERATING CONDITIONS I = Industrial (– +85 C) ...

Page 6

... I/O cells; the other two control the last eight macrocells. The Logic Allocator The logic allocator in the MACH110 takes the 64 logic product terms and allocates them to the 16 macrocells as needed. Each macrocell can be driven product terms. The design software automatically configures the logic allocator when fitting the design into the device ...

Page 7

... Switch Matrix Figure 1. MACH110 PAL Block MACH110-12/15/20 AMD Output Enable Output Enable Asynchronous Reset Asynchronous Preset I/O Cell Output M Macro 0 Cell I/O Cell Output M Macro 1 Cell I/O Cell Output M 2 Macro Cell ...

Page 8

... OUT (Note 0 Max (Note 3) OUT = MHz (Note 4) and I (or I and OZL IH OZH MACH110-12/15/20 (Com’ + +4. +5.25 V Min Typ Max Unit 2.4 V 0.5 V 2 – –10 A – ...

Page 9

... T-type LOW 6 HIGH 66.7 D-type + 62.5 T-type D-type 76.9 ) CNT T-type 71.4 1/( 83 MACH110-12/15/20 (Com’l) AMD Typ Unit -15 -20 Min Max Min Max Unit ...

Page 10

... VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) VCC = MHz (Note 4) and I (or I and OZL IH OZH MACH110-14/18/20 (Ind – +5.5 V Min Typ Max Unit 2 ...

Page 11

... Min Max 14.5 8.5 D-type T-type 7.5 LOW 7.5 HIGH 53.5 D-type + T-type D-type 61.5 ) CNT T-type 57 1/( 66 19.5 14.5 10 19.5 14.5 10 14.5 14.5 MACH110-14/18/20 (Ind) AMD Typ Unit -18 -24 Min Max Min Max Unit 13 14 MHz 38 30 ...

Page 12

... Output, LOW I (mA –3 –2 –1 –25 –50 –75 –100 –125 –150 Output, HIGH I (mA –2 – –20 –40 –60 –80 –100 Input MACH110-12/15/ 1.0 14127I (V) OH 14127I 14127I-6 ...

Page 13

... The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register Frequency (MHz) MACH110-12/15/20 AMD MACH110 14127I-7 13 ...

Page 14

... Furthermore, jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. 14 200 lfpm air 400 lfpm air 600 lfpm air 800 lfpm air MACH110-12/15/20 Typ PLCC Unit 14 C/W 39 ...

Page 15

... WL 14127I- Registered Input t HIR Input V T Register Clock t ICO V T Output Register Clock 14127I-13 Input Register to Output Register Setup MACH110-12/15/20 AMD V T 14127I PDL 14127I-10 Latched Output (MACH 2, 3, and GWS 14127I-12 Gate Width (MACH 2, 3, and 4) ...

Page 16

... T 2. Input pulse amplitude 3 Input rise and fall times 2 ns–4 ns typical SIL HIL IGO V T 14127I-15 Latched Input (MACH 2 and 4) t PDLL V T Latched Input and Output (MACH 2, 3, and 4) MACH110-12/15/ SLL V T 14127I-16 ...

Page 17

... WICL 14127I-17 Input, I/ Feedback Registered V T Output t ARR Clock V T 14127I- 0. 0.5V OL Output Disable/Enable MACH110-12/15/20 AMD WIGL 14127I-18 Input Latch Gate Width (MACH 2 and 4) t APW APR V 14127I-20 Asynchronous Preset 14127I-21 ...

Page 18

... State Permitted Unknown Does Not Center Apply Line is High- Impedance “Off” State Output Commercial 300 390 5 pF MACH110-12/15/20 KS000010-PAL Test Point 14127I-22 Measured Output Value 2 1 – ...

Page 19

... All frequencies except f MAX other measured AC parameters. f ured directly. (SECOND CHIP SIR + MACH110-12/15/20 AMD + t ). However type is the mini- MAX + t ). Usually, this minimum WH WL MAX no feedback.” . Because this involves no MAXIR no feed- MAX + the sum of ...

Page 20

... Min Pattern Data Retention Time Max Reprogramming Cycles 20 bipolar parts result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. Min Units 10 Years 20 Years 100 Cycles MACH110-12/15/20 Test Conditions Max Storage Temperature Max Operating Temperature Normal Programming Conditions ...

Page 21

... INPUT/OUTPUT EQUIVALENT SCHEMATICS ESD Protection Input 100 k Preload Feedback Circuitry Input I/O MACH110-12/15/20 AMD 100 14127I-24 21 ...

Page 22

... Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met Power-Up Reset Waveform MACH110-12/15/20 can rise to its steady state, two CC Max Unit 10 s See Switching Characteristics V ...

Page 23

... All MACH 2 devices support both preload and observability. Contact individual programming vendors in order to verify programmer support. On Preload Off Mode Figure 2. Preload/Reset Conflict Set Reset Figure 3. Combinatorial Latch MACH110-12/15/20 AMD Preloaded HIGH Preloaded HIGH 14127I-26 14127I-27 ...

Page 24

... PROsynthesis/AMD Software ComposerPIC (Requires MACH Fitter) Verilog, LeapFrog, RapidSim Simulators (Models also available from Logic Modeling) MacABEL (Requires SmartPart MACH Fitter) SmartCAT Circuit Analyzer ABEL (Requires MACH Fitter) (Requires MACH Fitter) SmartModel MACH110-12/15/20 Ver. 2.0 Software Software TM Designer Ver. 3.3 TM Software TM -5 Software Synario ...

Page 25

... Schematic Design Tool 386+ Digital Simulation Tools MultiSIM Interactive Simulator ViewPLD or PROPLD (Requires PROSim Simulator MACH Fitter) ViewSim Simulator (Models for ViewSim also available from Logic Modeling) TEST GENERATION SYSTEM TM ATGEN MACH110-12/15/20 AMD TM PLDSynthesis TM -XL Software TM SUSIE Simulator LASAR Test Generation Software ...

Page 26

... Hidden Creek Way, Suite H Cerritos, California 70703 (310) 926-6727 Advanced Micro Devices P.O. Box 3453, MS-1028 Sunnyvale, CA 94088-3453 (800) 222-9323 26 (subject to change) PROGRAMMER CONFIGURATION Pilot U84 BP1200 TM UniSite Model 3900 ALLPRO Sprint/Expert Stag Quazar Turpro-1 PROGRAMMER CONFIGURATION JTAG PROG MACHpro MACH110-12/15/20 AutoSite TM –88 ...

Page 27

... Santa Clara, CA 95051 (408) 982-0660 Logical Systems Corp. P.O. Box 6184 Syracuse, NY 13217-6184 (315) 478-0722 Procon Technologies, Inc. 1333 Lawrence Expwy, Suite 207 Santa Clara, CA 95051 (408) 246-4456 (subject to change) PART NUMBER Contact Manufacturer Contact Manufacturer Contact Manufacturer Contact Manufacturer MACH110-12/15/20 AMD 27 ...

Page 28

... AMD, the AMD logo, MACH, and PAL are registered trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 28 .062 .083 .042 .056 .500 REF .009 .015 .090 .120 .165 .180 SIDE VIEW MACH110-12/15/20 .590 .630 .013 .021 SEATING PLANE 16-038-SQ PL 044 DA78 6-28-94 ae ...

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