CY7C1338-100AC Cypress Semiconductor Corporation., CY7C1338-100AC Datasheet
CY7C1338-100AC
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CY7C1338-100AC Summary of contents
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... Intel and Pentium are registered trademarks of Intel Corporation. Cypress Semiconductor Corporation Functional Description The CY7C1338 is a 3.3V, 128K by 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap- tures the first address in a burst and increments the address automatically for the rest of the burst access ...
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... 100-Lead TQFP CY7C1338 CY7C1338 DDQ V SSQ BYTE1 10 V SSQ V DDQ DDQ ...
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... The outputs are automatically [3:0] three-stated when a WRITE cycle is detected. Power supply inputs to the core of the device. Should be connected to 3.3V power supply. 3 CY7C1338 are also loaded into the burst [1:0] are also loaded into the burst [1:0] to select one of the 64K address loca- ...
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... Maximum access delay from the clock rise ( 7.5 ns (117-MHz device). CDV The CY7C1338 supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence ...
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... LOW. Leaving ZZ unconnected defaults the device into an ac- 00 tive state. Fourth Address , Test Conditions Min. ZZ > > < 0.2V 2t CYC 5 CY7C1338 , ADSP, and ADSC must remain after the ZZ input returns ZZREC Max. Unit CYC ns ...
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... CY7C1338 ADV WE OE CLK L-H High L-H High L-H High L-H High L-H High High L L-H High-Z ...
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... DC Input Voltage ........................................... –0. Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... >200 mA Operating Range Ambient [6] Range Temperature + 0.5V Com’l 0°C to +70° CY7C1338 ...
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... IN IN DDQ inputs static Max Device Deselected – 0. 0.3V, IN DDQ inputs switching MAX Max Device Deselected – 0. 0.3V inputs static 8 CY7C1338 Min. Max. 2.4 2.0 0.4 0.7 2 0.3V 1 0.3V –0.3 0.8 –0.3 0 –30 5 –5 30 –5 5 –300 8.5-ns cycle, 117 MHz ...
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... V = 5.0V DD R1=317 3.3V OUTPUT 3.0V R2=351 5 pF GND INCLUDING JIG AND SCOPE (b) [9] -117 Min. Max. Min. 8.5 10 3.0 4.0 3.0 4.0 2.0 2.0 0.5 0.5 7.5 2.0 2.0 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 3 [10, 12] 3.5 [10, 12 3.5 (min). CLZ 9 CY7C1338 Max. Unit ALL INPUT PULSES 90% 90% 10% 10% 3.0 ns 3.0 ns -100 -90 -50 Max. Min. Max. Min. Max. Unit 11 20 4.5 4.5 4.5 4.5 2.0 2.0 0.5 0.5 8.0 8.5 11.0 2.0 2.0 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 3.5 3.5 3 3.5 3.5 3 ...
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... GW to define a write cycle (see Write Cycle Descriptions table). [3:0] 14. WDx stands for Write Data to Address X. Burst Write ADSP ignored with CE inactive masks ADSP UNDEFINED = DON’T CARE 10 CY7C1338 Pipelined Write Unselected ADSC initiated write WD3 Unselected with CE 2 High-Z 3a ...
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... RDx stands for Read Data from Address X. Burst Read ADSP ignored with Suspend Burst ADH masks ADSP DOH DON’T CARE = UNDEFINED 11 CY7C1338 Unselected Pipelined Read inactive 1 ADSC initiated read RD3 Unselected with CHZ ...
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... C t ADH t ADVH t WES ADSP ignored with CE HIGH 1 t EOHZ Q(B) D(C) (B+2) (B+1) (B+3) , and GW to define a write cycle (see Write Cycle Descriptions table). [1:0] and CE . All chip selects need to be active in order to select CY7C1338 ADH t CEH t CEH t WEH Q(D) (C+1) (C+2) (C+3) t DOH t CHZ ...
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... ADH t CEH t WES ADSP ignored with CE HIGH 1 Q(D) , and GW to define a write cycle (see Write Cycle Descriptions table). [1:0] and CE . All chip selects need to be active in order to select UNDEFINED = DON’T CARE 13 CY7C1338 WEH D (E) D (F) D (H) D (G) D(C) t DOH t CHZ ...
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... Timing Diagrams (continued) OE Switching Waveforms OE t EOHZ three-state I/Os t EOV t EOLZ 14 CY7C1338 ...
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... ADSP HIGH ADSC CE 1 LOW CE 2 HIGH I/Os Note: 16. Device must be deselected when entering ZZ mode. See Cycle Description table for all possible signal conditions to deselect the device. 17. I/Os are in three-state when exiting ZZ sleep mode. t ZZS I (active CCZZ Three-state 15 CY7C1338 t ZZREC ...
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... Ordering Information Speed (MHz) Ordering Code 117 CY7C1338-117AC 100 CY7C1338-100AC 90 CY7C1338-90AC 50 CY7C1338-50AC Document #: 38-00722-B Package Diagram 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 © Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product ...