AD9886KS-100 Analog Devices, AD9886KS-100 Datasheet
AD9886KS-100
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AD9886KS-100 Summary of contents
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GENERAL DESCRIPTION The AD9886 is a complete 8-bit 140 MSPS monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations. Its 140 MSPS encode rate capability and full-power analog bandwidth of 330 MHz supports resolutions ...
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... DIGITAL OUTPUTS Output Voltage, High (V ) Full OH Output Voltage, Low (V ) Full OL Duty Cycle DATACK, DATACK Full Output Coding ( 3.3 V, ADC Clock = Maximum Conversion Rate Test AD9886KS-100 Level Min Typ Max 8 I ± 0.5 +1.15/–1.0 VI +1.15/–1.0 I ± 0.5 ± 1.4 VI ± 1.75 VI Guaranteed VI 0 ...
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... VCO Range = 01, Charge Pump Current = 001, PLL Divider = 1693. 3 VCO Range = 10, Charge Pump Current = 110, PLL Divider = 1600. 4 DEMUX = 1, DATACK and DATACK Load = 10 pF, Data Load = 5 pF. 5 Using external pixel clock. Specifications subject to change without notice. Test AD9886KS-100 Level Min Typ Max IV 3.0 3.3 3 ...
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... Temperature Package Model Range Description AD9886KS-140 0°C to 70°C Plastic Quad Flatpack AD9886KS-100 0°C to 70°C Plastic Quad Flatpack AD9886/PCB 25°C Evaluation Board CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9886 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges ...
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VDD 1 PIN 1 GND 2 IDENTIFIER GREEN A<7> 3 GREEN A<6> 4 GREEN A<5> GREEN A<4> GREEN A<3> GREEN A<2> GREEN A<1> 9 GREEN A<0> 10 VDD 11 GND 12 GREEN B<7> 13 GREEN B<6> ...
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AD9886 P in Pin Type Name Function Analog Video R Analog Input for Converter R AIN Inputs G Analog Input for Converter G AIN B Analog Input for Converter B AIN External HSYNC Horizontal SYNC Input Sync/Clock VSYNC Vertical SYNC ...
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PIN FUNCTION DETAIL Inputs R Analog Input for RED Channel AIN G Analog Input for GREEN Channel AIN B Analog Input for BLUE Channel AIN High-impedance inputs that accept the RED, GREEN, and BLUE channel graphics signals, respectively. (The three ...
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AD9886 Outputs D A Data Output, Red Channel, Port Data Output, Red Channel, Port Data Output, Green Channel, Port Data Output, Green Channel, Port B ...
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Power Supply V Main Power Supply D These pins supply power to the main ele- ments of the circuit. It should be as quiet and filtered as possible. V Digital Output Power Supply DD A large number of output pins ...
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AD9886 DESIGN GUIDE General Description The AD9886 is a fully integrated solution for capturing analog RGB signals and digitizing them for display on flat panel monitors or projectors. The circuit is ideal for providing a computer interface for HDTV monitors ...
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The clamp timing can be established by simply exercising the CLAMP pin at the appropriate time (with EXTCLMP = 1). The polarity of this signal is set by the Clamp Polarity bit. A simpler method of clamp timing employs the ...
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AD9886 Sync-on-Green The Sync-on-Green input operates in two steps. First, it sets a baseline clamp level from the incoming video signal with a negative peak detector. Second, it sets the sync trigger level to ~150 mV above the negative peak. ...
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Table II. VCO Frequency Ranges Pixel Clock PV1 PV0 Range (MHz 12– 35– 70–110 1 1 110–140 3. The 3-Bit Charge Pump Current Register. This register allows the current that drives the low pass ...
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AD9886 OFFSET 7 DAC IN x1.2 CLAMP V OFF V 0.5V (128 CODES) V OFF (128 CODES) 0V SCAN Function The SCAN function is intended as a pseudo JTAG function for manufacturing test for the board. The ordinary operation of ...
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AD9886 RGB HSYNC PxCK HS 5-PIPE DELAY ADCCK DATACK D OUTA HSOUT RGB HSYNC PxCK HS 5-PIPE DELAY ADCCK DATACK D OUTA HSOUT ...
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RGB HSYNC PxCK HS 5-PIPE DELAY ADCCK DATACK D OUTA D OUTB HSOUT RGB HSYNC PxCK HS 6-PIPE DELAY ADCCK DATACK D OUTA D OUTB HSOUT ...
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AD9886 RGB HSYNC PxCK HS 5.5-PIPE DELAY ADCCK DATACK D OUTA D OUTB HSOUT RGB IN HSYNC PxCK HS 6-PIPE DELAY ADDCK DATACK ...
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Serial Register Map The AD9886 is initialized and controlled by a set of registers, which determine the operating modes. An external controller is employed to write and read the Control Registers through the 2-line serial interface port. Write and ...
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AD9886 Write and Hex Read or Default Address Read Only Bits Value W/R 0FH 7 W/R 10H 5:2 11 11H RO 7:1 Table V. Control Register Map (Continued) Register Name Function PLL and Bit 7—HSYNC Polarity. ...
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Write and Hex Read or Default Address Read Only Bits Value W/R 12H 7 W/R 13H 7:0 00100000 W/R 14H 7:0 1 W/R 15H 7:0 W/R 16H 7:0 17H RO 7:0 18H RO 7:0 NOTE 1 ...
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AD9886 TWO-WIRE SERIAL CONTROL REGISTER DETAIL CHIP IDENTIFICATION 00 7–0 Chip Revision Bits 7 through 4 represent functional revisions to the analog interface. Changes in these bits will generally indicate that software and/or hardware changes will be required for the ...
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Clamp Duration An 8-bit register that sets the duration of the internally generated clamp. When EXTCLMP = 0, a clamp signal is generated inter- nally position established by the clamp placement and for a duration set ...
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AD9886 0E 4 HSYNC Output Polarity One bit that determines the polarity of the HSYNC out- put and the SOG output. Table XI shows the effect of this option. SYNC indicates the logic state of the sync pulse. Table XI. ...
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Red Clamp Select A bit that determines whether the red channel is clamped to ground or to midscale. For RGB video, all three chan- nels are referenced to ground. For YcbCr (or YUV), the Y channel is referenced ...
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AD9886 SYNC DETECTION AND CONTROL 11 7 Analog Interface HSYNC Detect This bit is used to indicate when activity is detected on the HSYNC input pin (Pin 82). If HSYNC is held high or low, activity will not be detected. ...
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Table XXXII. Active VSYNC Results Bit 5 (VSYNC Detect) Override AVS Bit 2 in 12H AVS = 0 means Sync separator. AVS = 1 means VSYNC input. The override bit is in ...
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AD9886 DIGITAL CONTROL 13 7:0 Sync Separator Threshold This register is used to set the responsiveness of the sync separator. It sets how many pixel clock pulses the sync separator must count to before toggling high or low. It works ...
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SDA t BUFF t DHO t STAH SCL Data is read from the control registers of the AD9886 in a similar manner. Reading requires two data transfer operations: The base address must be written with the R/W bit of the ...
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AD9886 SYNC STRIPPER NEGATIVE PEAK CLAMP SOG HSYNC IN ACTIVITY DETECT COAST VSYNC IN ACTIVITY DETECT Table XLV. Control of the Sync Block Muxes via the Serial Register Control Mux Serial Bus Bit Nos. Control Bit State Result 1 and ...
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PCB LAYOUT RECOMMENDATIONS The AD9886 is a high-precision, high-speed analog device. As such, to get the maximum performance out of the part it is important to have a well laid-out board. The following is a guide for designing a board ...
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AD9886 Voltage Reference Bypass with a 0.1 µF capacitor. Place as close to the AD9886 pin as possible. Make the ground connection as short as possible. REFOUT is easily connected to REFIN with a short trace. Avoid making this trace ...