AM79C901AJC Advanced Micro Devices, AM79C901AJC Datasheet
AM79C901AJC
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AM79C901AJC Summary of contents
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PRELIMINARY Am79C901A HomePHY™ Single-Chip 1/10 Mbps Home Networking PHY DISTINCTIVE CHARACTERISTICS n Fully integrated 1 Mbps HomePNA Physical Layer (PHY) as defined by Home Phoneline Networking Alliance (HomePNA) specification 1.1 — Optimized for home networking applications over existing telephone wire ...
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BLOCK DIAGRAM LED Interface PHY_SEL PHY_AD ISOLATE MII/GPSI GM_MODE RXDAT, RXCLK, RXCRS, CLS, TXDAT, TXCLK, TXEN MII/GPSI or DATA Interface RXD[3:0], TXD[3:0], CRS, COL, RX_DV, TX_EN, TX_CLK, RX_CLK, RX_ER MDC, MDIO or CONTROL SCLK, SDI, SDO, CS Clock Reference 2 ...
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TABLE OF CONTENTS AM79C901A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Reverse Polarity Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Mbps HomePNA Receive Timing (GPSI ...
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LIST OF FIGURES Figure 1. Idle State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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LIST OF TABLES Table 1. Clock Source Selection 21 Table 2. GPSI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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CONNECTION DIAGRAM (PL 068) 9 RXD1 10 RXD0/RXDAT 11 DVSS 12 RX_DV 13 DVDD 14 RX_CLK/RXCLK 15 AVDD 16 PHY_SEL 17 DVDD 18 RX_ER 19 DVSS 20 GM_MODE 21 TX_CLK/TXCLK 22 TX_EN/TXEN 23 TXD0/TXDAT 24 TXD1/SDI ...
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CONNECTION DIAGRAM (PQT 80 RX01 4 RXD0/RXOAT 5 DVSS 6 RX_DV 7 DVDD 8 RX_CLK/RXCLK 9 AVDD 10 PHY_SEL 11 DVDD 12 RX_ER 13 DVSS GM_MODE 14 TX_CLK/TXCLK 15 TX_EN/TXEN 16 TXD0/TXDAT 17 TXD1/SDI 18 ...
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PIN DESIGNATIONS (PL 068) Listed By Pin Number Pin Pin Pin No. Name No. 1 LED_LINK 18 DVDD 2 LED_COL 19 RX_ER 3 LED_ACTIVITY 20 DVSS 4 DVDD 21 GM_MODE 5 LED_POWER 22 TX_CLK/TXCLK 6 LED_SPEED 23 TX_EN/TXEN 7 DVSS ...
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PIN DESIGNATIONS (PQT 80) Listed By Pin Number Pin Pin Pin No. Name No RXD1 23 TXD2 4 RXD0/RXDAT 24 TXD3/CS 5 DVSS 25 DVSS 6 RX_DV 26 COL/CLS 7 DVDD ...
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PIN DESIGNATIONS (PL 068) Listed By Group Pin Name Configuration MII/GPSI Selects MII or GPSI mode GM_MODE Selects MDC/MDIO and GPSI data ISOLATE Isolates device if register isolate bit is set = 1 PHY_SEL Defines default PHY PHY_AD Defines bit ...
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Pin Name GPSI Interface TXCLK GPSI Transmit Clock TXDAT GPSI Transmit Data TXEN GPSI Transmit Enable RXCLK GPSI Receive Clock RXDAT GPSI Receive Data RXCRS Carrier Sense CLS Collision SPI Interface SCLK SPI Clock SDI SPI Data In SDO SPI ...
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PIN DESIGNATIONS (PQT 80) Listed By Group Pin Name Configuration MII/GPSI Selects MII or GPSI mode GM_MODE Selects MDC/MDIO and GPSI data ISOLATE Isolates device if register isolate bit is set = 1 PHY_SEL Defines default PHY PHY_AD Defines bit ...
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Pin Name GPSI Interface TXCLK GPSI Transmit Clock TXDAT GPSI Transmit Data TXEN GPSI Transmit Enable RXCLK GPSI Receive Clock RXDAT GPSI Receive Data RXCRS Carrier Sense CLS Collision SPI Interface SCLK SPI Clock SDI SPI Data In SDO SPI ...
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PIN DESIGNATIONS Listed By Driver Type The following table describes the various types of out- put drivers used in the Am79C901A PHY. All I I values shown in the table apply to 3.3 V signaling. OH Driver Name LED TS ...
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ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Am79C901A J\V Valid Combinations Am79C901A ...
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PIN DESCRIPTIONS Configuration Pins MII/GPSI MII/GPSI MII/GPSI selects between the MII and the GPSI inter- face. This pin must be connected to either V Changing the state of this pin is prohibited. GM_MODE GM_MODE This input pin selects between the ...
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LED_SPEED LED_SPEED This output is designed to directly drive an LED. SPEED low indicates that the HomePNA PHY is currently in the high-speed mode. When operating in the 10BASE-T mode this output will be held high. LED_POWER LED_POWER This output ...
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RXD[3:0] Receive Data RXD[3:0] is the nibble-wide receive data bus. Data ...
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TMS Test Mode Select A serial input bit stream on the TMS pin is used to de- fine the specific boundary scan test to be executed. The pin has an internal pull-up resistor. Ethernet Network Interfaces TX± Serial Transmit Data ...
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BASIC FUNCTIONS Network Interfaces The Am79C901A PHY contains an integrated 1 Mbps home networking PHY and a 10BASE-T PHY. This de- vice is compliant with the HomePNA specification 1.0 and IEEE 802.3 specification. The integrated HomePNA transceiver is a physical ...
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TXCLK TXEN TXDAT RXCLK RXCRS RXDAT CLS Note: RXCLK becomes disabled as soon as RXCRS is asserted. TXCLK TXEN TXDAT RXCLK RXCRS RXDAT CLS Note: RXCLK and TXCLK are unrelated to each other during this time. When a symbol has ...
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TXCLK TXEN TXDAT RXCLK RXCRS RXDAT CLS Note: Once TXEN is asserted, the PHY stops RXCLK, asserts RXCRS, and toggles TXCLK. TXCLK TXEN TXDAT RXCLK RXCRS RXDAT CLS Note: TXCLK continues to toggle until the SFD is observed, as shown ...
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TXCLK TXEN TXDAT RXCLK RXCRS RXDAT CLS Note: Once TXEN is cleared, the last symbol gets encoded and transmitted, the looped-back data is presented back to the MAC, and RXCRS falls. Once RXCRS falls, TXCLK and RXCLK toggle for 96 ...
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TXCLK TXEN TXDAT RXCLK RXCRS RXDAT CLS Note: CLS may be asserted up to 120 s after RXCRS has been asserted. Once CLS has been asserted, TXCLK and RXCLK run until 96 cycles after CLS and RXCRS are cleared. It ...
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Op Codes ST OP READ 01 10 WRITE 01 01 READ 0000 = No Error/AAAA = Error Detected WRITE 0000 = No Error/AAAA = Error Detected Start Frame CS SCLK 1 SDI SDO SCLK 1 CS SDI SDO Figure 11. ...
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SCLK SDI Op Codes SDO MII-Compatible Interface for HomePNA PHY The control and data signals that are utilized in the MII- compatible interface of the 1 Mbps HomePNA PHY function in an manner ...
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The operation field (OP) follows the start field (ST). The OP indicates whether the operation is a read or a write operation. The PHY address (PHYADD) and the register address (REGADD) that were programmed follow this. A bus turnaround field ...
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TX_CLK TX_EN TXD data CRS RX_CLK RX_DV RXD data COL IPG 96 Bit Times data 55 If SEQ is enabled Figure 15. MII End of Transmission Am79C901A Idle ...
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Mbps HomePNA PHY The integrated HomePNA transceiver is a physical layer device supporting HomePNA specification 1.0 for home phoneline networking. It provides all of the PHY layer functions required to support 1 Mbps data transfer speeds over existing residential ...
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HomePNA Header SYNC Access ID interval AID AID AID blanking blanking blanking interval interval interval Fixed 14. tics 20 tics 66 tics 129 tics 129 tics 129 tics 129 tics SYNC ACCESS ACCESS ACCESS Symbol ...
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AID Symbol 0 pulse 0 SYNC_START TIC=0 SYNC_END TIC=126 D slice threshold AID Symbol 0 pulse 0 Detected envelope END_RCV_BLANK SYNC_START TIC=0 SYNC_END The SYNC interval is followed by six AID symbols (symbols 1 through 6). Transmit timing is shown ...
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The next two AID symbols (5 and 6) encode four bits of control word information. The MSB is encoded in AID Symbol 5. Control word messages are described further in the Mode Interface section. AID Transmit Timing: The transmitter encodes ...
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Data Transmit Timing A data symbol interval begins with the start of transmis- sion of a pulse as shown in Figure 19. Transmit Symbol timing (in TICs) is measured from this point (TIC = 0). Depending on the data code, ...
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Data Symbol RLL25 Encoding The RLL25 code is the version of TM32 that was devel- oped for the HomePNA PHY. It produces the highest bit rate for a given value of ISBI and TIC size manner similar to ...
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Header AID Remote Control Word Commands Stations may be configured either as master stations or as slave stations. Only one master may exist on a given HomePNA segment or network over which the HomePNA PHY header is preserved. The master ...
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The any1Home link packet consists of valid AID and PCOM fields followed by four bytes of data. The receiv- ing node’s MAC will interpret this packet as a runt frame and will not forward the frame to upper layers, thus ...
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Twisted Pair Interface Status The Am79C901A device will power up in the Link Fail state. The Auto-Negotiation algorithm will apply to allow it to enter the Link Pass state. In the Link Pass state, receive activity which passes the pulse ...
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Auto-Negotiation goes further by providing a mes- sage-based communication scheme called Next Pages before connecting to the Link Partner. Soft Reset Function The PHY Control Register (TBR0) incorporates the soft reset function (bit 15 read/write register and ...
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Table 12. IEEE 1149.1 Supported Instruction Summary Instruction Instruction Name Code Description EXTEST 0000 External Test ID Code IDCODE 0001 Inspection Sample SAMPLE 0010 Boundary Force Tri- TRI_ST 0011 State BYPASS 1111 Bypass Scan Normal Force Tri- TRI_ST 0011 State ...
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LED_POWER 17 LED_POWER BSR Cell No. Cell Name 16 LED_ACTIVITY 15 LED_ACTIVITY 14 LED_ACTIVITY 13 LED_COL 12 LED_COL 11 LED_COL 10 LED_LINK 9 LED_LINK 8 LED_LINK 7 MDC_SCLK 6 MDIO 5 MDIO 4 MDIO_OEN 3 ISOLATE 2 PHY_AD 1 ...
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USER ACCESSIBLE REGISTERS The Am79C901A PHY has two types of user regis- ters: 1 Mbps HomePNA PHY management registers (HPRs) and 10BASE-T PHY management registers (TBRs). Table 16. 1 Mbps HomePNA PHY Management Registers (HPRs) Register Address Symbol 0 HPR0 ...
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HPR0: HomePNA PHY Control Register (Register 0) Table 17. HPR0: HomePNA PHY Control Register (Register 0) Bits Name 15 RESET 14 Enable Loopback Mode 13 Speed Selection 12 Auto-Negotiation Enabled 11 Power Down 10 Isolate 9 Restart Auto-Negotiation 8 Duplex ...
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HPR1: HomePNA PHY Status Register (Register 1) Table 18. HPR1: HomePNA PHY Status Register (Register 1) Bits Name 15 100BASE-T4 100BASE-X Full-Duplex 14 13 100BASE-X Half-Duplex 10 Mbps Full-Duplex Mbps Half-Duplex 10:7 Reserved Management Frame Preamble 6 ...
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HPR2 and HPR3: HomePNA PHY ID Registers (Registers 2 and 3) Table 19. HPR2: HomePNA PHY ID Register (Register 2) Bits Name 15:0 PHY_ID MSB (31-16) Table 20. HPR3: HomePNA PHY ID Register (Register 3) Bits Name PHY_ID LSB (15-10) ...
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HPR4: HomePNA PHY Auto-Negotiation Advertisement Register (Register 4) This register contains the advertised ability of the Am79C901A device. The purpose of this register is to advertise the technology ability to the link partner de- Table 21. HPR4: HomePNA PHY Auto-Negotiation ...
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HPR5: HomePNA PHY Auto-Negotiation Link Partner Ability Register (Register 5) The Auto-Negotiation Link Partner Ability Register is Read Only. The register contains the advertised ability of the link partner. The bit definitions represent the re- ceived link code word. This ...
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HPR6: HomePNA PHY Auto-Negotiation Expansion Register (Register 6) The Auto-Negotiation Expansion Register provides additional information that aids the Auto-Negotiation Table 24. HPR6: HomePNA PHY Auto-Negotiation Expansion Register (Register 6) Bits Name 15:5 Reserved 1 = Parallel detection fault Parallel Detection ...
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HPR16: HomePNA PHY Control Register (Register 16) Table 26. HPR16: HomePNA PHY Control Register (Register 16) Bits Name Remote Command 15 Reserved 14:13 SQE_TEST Disable 12 11 Command Low Power 10 Command High Power 9 Command Low Speed 8 Command ...
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HPR17: HomePNA PHY Status/Control Register (Register 17) The HomePNA PHY Status/Control Register pro- vides information regarding the global aspects of the operation of the PHY. Table 27. HPR17: HomePNA PHY Status/Control Register (Register 17) Bits Name 15:13 Reserved 12 any1Home_ ...
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HPR20 and HPR21: HomePNA PHY RxCOMM Registers (Registers 20 and 21) Table 29. HPR20 and HPR21: HomePNA PHY RxCOMM Registers (Registers 20 and 21) Bits Name 15:0 PHY_RX_COMM (4) The 32-bit received data field to be used for out-of- band ...
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HPR24: HomePNA PHY Noise Control 2 Register (Register 24) Table 32. HPR24: HomePNA PHY Noise Control 2 Register (Register 24) Bits Name 15:8 Noise Attack Reserved 7:0 HPR25: HomePNA PHY Noise Statistics Register (Register 25) Table 33. HPR25: HomePNA PHY ...
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HPR26: HomePNA PHY Event Status Register (Register 26) Table 34. HPR26: HomePNA PHY Event Status Register (Register 26) Bits Name 15:10 Reserved RxPCOM 9 8 TxPCOM 7:4 Reserved 3 Packet Received 2 Packet Transmitted 1 Remote Command Received 0 Remote ...
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HPR28: HomePNA PHY ISBI Control Register (Register 28) Table 36. HPR28: HomePNA PHY ISBI Control Register (Register 28) Bits Name 15:8 ISBI_SLOW ISBI_FAST 7:0 HPR29: HomePNA PHY TX Control Register (Register 29) Table 37. HPR29: HomePNA PHY TX Control Register ...
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HPR31: HomePNA PHY Analog Control Register (Register 31) Table 39. HPR31: HomePNA PHY Analog Control Register (Register 31) Bits Name 15:11 Level_Adjust 10:8 Reserved 7 Force_Link_Valid 6:0 Reserved 10BASE-T PHY Management Registers (TBRs) The Am79C901A home networking device supports the ...
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TBR0: 10BASE-T PHY Control Register (Register 0) Table 41. TBR0: 10BASE-T PHY Control Register (Register 0) Bits Name Soft Reset (Note Enable Loopback Mode Speed Selection 13 (Note 3) Auto-Negotiation Enable 12 11 Power Down Isolate 10 ...
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TBR1: 10BASE-T Status Register (Register 1) The Status Register identifies the physical and Auto- Negotiation capabilities of the local PHY. This register is read only; a write will have no effect. See Table 42. Table 42. TBR1: 10BASE-T PHY Status ...
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TBR2 and TBR3: 10BASE-T PHY Identifier Register (Registers 2 and 3) Registers 2 and 3 contain a unique PHY identifier, con- sisting of 22 bits of the organizationally unique IEEE identifier, a 6-bit manufacturer’s model number, and a 4-bit manufacturer’s ...
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TBR4: 10BASE-T Auto-Negotiation Advertisement Register (Register 4) This register contains the advertised ability of the Am79C901A home networking device. The purpose of this register is to advertise the technology ability to the link partner device. See Table 45. Table 45. ...
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TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register 5) The Auto-Negotiation Link Partner Ability Register is Read Only. The register contains the advertised ability of the link partner. The bit definitions represent the re- ceived link code word. This register ...
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TBR6: 10BASE-T Auto-Negotiation Expansion Register (Register 6) The Auto-Negotiation Expansion Register provides ad- ditional information which aids the Auto-Negotiation Table 48. TBR6: 10BASE-T Auto-Negotiation Expansion Register (Register 6) Bits Name 15:5 Reserved 1 = Parallel detection fault Parallel Detection 4 ...
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TBR16: 10BASE-T Status and Enable Register (Register 16) The status bits indicate when there is a change in the Link Status, Duplex Mode, Auto-Negotiation status, or Speed status. Register 16 contains the status and enable bits. The status is always ...
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TBR17: 10BASE-T PHY Control/Status Register (Register 17) This register is used to control the configuration of the 10 Mbps PHY of the Am79C901A home networking device. See Table 1. Table 1. TBR17: 10BASE-T PHY Control/Status Register (Register 17) Bits Name ...
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TBR19: 10BASE-T PHY Management Extension Register (Register 19) Table 2 contains the PHY Management Extension Reg- ister (Register 19) bits. Table 2. TBR19: 10BASE-T PHY Management Extension Register (Register 19) Bits Name 15:6 Reserved 5 Mgmt Frame Format 4:0 PHY ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . – +150 C Ambient Temperature (C - +70 C Ambient ...
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DC CHARACTERISTICS Parameter Symbol Parameter Description Digital I/O Voltage V Input HIGH Voltage IH V Input HIGH voltage (5V) IH5V Input LOW Voltage V IL Output LOW Voltage Output HIGH Voltage (Notes Output Voltage ...
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SWITCHING WAVEFORMS Key to Switching Waveforms SWITCHING TEST CIRCUITS Sense Point WAVEFORM INPUTS Must be Steady May Change from May Change from ...
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AC CHARACTERISTICS GPSI 10BASE-T Transmit Timing (GPSI) No. Symbol TXDAT, TXEN setup time to TXCLK TXDAT, TXEN hold time from TXCLK H Transmit latency (TXEN sampled HIGH to 1st bit of data ...
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AC CHARACTERISTICS (CONTINUED) 10BASE-T Receive Timing (GPSI) No. Symbol 10 t CLS assert latency from SOP PD RXCRS assert latency from SOP Receive latency (SOP to RXDAT valid) PD RXCLK edge to RXDAT transition 13 ...
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AC CHARACTERISTICS (CONTINUED) 10BASE-T Receive Timing (GPSI) (Continued) RXCLK RX± CLS RXCRS Figure 4. 10 Mbps Receive End of Packet Timing (GPSI) 10BASE-T Transmit Clock Timing (GPSI) No. Symbol 18 t TXCLK period PER 19 t TXCLK pulse width HIGH ...
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AC CHARACTERISTICS (CONTINUED) 1 Mbps HomePNA Transmit Timing (GPSI) No. Symbol 23 t TXDAT setup time to TXCLK S TXEN setup time to TXCLK TXDAT hold time from TXCLK H TXEN hold time from TXCLK ...
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AC CHARACTERISTICS (CONTINUED) 1 Mbps HomePNA Receive Timing (GPSI) No. Symbol 29 t RXCLK edge to RXDAT transition (Note 1) PD SYNC pulse detected to RXCRS clocked as active by MAC (Note Last DATA ...
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AC CHARACTERISTICS (CONTINUED) 1 Mbps HomePNA Clock Timing (GPSI) No. Symbol Idle (excluding IPG time) TXCLK, RXCLK period 35 t PER 36 t TXCLK, RXCLK pulse width HIGH PWH TXCLK, RXCLK pulse width LOW 37 t PWL Preamble (first 64 ...
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AC CHARACTERISTICS (CONTINUED) MII 10BASE-T Transmit Timing (MII) No. Symbol TXD, TX_EN setup time to TXCLK TXD, TX_EN hold time from TXCLK H Transmit latency (TX_EN sampled HIGH to 1st bit of data ...
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AC CHARACTERISTICS (CONTINUED) 10BASE-T Receive Timing (MII) No. Symbol 48 t COL assert latency from SOP PD CRS assert latency from SOP Receive latency (SOP to RXD, RX_DV valid) (Note 1) PD RX_CLK edge to ...
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AC CHARACTERISTICS (CONTINUED) 10BASE-T Receive Timing (MII) (Continued) RX_CLK RX± COL CRS RX_DV Figure 11. 10 Mbps Receive End of Packet Timing (MII End of Packet ...
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AC CHARACTERISTICS (CONTINUED) 10BASE-T Transmit Clock Timing (MII) No. Symbol 57 t TX_CLK period PER TX_CLK pulse width HIGH 58 t PWH 59 t TX_CLK pulse width LOW PWL 10BASE-T Receive Clock Timing (MII) No. Symbol 57 t RX_CLK period ...
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AC CHARACTERISTICS (CONTINUED) 1 Mbps HomePNA Transmit Timing (MII) No. Symbol 62 t TXD, TX_EN setup time to TX_CLK S TXD, TX_EN hold time from TX_CLK Transmit Latency (TX_EN sampled HIGH to SYNC pulse (5 ...
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AC CHARACTERISTICS (CONTINUED) 1 Mbps HomePNA Receive Timing (MII) No. Symbol 68 t RX_CLK edge to RXD, RX_DV transitions (Note 1) PD SYNC pulse detected to CRS clocked as active by MAC (Note Last ...
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AC CHARACTERISTICS (CONTINUED) 1 Mbps HomePNA Clock Timing (MII) No. Symbol Idle (excluding IPG time) TX_CLK, RX_CLK period 74 t PER 75 t TX_CLK, RX_CLK pulse width HIGH PWH TX_CLK, RX_CLK pulse width LOW 76 t PWL Preamble (first 64 ...
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AC CHARACTERISTICS (CONTINUED) MDC/MDIO No. Symbol 79 t MDC period PER 80 t MDC pulse width HIGH PWH 81 t MDC pulse width LOW PWL 82 t MDIO output delay from MDC MDIO input setup time to ...
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AC CHARACTERISTICS (CONTINUED) SPI Parameter No. Symbol 88 t SCLK period PW SCLK Min pulse HIGH 89 t PWH 90 t SCLK Min pulse LOW PWL CS setup to SCLK hold to SCLK H ...
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AC CHARACTERISTICS (CONTINUED) 10BASE-T PMD No. Symbol Parameter Description Transmit End of Transmit Data 99 t TETD RX± Pulse Width Maintain/Turn Off 100 t PWKRD Threshold Note: RX± pulses narrower than t PWDRD will turn internal Carrier Sense off. TX± ...
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AC CHARACTERISTICS (CONTINUED) 1 Mbps HomePNA Analog Parameter No. Symbol Pulse Width 103 t PW 104 t Pulse Width HIGH PWH Pulse Width LOW 105 t PWL Maximum Voltage (positive) 106 t VMAXp Maximum Voltage (negative) 107 t VMAXn Notes: ...
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AC CHARACTERISTICS (CONTINUED) JTAG No. Parameter Symbol TCK Period 110 t PER 111 t TCK HIGH Time PWH 112 t TCK LOW Time PWL 113 t TDI, TMS Setup Time S 114 t TDI, TMS Hold Time H TDO Valid ...
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AC CHARACTERISTICS (CONCLUDED) External Clock (XTAL1) No. Symbol 119 t Cycle time PER 120 t Cycle HIGH time PWH 121 t Cycle LOW time PWL XTAL1 Reset Symbol Parameter Description t RESET to RESET ...
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PHYSICAL DIMENSIONS* PL 068 Plastic Leaded Chip Carrier (measured in inches) *For reference only. BSC is an ANSI standard for Basic Space Centering Am79C901A ...
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PHYSICAL DIMENSIONS* PQT 80 Thin Plastic Quad Flat Pack (measured in millimeters) *For reference only. BSC is an ANSI standard for Basic Space Centering Am79C901A 89 ...
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