AM79C982-4JC Advanced Micro Devices, AM79C982-4JC Datasheet
AM79C982-4JC
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AM79C982-4JC Summary of contents
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... This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. ...
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AMD For application examples on building a fully managed repeater using the IMR+ and HIMIB devices, refer to AMD’s IEEE 802.3 Repeater Technical Manual (PID#17314A) and the ISA-HUB (PID # 17642A). BLOCK DIAGRAM DI AUI CI Port DO RXD TP ...
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CONNECTION DIAGRAM DO– 12 DO+ 13 TXD0 TXD0– TXP1+ 17 TXP1– TXD1+ 20 TXD1– 21 TXP1+ 22 TXP1– TXD2+ 25 TXD2– 26 TXP2+ 27 TXP2– DV ...
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AMD LOGIC SYMBOL AUI Management Port LOGIC DIAGRAM Management Port Twisted Pair Port 0 1–74 PRELIMINARY TXD+ DO+ TXP+ DO– TXD– DI+ TXP– DI– RXD+ CI+ RXD– CI– Am79C981 DAT SCLK SI JAM SO ACK COL ...
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ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed by a combination of the elements below. Am79C981 DEVICE NUMBER/DESCRIPTION Am79C981 Integrated Multiport Repeater Plus (IMR+) Valid Combinations ...
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PIN DESCRIPTION ACK Acknowledge Input, Active LOW When this input is asserted, it signals to the requesting IMR+ device that it may control the DAT and JAM pins. If the IMR+ chip is not requesting control of the DAT line ...
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REQ Request Output, Active LOW This pin is driven LOW when the IMR+ chip is active. An IMR+ chip is active when it has one or more ports receiving or colliding the state where it is still ...
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TXD+ , TXD– 0–7 0–7 Transmit Data Output 10BASE-T port differential drivers (8 ports). TXP+ , TXP– 0–7 0–7 Transmit Predistortion Output 10BASE-T transmit waveform predistortion control differential outputs (8 ports). 1– ...
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FUNCTIONAL DESCRIPTION The Am79C981 Integrated Multiport Repeater Plus de- vice is a single chip implementation of an IEEE 802.3/Ethernet repeater (or hub). In addition to the eight integral 10BASE-T ports plus one AUI port comprising the basic repeater, the IMR+ ...
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AMD The reconnection algorithm option (standard or alter- nate global function for the TP ports, i.e. all TP ports use the same reconnection algorithm. The AUI reconnection algorithm option is programmed inde- pendently of the TP port reconnection ...
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Expansion Port The IMR+ chip Expansion Port is comprised of five pins; two are bi-directional signals (DAT and JAM), two are in- put signals (ACK and COL), and one is an output signal (REQ). These signals are used when a ...
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AMD 1/2 ’74 ASYNC D RESET XTAL OSC. Note 1: Direction DIR B A LOW A B HIGH Modular Repeater Design The expansion port of the IMR+ chip also allows for modular expansion. By sharing the ...
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Repeater MAC Interconnection Because all repeated data in the IMR+ chip or multi- IMR+ chip design is available on the Expansion Port, all network traffic can be monitored by an external Media Access Controller (MAC) device such as the Am7990, ...
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AMD Management Port The IMR+ device management functions are enabled when the TEST pin is tied LOW. The management com- mands are byte oriented data and are input serially on the SI pin. Any responses generated during execution of a ...
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Table 2. Management Port Command Summary Commands Set (Write) Opcodes IMR+ Chip Programmable Options Alternate AUI Partitioning Algorithm Alternate TP Partitioning Algorithm AUI Port Disable AUI Port Enable TP Port Disable TP Port Enable Disable Link Test Function (per TP ...
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AMD SET (Write) Opcodes IMR+ Chip Programmable Options SI data: 0000 1CSA SO data: None IMR+ Chip Programmable Options can be enabled (dis- abled) by setting (resetting) the appropriate bit in the command string. The three programmable bits are: C—CI ...
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AUI Port Enable SI data: 00111111 SO data: None This command enables a previously disabled AUI port. Note that a partitioned AUI port may be reconnected by first disabling (AUI Port Disable Command) and then re- enabling the port with ...
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AMD P Partitioning Status. This bit the AUI port is partitioned and 1 if connected. B Bit Rate Error. This bit is set there has been an instance of FIFO Overflow or Underflow, caused ...
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Version SI data: 11111111 SO data: XXXX0001 This command (1111 1111) can be used to determine the device version. The IMR+ chip responds by the bit pattern: XXXX 0001 The IMR chip (Am79C980) responds by the bit pattern: XXXX 0000 ...
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AMD XTAL OSC 1/2 ’ ASYNC D RESET Figure 3. Minimum Mode, Non-Intelligent Repeater Example X1 TCK (Note 1) CRS CRS CRS AUI TP0 (Note AUI TP0 (Note 3) STR Notes: 1. Externally generated signal ...
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XTAL OSC 1/2 ’ ASYNC D RESET Figure 5a. Port Activity Monitor Implementation RST TCK (Note 1) CRS STR (Note 3) Notes: 1. Externally generated signal illustrates internal IMR+ chip clock phase relationship. 2. IMR+ ...
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AMD Loopback Test Mode The IMR+ chip can be programmed to enter Loopback Mode on all network ports. This is accomplished by first driving the TEST pin HIGH, then clocking (using the SCLK pin) a minimum of three 0s into ...
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IMR+ Chip External Components Figure 6 shows a typical twisted pair port external com- ponents schematic. The resistors used should have a 1% tolerance to ensure interoperability with 10BASE-T compliant networks. The filters and pulse transformers are necessary devices that ...
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AMD APPLICATIONS A fully managed multiport repeater can be easily built by interfacing the IMR+ chip with the Hardware Imple- mented Management Information Base (HIMIB), Am79C987 device. The HIMIB device interfaces with all common Microprocessor System Busses with a Host ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . Ambient Temperature Under Bias Supply Voltage referenced ( ...
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AMD DC CHARACTERISTICS (continued) Parameter Symbol Parameter Description Twisted Pair Ports I Input current at RXD+/- IRXD R RXD differential input resistance RXD V RXD+,RXD- open circuit input TIVB voltage (bias) V Differential Mode input voltage TID range (RXD) V ...
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SWITCHING CHARACTERISTICS over operating ranges unless otherwise specified Parameter Symbol Parameter Description Clock and Reset t X1 Clock Period Clock HIGH X1H t X1 Clock LOW X1L t X1 Clock Rise Time X1R t X1 Clock Fall ...
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AMD SWITCHING CHARACTERISTICS (continued) Parameter Symbol Parameter Description Expansion Port (Continued) t DAT/JAM setup time DJSET t DAT/JAM hold time DJHOLD COL/ACK setup time t CASET COL/ACK hold time t CAHOLD TEST setup time with respect to RST t MHSET ...
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SWITCHING CHARACTERISTICS (continued) Notes: 1. Parameter not tested. 2. Uses switching test load pulses narrower than t (min) will be rejected; pulses wider than t PWODI 4. DI pulses narrower than t (min) will maintain internal DI carrier ...
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AMD KEY TO SWITCHING WAVEFORMS SWITCHING WAVEFORMS X1R 1–100 PRELIMINARY WAVEFORM INPUTS Must Be Steady May Change from May Change from Don’t Care Any Change Permitted Does Not Apply t X1 ...
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SWITCHING WAVEFORMS X1 RST TCK* Notes: t refers to synchronous Reset Timing. RSTSET *Externally generated (Figure 4) signal illustrates internal IMR+ device clock phase relationships. SCLK t SCLKH SI/TEST SO t SODLY PRELIMINARY t RSTHLD t t RST or t ...
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AMD SWITCHING WAVEFORMS X1 TCK* REQ ACK COL DAT JAM Note: *Externally generated (Figure 4) signal illustrates internal IMR+ chip clock phase relationships. X1 TCK* t X1HRL REQ t CASET ACK COL DAT JAM Note: *Externally generated (Figure 4) signal ...
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SWITCHING WAVEFORMS X1 TCK* t X1HRL REQ ACK t CASET COL DAT IN JAM Note: *Externally generated (Figure 4) signal illustrates internal IMR+ chip clock phase relationships. Test RST X1 STR SI, Don’t Care SCLK PRELIMINARY t X1HRH t CASET ...
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AMD SWITCHING WAVEFORMS X1 t DOTD D0+ D0– DO+/– DI+/– V ASQ t PWKDI t PWODI 1–104 PRELIMINARY DOTR DOTF AUI DO Timing Diagram t DOETD 40 mV 100 mV max. 80-Bit ...
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SWITCHING WAVEFORMS CI+/– V ASQ t PWOCI TXTD TXD+ TXP+ TXD– TXP– PRELIMINARY t PWKCI AUI Collision Timing Diagram TXTR XTXTF t TXTD TP Ports Output Timing Diagram ...
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AMD SWITCHING WAVEFORMS t PWPLP TXD+ TXP+ TXD– TXP– t PWLP V TSQ+ RXD+/– V TSQ– t PWKRD 1–106 PRELIMINARY t PWPLP t PERLP TP Idle Link Test Pulse t PWKRD TP Receive Timing Diagram Am79C981 17306B-30 t PWKRD V ...
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SWITCHING TEST CIRCUITS DO+ DO– TXD+ TXD– Includes Test Jig Capacitance TXP+ TXP– Includes Test Jig Capacitance PRELIMINARY AV DD 52.3 154 100 pF Includes Test Jig Capacitance AV SS 17306B-32 AUI DO Switching Test Circuit DV DD 294 Test ...
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APPENDIX A 10BASE-T INTERFACE The table below lists the recommended resistor values and filter and transformer modules for the IMR+ device. IMR+ Device Compatible 10BASE-T Media Interface Modules ¶ Manufacturer Part # Package Bel Fuse S556-5999-32 16-pin SMD Bel Fuse ...
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APPENDIX B Glossary Active Status In a non-collision state, an IMR+ chip is considered ac- tive receiving data on any one of its network ports the process of broadcasting (repeating) FIFO data from a ...
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Am79C981 ...