CY7C133-25JI Cypress Semiconductor Corporation., CY7C133-25JI Datasheet
CY7C133-25JI
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CY7C133-25JI Summary of contents
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... A 0L R/W R/W Note: 1. CY7C133 (Master): BUSY is open drain output and requires pull-up resistor. CY7C143 (Slave): BUSY is input. Cypress Semiconductor Corporation Document #: 38-06036 Rev Dual-Port Static RAM Functional Description The CY7C133 and CY7C143 are high-speed CMOS dual-port static RAMs. Two ports are provided permitting independent access to any location in memory ...
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... CY7C133 CY7C143 BUSY BUSY ...
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... To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. The CY7C133 and CY7C143 have an automatic power-down feature controlled by CE. Each port is provided with its own output enable control (OE), which allows data to be read from the device ...
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... L L port writes OK R port write inhibited R R port writes OK L port write inhibited or BUSY = “L”). BUSY and BUSY LOW. Writes are inhibited to the right port when BUSY L CY7C133 CY7C143 Operation Function R H Normal H Normal H Normal [4] Write Inhibit ...
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... IN [ MAX Test Conditions Min. = Min –4 4.0 mA [5] = 16.0 mA 2.2 −5 < and using AC Test Waveforms input levels of GND to 3V. RC CY7C133 CY7C143 Ambient Temperature V CC ° ° + ± 10% ° ° − + ± 10% 7C133-25 7C143-25 Min. ...
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... Max. Unit 281Ω BUSY OR INT 30 pF BUSY Output Load (CY7C133 ONLY) 90% 10% < Page [+] Feedback ...
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... HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 15. Port-to-port delay through RAM cells from writing port to reading port. Refer to timing waveform of “Read with BUSY, Master: CY7C133.” ...
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... IL 23. Address valid prior to or coincidence with CE transition LOW. Document #: 38-06036 Rev. *B Either Port Address Access Either Port CE/OE Access t ACE t DOE DATA VALID Read with BUSY (for master CY7C133 ADDRESS MATCH t PWE VALID ADDRESS MATCH t BLA t WDD . IL CY7C133 ...
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... VALID MATCH t WDD [17, 27] Either Port SCE PWE t SD DATA VALID HIGH IMPEDANCE for the reading port PWE HZWE . SD CY7C133 CY7C143 t DH VALID t DDD allow the data I/O pins to enter high SD Page [+] Feedback ...
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... If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state. Document #: 38-06036 Rev. *B [23, 28] Either Port SCE PWE t SD DATA VALID t HZWE HIGH IMPEDANCE ADDRESS MATCH BLC BHC ADDRESS MATCH BLC BHC CY7C133 CY7C143 LZWE Page [+] Feedback ...
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... ADDRESS MATCH ADDRESS ADDRESS L BUSY L Busy Timing Diagram No. 3 Write with BUSY (For Slave CY7C143 BUSY Document #: 38-06036 Rev ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA t PWE t WH CY7C133 CY7C143 Page [+] Feedback ...
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... Ordering Information Master Dual-Port SRAM Speed (ns) Ordering Code 25 CY7C133-25JC CY7C133-25JI 35 CY7C133-35JC CY7C133-35JI 55 CY7C133-55JC Package Diagram All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-06036 Rev. *B © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product ...
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... Document History Page Document Title: CY7C133/CY7C143 Dual-Port Static RAM Document Number: 38-06036 Issue Orig. of REV. ECN NO. Date Change ** 110178 09/22/01 *A 127954 08/27/03 *B 236761 See ECN Document #: 38-06036 Rev. *B Description of Change SZV Change from Spec number: 38-00414 to 38-06036 FSG Logic Block Diagram: fixed busy I/O flag on devices (typo) Removed obsolete parts from ordering information table: – ...