DS2404 Maxim Integrated Products, DS2404 Datasheet

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... Tape and Reel of DS2404B DESCRIPTION The DS2404 EconoRAM Time Chip offers a simple solution for storing and retrieving vital data and time information with minimal hardware. The DS2404 contains a unique lasered ROM, real-time clock/calendar, interval timer, cycle counter, programmable interrupts, and 4096-bits of SRAM. Two separate ports are provided for communication: 1-Wire and 3-wire ...

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... The DS2404 features can be used to create a stopwatch, alarm clock, time and date stamp, logbook, hour meter, calendar, system power-cycle timer, expiration timer, and event scheduler. DETAILED PIN DESCRIPTION PIN SYMBOL 1, IRQ 3 RST I/O 6 CLK 7,12 NC 8,13 GND 9 V BATB 10 V BATO ...

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... The “Power Control” section provides for two basic power configurations: battery operate mode and V operate mode. The battery operate mode utilizes one supply connected to V may utilize two supplies; the primary supply connects to V DS2404 BLOCK DIAGRAM Figure 1 COMMUNICATION PORTS Two communication ports are provided: a 1-Wire and a 3-wire port. The advantages of using the 1-Wire port are as follows: 1) provides access to the 64-bit lasered ROM, 2) consist of a single communication signal (I/O), and 3) multiple devices may be connected to the 1-Wire bus ...

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... LASERED ROM Each DS2404 contains a unique ROM code that is 64 bits long. The first eight bits are a 1-Wire family code (DS2404 code is 04h). The next 48 bits are a unique serial number. The last eight bits are a CRC of the first 56 bits. (See Figure 2.) The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates as shown in Figure 3 ...

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MEMORY MAP Figure ...

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MEMORY The memory map in Figure 4 shows a page (32 bytes) called the scratchpad and 17 pages called memory. Pages 0 through 15 each contain 32 bytes which make up the 4096-bit SRAM. Page 16 has only 30 bytes ...

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Alarm Registers The alarm registers for the real-time clock, interval timer, and cycle counter all operate in the same manner. When the value of a given counter equals the value in its associated alarm register, the appropriate flag bit is ...

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... Read Only programmable expiration occurs and the read only bit is set to a logic 1, then the DS2404 becomes read only programmable expiration occurs and the read only bit is a logic 0, then only the 64-bit lasered ROM can be accessed (see “Write Protect/Programmable Expiration” section). ...

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The third register (E/ read only register. The first five bits (E4: E0) of this register are called the ending offset. The ending offset is a byte offset within a page. Bit 5 (PF) is the partial byte ...

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MEMORY FUNCTION FLOW CHART Figure ...

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... The ending offset/data status byte is unaffected. The hardware of the DS2404 provides a means to accomplish error-free writing to the memory section. To safeguard reading data in the 1-Wire environment and to simultaneously speed up data transfers recommended to packetize data into data packets of the size of one memory page each ...

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... WRITE PROTECT/PROGRAMMABLE EXPIRATION The write protect bits (WPR, WPI, WPC) provide a means of write protecting the timekeeping data and limiting access to the DS2404 when an alarm occurs (programmable expiration). The write protect bits may not be written by performing a single copy scratchpad command. Instead, to write these bits, the copy scratchpad command must be performed three times. Please note that the AA bit will be set, as expected, after the first copy command is successfully executed ...

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... To facilitate this, each device attached to the 1-Wire bus must have open drain or 3-state outputs. The 1-Wire port of the DS2404 (I/O pin 5) is open drain with an internal circuit equivalent to that shown in Figure 8. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The 1-Wire bus has a maximum data rate of 16.3k bits per seconds. Depending on 1-Wire communication speed and bus load characteristics, the optimal pull-up resistor value will be in the 1.5 k Ω ...

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... This command allows the bus master to read the DS2404’s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can only be used if there is a single DS2404 on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-AND result) ...

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... The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS2404 on a multidrop bus. Only the DS2404 that exactly matches the 64-bit ROM sequence will respond to the following memory function command. All slaves that do not match the 64-bit ROM sequence will wait for a reset pulse ...

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ROM FUNCTIONS FLOW CHART (1-WIRE PORT ONLY) Figure 9 (See Figure ...

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... DS2404. During write time slots, the delay circuit determines when the DS2404 will sample the data line. For a read data time slot “0” transmitted, the delay circuit determines how long the DS2404 will hold the data line low overriding the 1 generated by the master. If the data bit is a “ ...

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... READ/WRITE TIMING DIAGRAM Figure 11 Write-one Time Slot Write-zero Time Slot Read-data Time Slot RESISTOR MASTER DS2404 60 μ s < t < 120 μ s SLOT 1 μ s ≤ t < 15 μ s LOW1 1 μ s ≤ t < ∞ REC 60 μ s ≤ t < 120 μ s < t LOW0 SLOT 1 μ s ≤ t < ...

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... If an alarm condition occurs while the device is disarmed, at first a type 2 interrupt will be produced. Spontaneous interrupts are signaled by the DS2404 by pulling the data line low for 960 to 3840 μ the interrupt condition begins (Figure 12). After this long low pulse a presence pulse will follow. If the alarm condition occurs just after the master has sent a reset pulse, i ...

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... TYPE 1 INTERRUPT Figure 12 TYPE 1A INTERRUPT (SPECIAL CASE) Figure 13 TYPE 2 INTERRUPT Figure 14 DS2404 ...

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... Command bits and data bits are input on the rising edge of the clock and data bits are output on the falling edge of the clock. When reading data from the DS2404, the DQ pin goes to a high impedance state while the clock is high. Taking communication and cause the DQ pin high impedance state ...

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... BATO To always allow communication through the 1-Wire or wire port, the voltage on V approximately 3-wire port, the voltage on V Otherwise the DS2404 will retain data, but will not allow any access. The V pin is normally connected to any standard 3V lithium cell or other energy source ...

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... This restriction does not apply to the 1-Wire interface. DEVICE OPERATION MODES With its two ports and two power modes the DS2404 can be operated in several ways. While the maximum voltage on the 1-Wire port (I/O) is always 6V, the maximum voltage on the 3-wire port (DQ) depends on the power mode and actual operating voltage ...

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... In addition, data should be organized as data packets with a length byte at the beginning and a CRC check at the end. Whenever one side has finished communication with the DS2404 it should write a token such as a “null-packet” into the scratchpad. A null-packet consists of three bytes that represent a zero length followed by a valid 16-bit CRC ...

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CRYSTAL PLACEMENT ON PCB Figure 18 3-WIRE WRITE DATA TIMING DIAGRAM Figure 19 3-WIRE READ DATA TIMING DIAGRAM Figure ...

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ABSOLUTE MAXIMUM RATINGS* Voltage on DATA to Ground Operating Temperature Range Storage Temperature Range Soldering Temperature ∗ This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the ...

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CAPACITANCE PARAMETER Input Capacitance Output Capacitance I/O (1-Wire) RESISTANCES PARAMETER Resistance to Ground RST DQ Resistance to Ground CLK Resistance to Ground AC ELECTRICAL CHARACTERISTICS: 3-WIRE PORT PARAMETER Data to CLK Setup CLK to Data Hold CLK to Data Delay ...

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NOTES: 1. All voltages are referenced to ground 2. 0.8V with 10ns maximum rise and fall time 2.4V and V = 0.4V, respectively. DQH DQL 4. Load capacitance = ...

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The reset low time (t RSTL ) otherwise, it could mask or conceal interrupt pulses. 21. When the battery is attached, the oscillator powers up in the off state. 22. The optimal sampling point for the master is as ...