ISPLSI1016EA-200LJ44 Lattice Semiconductor Corp., ISPLSI1016EA-200LJ44 Datasheet
ISPLSI1016EA-200LJ44
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ISPLSI1016EA-200LJ44 Summary of contents
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... Optimized Global Routing Pool Provides Global Interconnectivity Copyright © 2007 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. ...
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Functional Block Diagram Figure 1. ispLSI 1016EA Functional Block Diagram VCCIO I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O ...
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Boundary Scan Figure 2. Boundary Scan Waveforms and Timing Specifications TMS TDI T btch TCK TDO Data to be captured Data to be driven out Symbol t TCK [BSCAN test] clock pulse width btcp t TCK [BSCAN test] pulse width ...
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Absolute Maximum Ratings Supply Voltage V ................................ -0.5 to +7.0V CC Input Voltage Applied ........................ -2 Off-State Output Voltage Applied ..... -2 Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to ...
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Switching Test Conditions Input Pulse Levels Input Rise and Fall Time 10% to 90% Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see Figure 3) TEST ...
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External Timing Parameters 4 TEST 2 # PARAMETER COND Data Propagation Delay, 4PT Bypass, ORP Bypass pd1 Data Propagation Delay, Worst Case Path pd2 Clock Frequency with Internal Feedback max (Int.) ...
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Internal Timing Parameters 2 PARAM. # Inputs t 22 I/O Register Bypass iobp t 23 I/O Latch Delay iolat t 24 I/O Register Setup Time before Clock iosu t ioh 25 I/O Register Hold Time after Clock t 26 I/O ...
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Internal Timing Parameters PARAM. # Outputs t 49 Output Buffer Delay Output Buffer Delay, Slew Limited Adder I/O Cell OE to Output Enabled oen t 52 I/O Cell OE to Output Disabled odis t ...
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Timing Model I/O Cell Ded. In #28 I/O Reg Bypass I/O Pin #22 (Input) Input GRP Loading Register D Q RST #29 #59 # Reset Y1 Y0 GOE Derivations ...
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Maximum GRP Delay vs GLB Loads Power Consumption Power consumption in the ispLSI 1016EA device de- pends on two primary factors: the speed at which the device is operating and the number of Product Terms Figure 4. Typical Device Power ...
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Pin Description PLCC NAME PIN NUMBERS I I/O 3 15, 16, 17, 18, I I/O 7 19, 20, 21, 22, 13, 19, I I/O 11 25, 26, 27, 28, 23, I I/O ...
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Pin Configurations ispLSI 1016EA 44-Pin PLCC Pinout Diagram I/O 28 I/O 29 I/O 30 I/O 31 VCCIO 1. Pins have dual function capability which is software selectable. ispLSI 1016EA 44-Pin TQFP Pinout Diagram I/O 28 I/O 29 I/O 30 I/O ...
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Part Number Description ispLSI Device Family Device Number Speed 200 = 200 MHz fmax 125 = 125 MHz fmax 100 = 100 MHz fmax ispLSI 1016EA Ordering Information FAMILY fmax (MHz) tpd (ns) 200 200 125 ispLSI 125 100 100 ...