K4D551638F-TC40 Samsung, K4D551638F-TC40 Datasheet
![no-image](/images/manufacturer_photos/0/5/577/samsung_sml.jpg)
K4D551638F-TC40
Specifications of K4D551638F-TC40
Available stocks
Related parts for K4D551638F-TC40
K4D551638F-TC40 Summary of contents
Page 1
... K4D551638F-TC 256Mbit GDDR SDRAM Samsung Electronics reserves the right to change products or specification without notice 16Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM Revision 1.7 June 2004 - 1 - Target Spec 256M GDDR SDRAM Rev 1.7 (June 2004) ...
Page 2
... Revision 1.5 (March 18, 2004) - • Added K4D551638F-TC33 in the data sheet. Revision 1.4 (February 27, 2004) - • Added K4D551638F-TC36/40 in the data sheet. Revision 1.3 (December 5, 2003) • Changed VDD/VDDQ of K4D551638F-TC50 from 2. 2.6V + 0.1V Revision 1.2 (November 11, 2003) • "Wrtie-Interrupted by Read Function" is supported Revision 1.1 (October 13, 2003) • Defined ICC7 value Revision 1.0 (October 10, 2003) • ...
Page 3
... Differential clock input • No Write-Interrupted by Read Function ORDERING INFORMATION Part NO. K4D551638F-TC33 K4D551638F-TC36 K4D551638F-TC40 K4D551638F-TC50 K4D551638F-TC60* 1. K4D551638F-LC is the Lead Free package part number. 2. For the K4D551638F-TC60, VDD & VDDQ = 2. For the K4D551638F-TC36, VDD & VDDQ = 2.8V + 0.1V 4. For the K4D551638F-TC33, VDD & VDDQ = 2.8V ~ 2.95V ...
Page 4
... K4D551638F-TC PIN CONFIGURATION PIN DESCRIPTION CK,CK Differential Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe CAS Column Address Strobe WE Write Enable L(U)DQS Data Strobe L(U)DM Data Mask RFU Reserved for Future Use (Top View DDQ ...
Page 5
... K4D551638F-TC INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol CK, CK*1 Input CKE Input CS Input RAS Input CAS Input WE Input LDQS,UDQS Input/Output LDM,UDM Input Input/Output Input Input Power Supply Power Supply DDQ SSQ V Power Supply REF NC/RFU No connection/ Reserved for future use *1 : The timing reference point for the differential clocking is the cross point of CK and CK ...
Page 6
... K4D551638F-TC BLOCK DIAGRAM (4Mbit x 16I Bank) Bank Select CK,CK ADDR LCKE LRAS LCBR CK,CK CKE 16 Intput Buffer CK, CK Data Input Register Serial to parallel 4Mx16 4Mx16 4Mx16 4Mx16 Column Decoder Latency & Burst Length Programming Register LWE LCAS LWCBR Timing Register CS RAS CAS ...
Page 7
... K4D551638F-TC FUNCTIONAL DESCRIPTION • Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before VDDQ . - Apply VDDQ before VREF & VTT 2. Start clock and maintain stable condition for minimum 200us. ...
Page 8
... K4D551638F-TC MODE REGISTER SET(MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation ...
Page 9
... K4D551638F-TC EXTENDED MODE REGISTER SET(EMRS) The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by assert- ing low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register) ...
Page 10
... IL 6. For any pin under test input of 0V < For the K4D551638F-TC60 , VDD & VDDQ =2. For the K4D551638F-TC36 , VDD & VDDQ =2.8V + 0.1V and For the K4D551638F-TC33 , VDD & VDDQ = 2.8V ~ 2.95V Symbol ...
Page 11
... K4D551638F-TC DC CHARACTERISTICS Recommended operating conditions Unless Otherwise Noted, T Parameter Symbol Operating Current I CC1 (One Bank Active) Precharge Standby Current I P CC2 in Power-down mode Precharge Standby Current I N CC2 in Non Power-down mode Active Standby Current I P CC3 power-down mode Active Standby Current in ...
Page 12
... K4D551638F-TC AC OPERATING TEST CONDITIONS Parameter Input reference voltage for CK(for single ended) CK and CK signal maximum peak swing CK signal minimum slew rate Input Levels Input timing measurement reference level Output timing measurement reference level Output load condition Output CAPACITANCE (V =2.6V Parameter ...
Page 13
... K4D551638F-TC AC CHARACTERISTICS Parameter Symbol CK cycle time CL=3 tCK CK high level width tCH CK low level width tCL DQS out access time from CK tDQSCK Output access time from CK tAC Data strobe edge to Dout edge tDQSQ Read preamble tRPRE Read postamble tRPST CK to valid DQS-in ...
Page 14
... K4D551638F-TC AC CHARACTERISTICS (I) Parameter Symbol Row cycle time tRC Refresh row cycle time tRFC Row active time tRAS RAS to CAS delay for Read tRCDRD RAS to CAS delay for Write tRCDWR Row precharge time tRP Row active to Row active tRRD Last data in to Row precharge @Nor- ...
Page 15
... K4D551638F-TC Write Interrupted by a Read & burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered, any residual data from the burst write cycle must be masked by DM ...
Page 16
... K4D551638F-TC PACKAGE DIMENSIONS (66pin TSOP-II) #66 #1 (1.50) (0.71) NOTE REFERENCE ASS’Y OUT QUALITY #34 #33 22.22±0.10 (10×) 0.65TYP 0.30±0.08 0.65±0.08 (10× Target Spec 256M GDDR SDRAM Units : Millimeters (10×) (10×) +0.075 0.125 -0.035 0.10 MAX 0.25TYP [ ] 0.075 MAX 0×~8× Rev 1.7 (June 2004) ...