K4H281638D-TCB3 Samsung, K4H281638D-TCB3 Datasheet
K4H281638D-TCB3
Specifications of K4H281638D-TCB3
Related parts for K4H281638D-TCB3
K4H281638D-TCB3 Summary of contents
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D-die(x16) DDR SDRAM DDR SDRAM Specification Version 0 REV. 0.6 Oct. 21. 2002 ...
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D-die(x16) DDR SDRAM Revision History Version 0 (July, 2001) - First version for internal review Version 0.1 (September, 2001) - Changed spec to preliminary version Version 0.2(October,2001) - Changed final spec from preliminary spec. - Modificated typo. - Changed ...
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D-die(x16) DDR SDRAM Revision History Version 0.5 (Jan, 2002) - Added tRAP(Active to Read w/ Auto precharge command) Version 0.6 (Oct, 2002) - Modify DC current(IDD spec table) REV. 0.6 Oct. 21. 2002 - 3 - ...
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D-die(x16) DDR SDRAM Contents Revision History General Information 1. Key Features 1.1 Features 1.2 Operating Frequencies 2. Package Pinout & Dimension 2.1 Package Pintout 2.2 Input/Output Function Description 2.3 66 Pin TSOP(II)/MS-024FC Package Physical Dimension 3. Functional Description 3.1 ...
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D-die(x16) DDR SDRAM 3.3.7 Write Interrupted by a Read & DM 3.3.8 Write Interrupted by a Precharge & DM 3.3.9 Burst Stop 3.3.10 DM masking 3.3.11 Read With Auto Precharge 3.3.12 Write With Auto Precharge 3.3.13 Auto Refresh & ...
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D-die(x16) DDR SDRAM List of tables Table 1 : Operating frequency and DLL jitter Table 2. : Column address configurtion Table 3 : Input/Output function description Table 4 : Burst address ordering for burst length Table 5 : Bank ...
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D-die(x16) DDR SDRAM List of figures Figure 1 : 128Mb Package Pinout Figure 2 : Package dimension Figure 3 : State digram Figure 4 : Power up and initialization sequence Figure 5 : Mode register set Figure 6 : ...
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... D-die(x16) DDR SDRAM General Information Organization 166Mhz/ CL=2.5 K4H281638D-TCB3 8Mx16 K4H281638D-TLB3 Memory DRAM Small Classification Density and Refresh Organization Bank 1. SAMSUNG Memory : K 2. DRAM : 4 3. Small Classification H : DDR SDRAM 4. Density & Refresh 64 : 64M 4K/64ms 28 : 128M 4K/64ms ...
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D-die(x16) DDR SDRAM 1. Key Features 1.1 Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with ...
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D-die(x16) DDR SDRAM 2. Package Pinout & Dimension 2.1 Package Pinout DM is internally loaded to match DQ and DQS identically. 8Mb ...
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D-die(x16) DDR SDRAM 2.2 Input/Output Function Description SYMBOL TYPE CK, CK Input CKE Input CS Input RAS, CAS, WE Input *1 Input LDM,(U)DM BA0, BA1 Input Input I I/O LDQS,(U)DQS NC ...
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D-die(x16) DDR SDRAM 2.3 66pin TSOP-II Package Dimension #66 #1 (1.50) (0.71) NOTE REFERENCE ASS’ Y OUT QUALITY #34 #33 22.22 ± 0.10 (10 × ) 0.65TYP 0.30± 0.08 0.65 ± ...
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D-die(x16) DDR SDRAM 3. Functional Description 3.1 Simplified State Diagram MODE REGISTER SET POWER POWER APPLIED MRS IDLE CKEH POWER ACT DOWN CKEH CKE L ROW ACTIVE WRITE WRITEA READA READ WRITEA WRITE WRITEA READA PRE WRITEA PRE PRE ...
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D-die(x16) DDR SDRAM 3.2 Basic Functionality 3.2.1 Power-Up and Initialization Sequence The following sequence is required for POWER UP and Initialization. 1. Apply power and attempt to maintain CKE at a low state(all other inputs may be undefined.) - ...
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D-die(x16) DDR SDRAM 3.2.2 Mode Register Definition 3.2.2.1 Mode Register Set(MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and ...
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D-die(x16) DDR SDRAM Burst Length Address(A2, A1, A0 Table 4. Burst address ordering for burst length Mode Register Set Precharge Command All Banks MRS can be issued only at ...
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... READ command can be issued. Output Drive Strength The normal drive strength for all outputs is specified to be SSTL_2, Class II. Samsung supports a weak driver strength option, intended for lighter load and/or point-to-point environments. I-V curves for the normal drive strength and weak drive strength are included in 11.1~2 of this document. ...
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D-die(x16) DDR SDRAM 3.2.3 Precharge The precharge command is used to precharge or close a bank that has been activated. The precharge com- mand is issued when CS, RAS and WE are low and CAS is high at the ...
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D-die(x16) DDR SDRAM 3.2.5 Row Active The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock(CK). The DDR SDRAM has four independent banks, so two ...
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D-die(x16) DDR SDRAM 3.3 Essential Functionality for DDR SDRAM The essential functionality that is required for the DDR SDRAM device is described in this chapter 3.3.1 Burst Read Operation Burst Read operation in DDR SDRAM is in the same ...
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D-die(x16) DDR SDRAM 3.3.2 Burst Write Operation The Burst Write command is issued by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock(CK). The address inputs determine the starting column address. ...
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D-die(x16) DDR SDRAM 3.3.3 Read Interrupted by a Read A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is interrupted, the remaining addresses are overridden by ...
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D-die(x16) DDR SDRAM 3.3.5 Read Interrupted by a Precharge A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to precharge intervals. A precharge command to output ...
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D-die(x16) DDR SDRAM 3.3.6 Write Interrupted by a Write A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restric- tion that the interval that separates the commands must be ...
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D-die(x16) DDR SDRAM 3.3.7 Write Interrupted by a Read & burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one clock cycle before ...
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D-die(x16) DDR SDRAM 3.3.8 Write Interrupted by a Precharge & burst write operation can be interrupted before completion of the burst by a precharge of the same bank. Random column access is allowed. A write recovery time(tWR) ...
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D-die(x16) DDR SDRAM 3. For a Write with autoprecharge command, a new Bank Activate command may be issued to the same bank after tWR+tRP where tWR+tRP starts on the falling DQS edge that strobed in the last valid data ...
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D-die(x16) DDR SDRAM 6. When terminating a burst Read command, the BST command must be issued L cycles before the clock edge at which the output buffers are tristated, where L for read operations. This is shown in previous ...
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D-die(x16) DDR SDRAM 3.3.11 Read With Auto Precharge If a read with auto-precharge command is initiated, the DDR SDRAM automatically enters the precharge operation BL/2 clock later from a read with auto-precharge command when tRAS(min) is satisfied. If not, ...
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D-die(x16) DDR SDRAM 3.3.12 Write with Auto Precharge If A10 is high when write command is issued , the write with auto-precharge function is performed. Any new command to the same bank should not be issued until the internal ...
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D-die(x16) DDR SDRAM 3.3.13 Auto Refresh & Self Refresh Auto Refresh An auto refresh command is issued by having CS, RAS and CAS held low with CKE and WE high at the ris- ing edge of the clock(CK). All ...
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D-die(x16) DDR SDRAM 3.3.14 Power down The power down mode is entered when CKE is low and exited when CKE is high. Once the power down mode is initiated, all of the receiver circuits except clock, CKE and DLL ...
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D-die(x16) DDR SDRAM 4. Command Truth Table COMMAND Register Extended MRS Register Mode Register Set Auto Refresh Entry Refresh Self Refresh Exit Bank Active & Row Addr. Read & Auto Precharge Disable Column Address Auto Precharge Enable Write & ...
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D-die(x16) DDR SDRAM 5. Functional Truth Table Current State CS RAS CAS PRECHARGE L H STANDBY ACTIVE L H STANDBY ...
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D-die(x16) DDR SDRAM Current State CS RAS CAS WRITE READ with L H AUTO PRECHARGE L H (READA ...
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D-die(x16) DDR SDRAM Current State CS RAS CAS PRECHARG ING L H (DURING tRP ROW L H ACTIVATING L H (FROM ROW L L ACTIVE tRCD) ...
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D-die(x16) DDR SDRAM Current State CS RAS CAS RE FRESHING MODE L H REGISTER L H SETTING Address ...
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D-die(x16) DDR SDRAM CKE CKE Current State n-1 n SELF REFRESHING POWER ALL BANKS ...
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D-die(x16) DDR SDRAM 6. Absolute Maximum Rating Parameter Voltage on any pin relative to V Voltage on V & V supply relative DDQ Storage temperature Power dissipation Short circuit current Note : Permanent device damage may ...
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D-die(x16) DDR SDRAM Notes 1. Includes 25mV margin for DC offset on V bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes both of which may result in V REF 2.V is ...
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... DDR333(166Mhz, CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRCD=10*tCK, tRAS=7*tCK Read : repeat the same timing with random address changing *50% of data changing at every burst Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP K4H281638D- K4H281638D- K4H281638D- TCA2 TCB0 TCA0 (DDR266A) (DDR266B) (DDR200) ...
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D-die(x16) DDR SDRAM DD7A I : Operating current: Four bank operation 1. Typical Case : Vdd = 2.5V, T=25’ Worst Case : Vdd = 2.7V, T= 10’ Four banks are being interleaved with tRC(min), Burst ...
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D-die(x16) DDR SDRAM 8.2 AC Overshoot/Undershoot specification 8.2.1 Overshoot/Undershoot specification for Address and Control Pins Parameter Maximum peak amplitude allowed for overshoot (See Figure 1): Maximum peak amplitude allowed for undershoot (See Figure 1): The area between the overshoot ...
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D-die(x16) DDR SDRAM 8.2.2 Overshoot/Undershoot specification for Data Pins Parameter Maximum peak amplitude allowed for overshoot (See Figure 2): Maximum peak amplitude allowed for undershoot (See Figure 2): The area between the overshoot signal and VDD must be less ...
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D-die(x16) DDR SDRAM AC Timming Parameters & Specifications Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to ...
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D-die(x16) DDR SDRAM Parameter Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS Control & Address input pulse width DQ & DM input pulse width Power down exit time ...
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D-die(x16) DDR SDRAM 8. I/O Setup/Hold Plateau Derating I/O Input Level (mV) 280 This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF 310mV for a duration ...
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D-die(x16) DDR SDRAM 9. AC Operating Test Conditions (V =2.5V, V =2.5V DDQ A Parameter Input reference voltage for Clock Input signal maximum peak swing Input Levels ...
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D-die(x16) DDR SDRAM 11. IBIS: I/V Characteristics for Input and Output Buffers 11.1 Normal strength driver 1. The full variation in driver pulldown current from minimum to maximum process, temperature, and voltage will lie within the outer bounding lines ...
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D-die(x16) DDR SDRAM Pulldown Current (mA) Voltage Typical Typical (V) Low 0.1 6.0 0.2 12.2 0.3 18.1 0.4 24.1 0.5 29.8 0.6 34.6 0.7 39.4 0.8 43.7 0.9 47.5 1.0 51.3 1.1 54.1 1.2 56.2 1.3 57.9 1.4 59.3 ...
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D-die(x16) DDR SDRAM 11.2 Weak strength driver 1. The nominal pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a. 2. The full variation in driver pulldown current ...
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D-die(x16) DDR SDRAM Pulldown Current (mA) Voltage Typical Typical (V) Low 0.1 3.4 0.2 6.9 0.3 10.3 0.4 13.6 0.5 16.9 0.6 19.6 0.7 22.3 0.8 24.7 0.9 26.9 1.0 29.0 1.1 30.6 1.2 31.8 1.3 32.8 1.4 33.5 ...