K4J52324QC-BC20 Samsung, K4J52324QC-BC20 Datasheet
K4J52324QC-BC20
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K4J52324QC-BC20 Summary of contents
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... K4J52324QC 512Mbit GDDR3 SDRAM INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. ...
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... K4J52324QC Revision History Revision 1.5 (June 29, 2006) •.Added comment on page 28. Revision 1.4 (March 22, 2006) •.Added CKE condition in Intialization Sequence #4 on page 10. • Changed minimum delay from a read w/AP to write or write w/AP on page 50. Revision 1.3 (November 4, 2005) • Changed tRFC of -BC16 from 33tCK to 31tCK effective date code with WW0543. ...
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... Added Write Latency 5, 6, and 7 (clock) in the spec. • Added tWR_A 8 and 9 (clock) in the spec. Revision 0.1 (December 18, 2003) • Changed CL of -GC12 from 9tCK to 10tCK • Changed tCK(max) from 3.0ns to 3.3ns Revision 0.0 (December 18 , 2003) - K4J52324QC-B A .... 136FBGA, Leaded B .... 136FBGA, Lead-free Target Spec - 3/59 - 512M GDDR3 SDRAM ...
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... ORDERING INFORMATION Part NO. K4J52324QC-BJ11 K4J52324QC-BJ12 K4J52324QC-BC14 K4J52324QC-BC16 K4J52324QC-BC20 K4J52324QC-A*** is leaded package part number GENERAL DESCRIPTION FOR 2M x 32Bit x 8 Bank GDDR3 SDRAM The K4J52324QC is 536,870,912 bits of hyper synchronous data rate Dynamic RAM organized 2,097,152 words by 32 bits, fabricated with SAMSUNG extremely high performance ...
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... K4J52324QC PIN CONFIGURATION Normal Package (Top View VDDQ VDD B VSSQ DQ0 C VDDQ DQ2 D VSSQ WDQS0 E VDDQ DQ4 F VDD DQ6 G VSS VSSQ H VREF A1 J VSSA RFU1 K VDDA A10 L VSS VSSQ M VDD DQ24 N VDDQ DQ26 P VSSQ WDQS3 R VDDQ DQ28 T VSSQ DQ30 V VDDQ ...
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... K4J52324QC INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol Type Clock: CK and CK are differential clock inputs. CMD, ADD inputs are sampled on the crossing of the posi- CK, CK Input tive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). CK and CK should be maintained stable except self-refresh mode. ...
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... K4J52324QC Mirror Function The GDDR3 SDRAM provides a mirror function (MF) ball to change the physical location of the control lines and all address lines which helps to route devices back to back. The MF ball will affect RAS, CAS, WE, CS and CKE on balls H3, F5, H9, F9 and H4 respectively and A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, BA0, BA1 and BA2 on balls K4, H2, K3, M4, K9, H11, K10, L9, K11, M9, K2, L4, G4, G9 and H10 respectively and only detects a DC input ...
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... K4J52324QC BLOCK DIAGRAM (2Mbit x 32I Bank) Bank Select iCK ADDR LCKE LRAS LCBR iCK CKE WDQS Input Buffer Input Buffer Data Input Register Serial to parallel Column Decoder Latency & Burst Length ...
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... K4J52324QC FUNCTIONAL DESCRIPTION Simplified State Diagram Power Applied Power On Precharge PREALL MRS EMRS Write A PREALL = Precharge All Banks MRS = Mode Register Set EMRS = Extended Mode Register Set REFS = Enter Self Refresh REFSX = Exit Self Refresh REFA = Auto Refresh REFS REFSX MRS ...
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... K4J52324QC INITIALIZATION GDDR3 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. 1. Apply power and keep CKE/RESET at low state ( All other inputs may be undefined) - Apply VDD and VDDQ simultaneously - Apply VDDQ before Vref. ( Inputs are not recognized as valid until after V 2 ...
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... K4J52324QC MODE REGISTER SET(MRS) The mode register stores the data for controlling the various operating modes of GDDR3 SDRAM. It programs CAS latency, addressing mode, test mode and various vendor specific options to make GDDR3 SDRAM useful for variety of dif- ferent applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for the proper operation ...
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... K4J52324QC PROGRAMMABLE IMPEDANCE OUTPUT BUFFER AND ACTIVE TERMINATOR The GDDR3 SDRAM is equipped with programmable impedance output buffers and Active Terminators. This allows a user to match the driver impedance to the system. To adjust the impedance, an external precision resistor(RQ) is connected between the ZQ pin and Vss. The value of the resistor must be six times of the desired output impedance. ...
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... K4J52324QC CAS LATENCY (READ LATENCY) The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 4~11 clocks READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n+m ...
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... K4J52324QC WRITE LATENCY The Write latency (WL) is the delay, in clock cycles, between the registration of a WRITE command and the availability of the first bit of input data. The latency can be set from clocks depending in the operating frequency and desired current draw. When the write latencies are set clocks, the input receivers never turn off when the WRITE command is registered ...
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... K4J52324QC TEST MODE The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7 set to zero, and bits A0-A6 and A8- A11 set to the desired values. Test mode is entered by issuing a MODE REGISTER SET command with bit A7 set to one, and bits A0- A6 and A8-A11 set to the desired values. Test mode functions are specific to each Dram Manufacturer and its exact functions are hidden from the user ...
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... K4J52324QC EXTENDED MODE REGISTER SET(EMRS) The extended mode register stores the data output driver strength and on-die termination options. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The GDDR3 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode regis- ter) ...
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... K4J52324QC DLL ENABLE/DISABLE The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after disabling the DLL for debugging or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 20K clock cycles must occur before a READ command can be issued ...
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... K4J52324QC Vendor ID Read RES CKE CKE COMMAND High DQ[3:0] Ta2 Tb3 Tc4 EMRS EMRS PRE >20ns >20ns Vendor Code MRD Precharge EMRS EMRS Vendor_ID All Banks Vendor_ID On Off DON’T CARE - 18/59 - 512M GDDR3 SDRAM ...
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... K4J52324QC Clock frequency change sequence during the device operation Both existing tCK and desired tCK are in DLL-On mode - Change frequency from existing frequency to desired frequency - Issue Precharge All Banks command - Issue MRS command to reset the DLL while other fields are valid and required 20K tCK to lock the DLL - Issue Precharge All Banks command ...
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... K4J52324QC BOUNDARY SCAN FUNCTION GENERAL INFORMATION The 512Mb GDDR3 incorporates a modified boundary scan test mode as an optional feature. This mode doesn’t operate in accor- dance with IEEE Standard 1149.1 - 1990. To save the current GDDR3 ball-out, this mode will scan parallel data input and output and the scanned data through WDQS0 pin controlled by an add-on pin, SEN which is located at V-4 of 136 ball package ...
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... K4J52324QC BOUNDARY SCAN EXIT ORDER BIT# BALL BIT# BALL D-11 24 *Note : 1. When the device is in scan mode, the mirror function will be disabled and none of the pins are remapped. 2. Since the other input of the MUX for DM0 tied to GND, the device will output the continuous zeros after scanning a bit #67, if the chip stays in scan shift mode. ...
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... K4J52324QC SCAN DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS PARAMETER/CONDITON Input High (Logic 1) Voltage Input Low (Logic 0) Voltage *Note : 1. The parameter applies only when SEN is asserted. 2. All voltages referenced to GND. SCK SEN LOW SSH SOE Pins under Test SCK SEN SSH SOE SOUT ...
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... K4J52324QC SCAN AC ELECTRICAL CHARACTERISTICS PARAMETER/CONDITON Clock Clock cycle time Scan Command Time Scan enable setup time Scan enable hold time Scan command setup time for SSH, SOE# and SOUT Scan command hold time for SSH, SOE# and SOUT Scan Capture Time ...
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... K4J52324QC COMMANDS Below Truth table-COMMANDs provides a quick reference of available commands. This is followed by a verbal descrip- tion of each command. Two additional Truth Tables appear following the operation section : these tables provide current state/next state information. TRUTH TABLE - COMMANDs Name (Function) DESELECT (NOP) ...
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... K4J52324QC DESELECT The DESELECT function (/CS high) prevents new commands from being executed by the DDR(x32). The GDDR3(x32) SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to instruct selected GDDR3(x32) to perform a NOP (/CS LOW). This pre- vents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected ...
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... K4J52324QC AUTO PRECHARGE Auto precharge is a feature which performs the same individual-bank precharge function described above, but without requiring an explicit command. This is accomplished by using A8 to enable auto precharge in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is auto- matically performed upon completion of the READ or WRITE burst ...
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... K4J52324QC DATA TERMINATOR DISABLE (BUS SNOOPING FOR READ COMMAND) The DATA TERMINATOR DISABLE COMMAND is detected by the device by snooping the bus for READ commands excluding /CS. The GDDR3 DRAM will disable its Data terminators when a READ command is detected. The terminators are disable CL-1 Clocks after the READ command is detected two rank system both dram devices will snoop the bus for READ commands to either device and both will disable their terminators if a READ command is detected ...
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... K4J52324QC OPERATIONS BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a banks within the GDDR3 SDRAM, a row in that bank must be "opened." This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated. After a row is opened with an ACTIVE command, a READ or WRITE command may be issued ...
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... K4J52324QC READs READ bursts are initiated with a READ command, as below figure. The start- ing column and bank addresses are provided with the READ command and auto precharge is either enabled or disabled for that burst access. If auto pre- charge is enabled, the row being accessed is precharged at the completion of the burst after t has been met ...
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... K4J52324QC Data Output Timing ( CK# CK 1.6 RDQS DQ(Last data valid) DQ(First data no longer valid) 5 All DQs and RDQS, collectively Data Output Timing ( CK# CK 1.6 RDQS 5 All DQs and RDQS, collectively 1.6 RDQS 5 All DQs and RDQS, collectively Note : 1. t represents the skew between the 8 DQ lines and the respective RDQS pin. ...
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... K4J52324QC READ Burst T0 /CK CK COMMAND READ Bank a, ADDRESS Col RDQS DQ T0 /CK CK COMMAND READ Bank a, ADDRESS Col RDQS n=data-out from column n. NOTE : 2. Burst length = 4 3. Three subsequent elements of data-out appear in the programmed order following Shown with nominal t 5 ...
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... K4J52324QC Consecutive READ Bursts T0 /CK CK COMMAND READ Bank a, ADDRESS Col n RDQS ( data-out from column n (or column b). NOTE : 2. Burst length = 4 3. Three subsequent elements of data-out appear in the programmed order following Three subsequent elements of data-out appear in the programmed order following DQ b. ...
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... K4J52324QC Nonconsecutive READ Bursts T0 /CK CK COMMAND READ Bank a, ADDRESS Col RDQS DQ T0 /CK CK COMMAND READ Bank a, ADDRESS Col RDQS ( data-out from column n (or column b). NOTE : 2. Burst length = 4 3. Three subsequent elements of data-out appear in the programmed order following DQ n. ...
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... K4J52324QC Random READ Accesses T0 /CK CK COMMAND READ Bank a, ADDRESS Col n RDQS DQ T0 /CK CK COMMAND READ Bank a, ADDRESS Col n RDQS ( data-out from column n (or column x or column x or column b or column g). NOTE : 2. Burst length = 4 3. n’ b’ or g’ indicates the next data-out following respectively 4 ...
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... K4J52324QC READ to WRITE T0 /CK CK COMMAND READ Bank ADDRESS Col n RDQS WDQS Termination data-out from column n. NOTE : data-in from column b. 3. Burst length = 4 4. One subsequent element of data-out appears in the programmed order following Data-in elements are applied following the programmed order. ...
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... K4J52324QC READ to PRECHARGE T0 /CK CK COMMAND READ Bank a, ADDRESS Col n RDQS DQ T0 /CK CK COMMAND READ Bank a, ADDRESS Col n RDQS DQ NOTE ( data-out from column n (or column b Burst length = 4 3. Three subsequent elements of data-out appear in the programmed order following Three subsequent elements of data-out appear in the programmed order following DQ b. ...
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... K4J52324QC WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is pre- charged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled ...
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... K4J52324QC WRITE Burst T0 /CK CK COMMAND WRITE Bank a, ADDRESS Col b t (NOM) t DQSS DQSS WDQS (MIN) t DQSS DQSS WDQS (MAX) t DQSS DQSS WDQS DQ DM NOTE data-in for column Three subsequent elements of data-in are applied in the programmed order following DI b. ...
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... K4J52324QC Consecutive WRITE to WRITE T0 CK# CK COMMAND WRITE NOP Bank ADDRESS Col b t (NOM) DQSS WDQS etc. = data-in for column b, etc. NOTE : 2. Three subsequent elements of data-in are applied in the programmed order following Three subsequent elements of data-in are applied in the programmed order following DI n. ...
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... K4J52324QC Nonconsecutive WRITE to WRITE T0 /CK CK COMMAND WRITE NOP Bank, ADDRESS Col b t (NOM) DQSS WDQS etc. = data-in for column b, etc. NOTE : 2. Three subsequent elements of data-in are applied in the programmed order following Three subsequent elements of data-in are applied in the programmed order following DI n. ...
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... K4J52324QC Random WRITE Cycles T0 /CK CK COMMAND WRITE NOP Bank ADDRESS Col b t (NOM) DQSS WDQS DQ DM NOTE etc. = data-in for column b, etc etc. = the next data - in following DI b. etc., according to the programmed burst order. 3. Programmed burst length = 4 cases shown. ...
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... K4J52324QC WRITE to READ T0 T1 /CK CK COMMAND WRITE NOP Bank ADDRESS Col (NOM) DQSS DQSS WDQS DQ DM RDQS t t (MIN) DQSS DQSS WDQS DQ DM RDQS t t (MAX) DQSS DQSS WDQS DQ DM RDQS data-in for column b. NOTE : 2. Three subsequent elements of data-in the programmed order following DI b. ...
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... K4J52324QC WRITE to PRECHARGE T0 T1 /CK CK COMMAND WRITE NOP Bank ADDRESS Col (NOM) DQSS DQSS WDQS (MIN) DQSS DQSS WDQS (MAX) DQSS DQSS WDQS DQ DM NOTE data-in for column Three subsequent elements of data-in the programmed order following DI b. ...
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... K4J52324QC PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (t CHARGE command is issued. Input A8 determines whether one or all banks are to be precharged, and in the case where only one bank precharged, inputs BA0, BA1, BA2 select the bank. When all banks are to be precharged, inputs BA0, BA1, BA2 are treated as “ ...
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... K4J52324QC GDDR3 tFAW Definition For eight bank GDDR3 devices, there is a need to limit the number of activates in a rolling window to ensure that the instantaneous current supplying capability of the devices is not exceeded. To reflect the true capability of the DRAM instan- taneous current supply, the same parameter tFAW(four activate window) as DDR2 is defined. ...
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... K4J52324QC TRUTH TABLE - Clock Enable (CKE) CKEn-1 CKEn CURRENT STATE Power-Down L L Self Refresh Power-Down L H Self Refresh All Banks Idle H L Bank(s) Active All Banks Idle NOTES : 1. CKEn is the logic state of CKE at clock edge n; CKEn-1was the state of CKE at the previous clock edge. ...
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... K4J52324QC TRUTH TABLE - CURRENT STATE BANK n CURRENT STATE /CS /RAS /CAS H X Any Idle Row Active Read (Auto-Precharge L H Disable Write (Auto-Precharge L H Disabled NOTES : 1. This table applies when CKE n-1 (if the previous state was self refresh) ...
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... K4J52324QC Read w/ Auto- : Starts with registration of an READ command with auto precharge enabled and ends Precharge Enabled when tRP has been met. Once t Write w/ Auto- : Starts with registration of a WRITE command with auto precharge enabled and ends Precharge Enabled when t 5. The following states must not be interrupted by any executable command ; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states ...
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... K4J52324QC TRUTH TABLE - CURRENT STATE BANK n CURRENT STATE /CS /RAS /CAS H X Any Idle Row Activating Active Prechrging Read L H (Auto-Precharge L H Disable Write L H (Auto-Precharge L H Disabled Read L H (With ...
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... K4J52324QC 3. Current state definitions : Idle : The bank has been precharged, and t Row Active : A row in the bank has been activated, and t No data bursts/accesses and no register accesses are in progress. Read : A READ burst has been initiated, with auto precharge disabled. Write : A WRITE burst has been initiated, with auto precharge disabled. ...
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... DQ and DM input slew rate must not deviate from DQS by more than 10%. If the DQ,DM and DQS slew rate is less than 3V/ns, timing is longer than referenced to the mid-point but to the VIL(AC) maximum and VIH(AC) minimum points. 6. VIH overshoot: VIH(max) = VDDQ + 0.5V for a pulse width VIL undershoot: VIL(min)=0.0V for a pulse width 7. K4J52324QC-BJ** 8. K4J52324QC-BC OL(DC) max for -BJ** is 0.84V Symbol V ...
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... K4J52324QC CLOCK INPUT OPERATING CONDITIONS Recommended operating conditions ( Parameter/ Condition Clock Input Mid-Point Voltage; CK and /CK Clock Input Voltage Level; CK and /CK Clock Input Differential Voltage; CK and /CK Clock Input Differential Voltage; CK and /CK Clock Input Crossing Point Voltage; CK and /CK Note: 1. This provides a minimum of 1.16V to a maximum of 1.36V for -BC part and 1.3V ~ 1.5V for -BJ part 2 ...
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... K4J52324QC DC CHARACTERISTICS-I ( 0°C ≤ Tc ≤85°C ; VDD=2.0V + 0.1V, VDDQ=2.0V + 0.1V Parameter Symbol Operating Current I CC1 (One Bank Active) Precharge Standby Current I P CC2 in Power-down mode Precharge Standby Current I N CC2 in Non Power-down mode Active Standby Current I P CC3 power-down mode Active Standby Current in ...
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... K4J52324QC AC CHARACTERISTICS (I-I) Parameter DQS out access time from CK CK high-level width CK low-level width CL=11 CL=10 CK cycle time CL=9 CL=8 CL=7 WRITE Latency DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS Active termination setup time Active termination hold time DQS input high pulse width ...
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... K4J52324QC AC CHARACTERISTICS (I-II) Parameter DQS out access time from CK CK high-level width CK low-level width CL=11 CL=10 CK cycle time CL=9 CL=8 CL=7 WRITE Latency DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS Active termination setup time Active termination hold time DQS input high pulse width ...
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... K4J52324QC AC CHARACTERISTICS II-I Parameter Row active time Row cycle time Refresh row cycle time RAS to CAS delay for Read RAS to CAS delay for Write Row precharge time Row active to Row active Last data in to Row precharge (PRE or Auto-PRE) t Last data in to Read command ...
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... K4J52324QC IBIS : I/V Characteristics for Input and Output Buffers (1) OCD (40 Ω) Pulldown Current (mA) Voltage Minimum (V) 0.1 2.4 0.2 4.7 0.3 7.0 0.4 9.3 0.5 11.5 0.6 13.6 0.7 15.7 0.8 17.7 0.9 19.6 1.0 21.4 1.1 23.2 1.2 24.8 1.3 26.3 1.4 27.7 1.5 29 -10 -15 -20 -25 -30 -35 -40 Maximum 2.8 5.5 8.3 11.0 13.7 16.4 19.0 21.6 24.2 26.7 29.1 31.6 34.0 36.3 38.5 Pull- Voltage (V) - 57/59 - 512M GDDR3 SDRAM Pullup Current (mA) Minimum -2.4 -4.7 -7.0 -9.2 -11.4 -13.4 -15.4 -17.1 -18.8 -20.3 -21.7 -22.9 -23.9 -24.8 -25 Min Max Rev. 1.5 June 2006 Maximum -3.1 -6.2 -9.2 -12.1 -14.9 -17.7 -20.3 -22.8 -25.2 -27.5 -29.6 -31.6 -33.3 -34.9 -36.3 ...
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... K4J52324QC Pull-Down Voltage (V) - 58/59 - 512M GDDR3 SDRAM Min Max 13 15 Rev. 1.5 June 2006 ...
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... K4J52324QC PACKAGE DIMENSIONS (FBGA) 0.12 Max 0.45 ± 0.05 0.35 ± 0.05 1.20 Max A1 INDEX MARK 11.0 <Top View> 0.8x11=8.8 0 0.40 <Top View: See the balls through the package> Ball existing Depopulated ball - 59/59 - 512M GDDR3 SDRAM 14.0 0 ...