MACH130-20JC Lattice Semiconductor Corp., MACH130-20JC Datasheet

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MACH130-20JC

Manufacturer Part Number
MACH130-20JC
Description
High-density EE CMOS programmable logic, 20ns
Manufacturer
Lattice Semiconductor Corp.
Datasheet

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MACH130-15/20
High-Density EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
The MACH130 is a member of the high-performance
EE CMOS MACH 1 family. This device has approxi-
mately six times the logic macrocell capability of the
popular PAL22V10 without loss of speed.
The MACH130 consists of four PAL blocks intercon-
nected by a programmable switch matrix. The switch
matrix connects the PAL blocks to each other and to all
input pins, providing a high degree of connectivity
between the fully-connected PAL blocks. This allows
designs to be placed and routed efficiently.
84 Pins
64 Macrocells
15 ns t
18 ns t
66.6 MHz f
70 Inputs
PD
PD
FINAL
Commercial
Industrial
CNT
COM’L: -15/20
IND: -18/24
The MACH130 macrocell provides either registered or
combinatorial outputs with programmable polarity. If a
registered configuration is chosen, the register can be
configured as D-type or T-type to help reduce the
number of product terms. The register type decision can
be made by the designer or by the software. All
macrocells can be connected to an I/O cell. If a buried
macrocell is desired, the internal feedback path from the
macrocell can be used, which frees up the I/O pin for use
as an input.
64 Outputs
64 Flip-flops; 4 clock choices
4 “PAL26V16” Blocks
Pin-compatible with MACH131, MACH230,
MACH231, MACH435
Lattice Semiconductor
Publication# 14131
Issue Date: April 1995
Rev. H
Amendment /0

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MACH130-20JC Summary of contents

Page 1

... EE CMOS MACH 1 family. This device has approxi- mately six times the logic macrocell capability of the popular PAL22V10 without loss of speed. The MACH130 consists of four PAL blocks intercon- nected by a programmable switch matrix. The switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks ...

Page 2

... I/O Cells 16 16 Macrocells AND Logic Array and Logic Allocator 26 Switch Matrix AND Logic Array and Logic Allocator OE Macrocells 16 I/O Cells 16 I/O – I MACH130-15/ CLK /I , CLK / CLK /I , CLK / 14131H-1 ...

Page 3

... Note: Pin-compatible with MACH131, MACH230, MACH231, and MACH435. PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V = Supply Voltage CC PLCC/CQFP PLCC MACH130-15/20 74 GND I ...

Page 4

... The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. MACH130-15/20 (Com’l) OPTIONAL PROCESSING Blank = Standard Processing OPERATING CONDITIONS C = Commercial ( +70 C) ...

Page 5

... The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. MACH130-18/24 (Ind) OPTIONAL PROCESSING Blank = Standard Processing OPERATING CONDITIONS I = Industrial (– +85 C) ...

Page 6

... I/O cells; the other two control the last eight macrocells. The Logic Allocator The logic allocator in the MACH130 takes the 64 logic product terms and allocates them to the 16 macrocells as needed. Each macrocell can be driven product terms. The design software automatically configures the logic allocator when fitting the design into the device ...

Page 7

... Switch Matrix Figure 1. MACH130 PAL Block MACH130-15/20 Output Enable Output Enable Asynchronous Reset Asynchronous Preset I/O Cell Output M Macro 0 Cell I/O Cell Output M Macro 1 Cell I/O Cell Output M Macro 2 Cell I/O Cell ...

Page 8

... OUT (Note 0 Max (Note 3) OUT 5V MHz CC A (Note 4) and I (or I and OZL IH OZH MACH130-15/20 (Com’ + +4. +5.25 V Min Typ Max Unit 2.4 V 0.5 V 2 – –10 A – ...

Page 9

... MHz OUT D-type T-type LOW HIGH D-type + T-type D-type ) CNT T-type 1/( MACH130-15/20 (Com’l) Typ Unit -15 -20 Min Max Min Max Unit ...

Page 10

... VIN = 5.25 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) VCC = MHz (Note 4) MACH130-18/24 (Ind – + ...

Page 11

... Test Conditions VIN = 2.0 V VCC = 5 VOUT = 2 MHz -18 Min 12 D-type T-type 13.5 0 7.5 LOW HIGH 7.5 D-type 40 T-type 38 D-type 53 T-type 44 1/(tWL + tWH) 66 MACH130-18/24 (Ind) Typ Unit -24 Max Min Max Unit 14 MHz ...

Page 12

... Output, LOW I (mA –3 –2 –1 –25 –50 –75 –100 –125 –150 Output, HIGH I (mA –2 – –20 –40 –60 –80 –100 Input MACH130-15/ 1.0 14131H (V) OH 14131H 14131H-6 ...

Page 13

... The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register Frequency (MHz) MACH130-15/20 MACH130 60 70 14131H-7 13 ...

Page 14

... Furthermore, jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. 14 200 lfpm air 400 lfpm air 600 lfpm air 800 lfpm air MACH130-15/20 Typ PLCC Unit C ...

Page 15

... Gate t WL 14131H- Registered Input t HIR Input V T Register Clock t ICO V T Output Register Clock 14131H-13 MACH130-15/ 14131H PDL Latched Output (MACH 2, 3, and GWS Gate Width (MACH 2, 3, and ICS ...

Page 16

... Input pulse amplitude 3 Input rise and fall times 2 ns–4 ns typical SIL HIL Latched Input (MACH 2 and 4) t IGOL Latched Input and Output (MACH 2, 3, and 4) MACH130-15/ IGO V T 14131H-15 t PDLL SLL V ...

Page 17

... Gate t WICL 14131H-17 Input, I/ Feedback Registered V T Output t ARR Clock V T 14131H- Outputs + V OL Output Disable/Enable MACH130-15/20 t WIGL Input Latch Gate Width (MACH 2 and 4) t APW Asynchronous Preset 0. 0.5V 14131H- 14131H- APR ...

Page 18

... Apply Output Commercial 300 390 5 pF MACH130-15/20 OUTPUTS Will be Steady Will be Changing from Will be Changing from Changing, State Unknown Center Line is High- Impedance “Off” State KS000010-PAL Test Point 14131H-22 Measured ...

Page 19

... All frequencies except f MAX other measured AC parameters. f ured directly. ” (SECOND CHIP MACH130-15/ type is the mini- MAX + t ). Usually, this minimum feedback.” MAX . Because this involves no MAXIR + the sum of SIR HIR + t ). The clock widths are nor- ...

Page 20

... Min Pattern Data Retention Time Max Reprogramming Cycles 20 bipolar parts result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. Min Units 10 Years 20 Years 100 Cycles MACH130-15/20 Test Conditions Max Storage Temperature Max Operating Temperature Normal Programming Conditions ...

Page 21

... INPUT/OUTPUT EQUIVALENT SCHEMATICS ESD Protection Input 100 k Preload Feedback Circuitry Input I/O MACH130-15/20 CC 100 14131H-24 21 ...

Page 22

... Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met Power-Up Reset Waveform MACH130-15/20 can rise to its steady state, two CC rise must be monotonic. Max 10 See Switching Characteristics V CC ...

Page 23

... All MACH 2 devices support both preload and observability. Contact individual programming vendors in order to verify programmer support. On Preload Off Mode Figure 2. Preload/Reset Conflict Set Reset Figure 3. Combinatorial Latch MACH130-15/20 Preloaded HIGH Preloaded HIGH 14131H-26 14131H-27 23 ...

Page 24

... REF .032 TOP VIEW *For reference only. BSC is an ANSI standard for Basic Space Centering. 28 .062 .083 .042 .056 1.000 REF .007 .013 .090 .130 .165 .180 SIDE VIEW MACH130-15/20 1.090 1.130 .013 .021 SEATING PLANE 16-038-SQ PL 084 DF79 8-1-95 ae ...

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