MACH220-20JC Lattice Semiconductor Corp., MACH220-20JC Datasheet
MACH220-20JC
Available stocks
Related parts for MACH220-20JC
MACH220-20JC Summary of contents
Page 1
... PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently. The MACH220 has two kinds of macrocell: output and buried. The output macrocell provides registered, latched, or combinatorial outputs with programmable BLOCK DIAGRAM ...
Page 2
I/O 0 – I/O 5 I/O 6 – I I/O Cells I/O Cells Macrocells Macrocells Macrocells AND Logic Array and Logic Allocator AND Logic Array ...
Page 3
... Note: Pin-compatible with MACH120 and MACH221. PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V = Supply Voltage CC PLCC MACH220-10/12/15/ I GND ...
Page 4
... The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. MACH220-10/12/15/20 (Com’l) OPTIONAL PROCESSING Blank = Standard Processing OPERATING CONDITIONS C = Commercial ( +70 C) ...
Page 5
... The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. MACH220-14/18/24 (Ind) OPTIONAL PROCESSING Blank = Standard Processing OPERATING CONDITIONS I = Industrial (– +85 C) ...
Page 6
... The Logic Allocator The logic allocator in the MACH220 takes the 48 logic product terms and allocates them to the 12 macrocells as needed. Each macrocell can be driven product terms. The design software automatically configures the logic allocator when fitting the design into the device ...
Page 7
... Matrix Figure 1. MACH220 PAL Block MACH220-10/12/15/20 Output Enable Output Enable Asynchronous Reset Asynchronous Preset I/O Cell Output Macro Cell M 0 Buried Macro Cell M 1 I/O Cell Output Macro M Cell ...
Page 8
... (Note 0 Max (Note 3) OUT MHz CC A (Note 4) and I (or I and OZL IH OZH MACH220-10 (Com’l) ) Operating + with +4. +5.25 V Min Typ Max 2.4 0.5 2.0 0.8 10 –100 10 –100 –30 –130 205 Unit V ...
Page 9
... Test Conditions MHz OUT D-type T-type LOW HIGH D-type T-type D-type ) CNT T-type D-type T-type LOW HIGH MACH220-10 (Com’l) Typ Unit -10 Min Max Unit 10 ns 6 MHz ...
Page 10
... Input, I/O, or Feedback to Output Disable ER Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 10 MACH220-10 (Com’l) -10 Min Max Unit ...
Page 11
... VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) VCC = MHz (Note 4) and I (or I and OZL IH OZH MACH220-12/15/20 (Com’l) ) Operating + with +4. +5.25 V Min Typ Max 2.4 ...
Page 12
... D-type 83.3 ) CNT T-type 76.9 83.3 1/( D-type 12 13 T-type LOW 6 HIGH 6 1/( 83.3 WICL WICH MACH220-12/15/20 (Com’l) Typ Unit = -15 -20 Max Min Max Min Max Unit ...
Page 13
... These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit for test conditions. 3. Parameters measured with 24 outputs switching. -12 Min Max MACH220-12/15/20 (Com’l) -15 -20 Min Max Min Max Unit ...
Page 14
... VIN = 0 V, VCC = Max (Note 2) VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) VCC = MHz (Note 4) MACH220-14/18/24 (Ind – + with ...
Page 15
... D-type 1/( T-type 61.5 D-type 57 T-type 66.5 1/(tWL + tWH) 8 7 D-type 14.5 16 T-type 7.5 LOW 7.5 HIGH 1/(tWICL + tWICH ) 66.5 2 7.5 19.5 MACH220-14/18/24 (Ind) Typ Unit -18 -24 Min Max Min Max Unit 13 14 MHz 38 30.5 MHz ...
Page 16
... These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 2. See Switching Test Circuit for test conditions. 3. Parameters measured with 24 outputs switching. 16 -14 Min Max 19.5 14.5 10 19.5 14.5 10 14.5 14.5 MACH220-14/18/24 (Ind) -18 -24 Min Max Min Max Unit ...
Page 17
... Output, LOW I (mA –3 –2 –1 –25 –50 –75 –100 –125 –150 Output, HIGH I (mA –2 – –20 –40 –60 –80 –100 Input MACH220-10/12/15/ 1.0 14130I (V) OH 14130I 14130I-6 17 ...
Page 18
... The selected “typical” pattern is a 12-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register Frequency (MHz) MACH220-10/12/15/20 MACH220 14130I-7 ...
Page 19
... Furthermore, jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. 200 lfpm air 400 lfpm air 600 lfpm air 800 lfpm air MACH220-10/12/15/20 Typ PLCC Units 10 C/W ...
Page 20
... Gate t WL 14130I- Registered Input t HIR Input V T Register Clock t ICO V T Output Register Clock 14130I-13 MACH220-10/12/15/ 14130I PDL Latched Output (MACH 2, 3, and GWS Gate Width (MACH 2, 3, and ICS ...
Page 21
... Input pulse amplitude 3 Input rise and fall times 2 ns–4 ns typical SIL HIL Latched Input (MACH 2 and 4) t IGOL Latched Input and Output (MACH 2, 3, and 4) MACH220-10/12/15/ IGO V T 14130I-15 t PDLL SLL ...
Page 22
... Gate t WICL 14130I-17 Input, I/ Feedback Registered V T Output t ARR Clock V T 14130I- Outputs + V OL Output Disable/Enable MACH220-10/12/15/20 t WIGL Input Latch Gate Width (MACH 2 and 4) t APW Asynchronous Preset 0. 0.5V 14130I- 14130I- APR ...
Page 23
... Apply Output Commercial 300 390 5 pF MACH220-10/12/15/20 OUTPUTS Will be Steady Will be Changing from Will be Changing from Changing, State Unknown Center Line is High- Impedance “Off” State KS000010-PAL Test Point 14130I-22 Measured ...
Page 24
... All frequencies except f MAX other measured AC parameters. f ured directly. ” (SECOND CHIP MACH220-10/12/15/ type is the mini- MAX + t ). Usually, this minimum feedback.” MAX . Because this involves no MAXIR + the sum of SIR HIR + t ). The clock widths are nor- ...
Page 25
... Min Pattern Data Retention Time Max Reprogramming Cycles bipolar parts result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. Min Units 10 Years 20 Years 100 Cycles MACH220-10/12/15/20 Test Conditions Max Storage Temperature Max Operating Temperature Normal Programming Conditions 25 ...
Page 26
... INPUT/OUTPUT EQUIVALENT SCHEMATICS ESD Protection Input 100 k Preload Feedback Circuitry Input I/O MACH220-10/12/15/20 CC 100 14130I-24 ...
Page 27
... Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met Power-Up Reset Waveform MACH220-10/12/15/20 can rise to its steady state, two CC rise must be monotonic. Max 10 See Switching Characteristics V CC ...
Page 28
... All MACH 2 devices support both preload and observability. Contact individual programming vendors in order to verify programmer support Preload Off Mode Figure 2. Preload/Reset Conflict Set Reset Figure 3. Combinatorial Latch MACH220-10/12/15/20 Preloaded HIGH Preloaded HIGH 14130I-26 14130I-27 ...
Page 29
... REF .032 TOP VIEW *For reference only. BSC is an ANSI standard for Basic Space Centering. .062 .083 .042 .056 .007 .013 .090 .130 .165 .180 SIDE VIEW MACH220-10/12/15/20 .800 .890 REF .930 .013 .021 SEATING PLANE 16-038-SQ PL 068 DA78 6-28- ...