MT9171AP Zarlink Semiconductor, MT9171AP Datasheet
MT9171AP
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MT9171AP Summary of contents
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... Status DSTo/Do Receive Prescrambler Interface CDSTo/ CDo Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1999-2006, Zarlink Semiconductor Inc. All Rights Reserved. 2 ISO -CMOS ST-BUS FAMILY MT9171/72 Digital Subscriber Interface Circuit Digital Network Interface Circuit MT9171/72AE ...
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... OSC2 C4/TCK F0/CLD 15 10 F0o/RCK CDSTi/CDi 14 11 DSTi/Di CDSTo/CDo 13 12 DSTo/Do VSS 24 PIN SSOP Figure 2 - Pin Connections Description . 2 Zarlink Semiconductor Inc. Data Sheet • MS2 6 24 LOUT DIS Precan MS1 8 22 OSC1 MS0 9 21 OSC2 ...
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... An OUT Disable. When held to logic “1”, L OUT functions normally. An internal pulldown (50 kΩ) is provided on OUT Connect Zarlink Semiconductor Inc. Data Sheet the internal path from L to the ’, OUT is disabled (i.e., output = V ). When Bias ...
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... Channel Time 16 4 Zarlink Semiconductor Inc. Data Sheet ...
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... In DUAL port mode the C and D channels are accessed via the CD port (Figure 7) while in SINGL port mode they are transferred through the DV port (Figures 5, 6) along with the B1 and B2 channels. MT9171/72 implemented using the MT9171/ line 5 Zarlink Semiconductor Inc. Data Sheet ...
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... 15.6 µsec Channel Time 1 Channel Time 2 B1-Channel C-Channel Figure Port - 160 kbit/s (Modes 0,4) 6 Zarlink Semiconductor Inc. Data Sheet ...
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... Channel Time 16 Figure Port (Modes 2, Figure Port (Modes 1, entering the DNIC this signal passes through Zarlink Semiconductor Inc. Data Sheet ...
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... E=Enabled X=Not Applicable Blanks are disabled MT9171/72 Operating Mode SLV MAS DUAL SINGL Table 1 - Mode Select Pins 8 Zarlink Semiconductor Inc. Data Sheet MO DN D-C C-D ODE ...
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... Input F0o Output RCK Output Input F0o Output Input F0o Output F0o Output RCK Output F0o Output Input F0o Output Table 3 - Pin Configurations 9 Zarlink Semiconductor Inc. Data Sheet C4/TCK Name Input/Output C4 Input TCK Output C4 Input C4 Input C4 Output TCK Output C4 Output C4 Input ...
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... Channel • • • • • • • • Most Bit 7 Bit 6 Bit 5 Bit 4 Significant Bit (First) 3.9 µsec Figure 9 - ST-BUS Format 10 Zarlink Semiconductor Inc. Data Sheet Channel Channel Channel Channel Least Bit 3 Bit 2 Bit 1 Bit 0 Significant ...
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... When set to ’0’, the data prescrambler and deprescrambler are disabled. MT9171/72 bit 2 bit 3 bit 4 DRR BRS DINB Default Mode Selection (Refer to Table 4a) Description 11 Zarlink Semiconductor Inc. Data Sheet c hannel is written to the bit 5 bit 6 bit 7 PSEN ATTACK TxHK ...
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... DSTi internally looped back into DSTo for system diagnostics internally looped back into L OUT 1 DSTo is internally looped back into DSTi for end-to-end testing. 12 Zarlink Semiconductor Inc. Data Sheet bit 5 bit 6 bit 7 PSEN ATTACK TxHK 1 When ’0’, the echo ...
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... Loopback FUN PSWAP Default Mode Selection Description Table 5 - Diagnostic Register Future Functionality Function Table 6 - Status Register 13 Zarlink Semiconductor Inc. Data Sheet bit 5 bit 6 bit 7 DLO Not Used (Refer to Table 4a) is set When set to ’0’, OUT Bias ...
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... L IN OUT DIS pin high or by writing DLO (bit 6) of the Diagnostics Register to OUT level. L DIS has an internal pull-down to allow this pin to be Bias OUT 14 Zarlink Semiconductor Inc. Data Sheet receiving the IN . The transmit signal Baud ...
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... SYNC OUT 7 0 Figure 11 - Frame Format - 80 kbit/s (Modes MT9171/72 Bit 5 Bit 4 Bit Figure 10 - Data & Line Encoding Zarlink Semiconductor Inc. Data Sheet Bit 2 Bit 1 Bit Bias SYNC ...
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... OSC1 D.C. coupled, Frequency locked 10.24 MHz clock. OSC2 Refer to AC Electrical NC Characteristics F0o Clock Timing C1 = 0.33 µF DN Mode. Note: Low leakage diodes (1 & 2) are required so To Next DNIC that the DC voltage Zarlink Semiconductor Inc. Data Sheet SYNC For 80 kbit/s: C2’ ...
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... MUR405 R2 = 390 Ω Ω 10.24 MHz XTAL C3=33pF=C4 Note: Low leakage diodes (1 & 2) are required so that the DC voltage Zarlink Semiconductor Inc. Data Sheet For 80 kbit/s: C2’ = 3.3 nF 2:1 1.0 µF 68 Volts Supply (Typ) 2.5 Joules 0.02 Watt C1 = 0.33 µF ≈ Bias ...
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... 0 7 1.8 O Bias Zarlink Semiconductor Inc. Data Sheet Min. Max. Units -0 -0 °C -65 +150 750 mW ) unless otherwise stated. Units Test Conditions V °C V for 400 mV noise margin V for 400 mV noise margin ...
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... OUT 500 OUT Lout ) 100 Ref ) C 20 OUT Lout ) 0.1 Ref ( 3.2 4.3 4.6 OUT o 19 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions µ kΩ µA Units Test Conditions V pp kΩ f =160 kHz Baud MHz ppm % Normal temp. & ...
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... C4W t 50 F0S t 50 F0H t 244 F0W J ±15 C (see Figure 17). C Channel 0 Channel 0 Bit 7 Bit 6 t C4P t t F0S F0H t F0W Φ Zarlink Semiconductor Inc. Data Sheet Test Conditions Master Mode - Note Note 2 t C4W t C4W ...
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... 3.125 CLDS t 3.125 CLDH t 6.05 CLDW CLDP CLDH CLDS t CLDW Zarlink Semiconductor Inc. Data Sheet Test Units Conditions Typ.* Max. 6.25 ms 3.125 =40pF L 1.56 ms 1.56 ms 2.925 ...
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... DS t 4.5 2 Sym. Min. Typ.* Max 3.0 80 2.2 L 3.0 160 2.2 22 Zarlink Semiconductor Inc. Data Sheet Max. Units Test Conditions ns ns 120 ns C =40pF L 140 ns C =40pF Test Units Conditions Max. ns µ =40pF ...
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... Min. Typ.* Max 5.0 80 3.4 L 4.0 160 3.0 to Slave L at 3/4baud frequency. OUT IN Bit Cell Bit Cell Zarlink Semiconductor Inc. Data Sheet Units Test Conditions dB SNR≥16.5dB (300 kHz bandlimited noise) km attenuation - 6.9 dB/km attenuation - 10.0 dB/km km attenuation - 8.0 dB/km attenuation - 11.5 dB/ ...
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... TCK 0.4V 2.0V Di CDI 0. 2.4V CDo 0.4V RCK 2.4V Do 0.4V Figure 21 - Data Timing for Slave Modem Mode MT9171/ ¼ Zarlink Semiconductor Inc. Data Sheet t TD ...
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