ADP3203 Analog Devices, ADP3203 Datasheet

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ADP3203

Manufacturer Part Number
ADP3203
Description
Manufacturer
Analog Devices
Datasheet

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a
GENERAL DESCRIPTION
The ADP3203 is a 1- or 2-phase hysteretic peak current dc-to-dc
buck converter controller dedicated to power a mobile
processor’s core. The optimized low voltage design is powered
from the 3.3 V system supply and draws only 10 µA maximum
in shutdown. The nominal output voltage is set by a 5-bit VID
code. To accommodate the transition time required by the
newest processors for on-the-fly VID changes, the ADP3203
features high speed operation to allow a minimized inductor size
that results in the fastest change of current to the output. To
further allow for the minimum number of output capacitors to
be used, the ADP3203 features active voltage positioning with
ADOPT optimal compensation to ensure a superior load transient
response. The output signal interfaces with the ADP3415
MOSFET driver that is optimized for high speed and high effi-
ciency for driving both the top and bottom MOSFETs of the buck
converter. The ADP3203 is capable of controlling the synchronous
rectifier to extend battery lifetime in light load conditions.
ADOPT is a trademark of Analog Devices.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
FEATURES
Pin Selectable 1- or 2-Phase Operation
Static and Dynamic Current Sharing Characteristics
Backward Compatible to IMVP-II
Superior Load Transient Response with ADOPT
Noise Blanking for Speed and Stability
Synchronous Rectifier Control Extends Battery Life
Smooth Output Transition During VID Code Change
Cycle-by-Cycle Current Limiting
Hiccup or Latched Overload Protection
Transient Glitch-Free Power Good
Soft Start Eliminates Power-On In-Rush Current Surge
2-Level Overvoltage and Reverse Voltage Protection
APPLICATIONS
IMVP-II and IMVP-III Core DC-to-DC Converters
Fixed Voltage Mobile CPU Core DC-to-DC Converters
Notebook/Laptop Power Supplies
Programmable Output Power Supplies
Optimal Positioning Technology
TM
Core Controller for Mobile CPUs
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
DPRSLP
HYSSET
PWRGD
DSHIFT
BSHIFT
DSLP
2-Phase IMVP-II and IMVP-III
BOM
VID4
VID3
VID2
VID1
VID0
SD
ADP3203
FUNCTIONAL BLOCK DIAGRAM
ENABLE _UVLO MAIN BIAS
VID MUX AND
PWRGD BLANKER
SELECTOR
SHIFT
EN
CORE
PM MODULE
SS-HICCUP TIMER AND OCP
5-BIT VID
CLIM
FIXED
VCC
DAC
AND
REF
GND
HYSTERESIS
SHIFT-MUX
SETTING
AND
COREGD MONITOR
VR
© Analog Devices, Inc., 2002
SR CONTROL
OVP AND RVP
ADP3203
CURRENT
SPLITTER
SENSE
PHASE
MUX
VR
www.analog.com
OUT2
OUT1
CS2
CS1
CS+
CS–
RAMP
REG
DACOUT
DRVLSD
COREFB
SS
CLAMP

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ADP3203 Summary of contents

Page 1

... Notebook/Laptop Power Supplies Programmable Output Power Supplies GENERAL DESCRIPTION The ADP3203 2-phase hysteretic peak current dc-to-dc buck converter controller dedicated to power a mobile processor’s core. The optimized low voltage design is powered from the 3.3 V system supply and draws only 10 µA maximum in shutdown ...

Page 2

... ADP3203–SPECIFICATIONS 100 pF, C =0.047 F, R OUT1 OUT2 SS DPRSHIFT are open; BOM = H, DSLP = H, DPRSLP = L, unless otherwise noted.) Current sunk by a pin has a positive sign, sourced by a pin has a negative sign. Negative sign is disregarded for min and max values. Parameter ...

Page 3

... V, BOM = –10 A HYSSET I = –100 A HYSSET = 1.23 V, BOM = –10 A HYSSET I = –100 A HYSSET = 1.27 V, BOM = –10 A HYSSET I = –100 A HYSSET –3– ADP3203 Min Typ Max ± 1 ± 1 2.5 3 130 180 ± 1 –3 60 100 150 –8 –10 – ...

Page 4

... ADP3203 Parameter SHIFT SETTING Battery Shift Current Battery Shift Reference Voltage Deep Sleep Shift Current Deep Sleep Shift Reference Voltage SHIFT CONTROL INPUTS BOM Threshold (CMOS Input) DSLP Threshold (V -Level CMOS Input DPRSLP Mode Threshold (CMOS Input) LOW SIDE DRIVE CONTROL ...

Page 5

... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3203 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...

Page 6

... ADP3203 Pin Mnemonic Function 1 HYSSET Hysteresis Set. This is an analog I/O pin whose output is a fixed voltage reference and whose input is a current that is programmed by an external resistance to ground. The current is used in the IC to set the hysteretic currents for the core comparator and the current limit comparator. Modification of the resistance will affect both the hysteresis of the feedback regulation and the current limit set- point and hysteresis ...

Page 7

... V5_ALWAYS). If the external FET is used, this implementation will keep the core voltage clamped until the ADP3203 has power reapplied, thus keeping protection for the CPU even after a hard-failure power-down and restart (e.g., a shorted top or bottom FET). ...

Page 8

... ADP3203 Pin Mnemonic Function 21 OUT2 Output to Driver 2. This digital output pin is used to command the state of the switched node via the driver. It should be connected to the IN pin of the ADP3415 driver that corresponds to the second of two channels. 22 CS1 Current Sense, Channel 1. This high impedance analog input pin is used to provide negative feedback of the current information for the first of two channels ...

Page 9

... ZERO SCALE 0.600 0.595 7.2mV 0.590 0.585 0.580 AMBIENT TEMPERATURE – C TPC 3. DAC Output Voltage vs. Temperature REV. 0 Typical Performance Characteristics–ADP3203 HIGH LOW 60 80 100 TPC 4. Power Good vs. Relative Core Voltage Variation 100 10 0.1 0. 100 TPC 5. Soft Start Timing vs. Timing Capacitor ...

Page 10

... ADP3203 MBRS130LT3 D6 MBRS130LT3 D5 Figure 1. Typical Application –10– REV. 0 ...

Page 11

... GMUXSEL signal precedes any VID code change with a few nanoseconds, while in an IMVP-III system, it follows it with a maximum 12 µs delay. To comply with both specifications, the ADP3203 has a VID register in front of the DAC inputs that is written by a short pulse generated at the rising or falling edge of the GMUXSEL signal IMVP-II configuration, if the external VID multiplex settling time is longer than the internal VID register’ ...

Page 12

... COREFB, which is also used for Power Good monitoring but not for voltage regulation, and an output pin, CLAMP. The CLAMP pin defaults to a low state at startup of the ADP3203 and remains low until an overvoltage or reverse voltage condition is detected. If either condition is detected, the CLAMP pin is switched and latched to the VCC pin ...

Page 13

... Control Circuitry ADP3203, Control Components 12. If the ADP3203 cannot be placed as previously recom- mended, care should be taken to keep the device and surrounding components away from radiation sources (e.g., from power inductors) and capacitive coupling from noisy power nodes ...

Page 14

... Figure 4 shows a simplified block diagram of a 3-phase converter using the control principle (3) implemented with the ADP3203, the 3-phase member of the ADP320x family. As Figure 4 shows, in the multiphase configuration the ripple current signal is multiplexed from all channels. During the on time of any given channel, its current is compared to the upper threshold of the hysteretic comparator ...

Page 15

... MathSoft’s MathCAD has been developed. Please contact ADI for further information. PHASE PHASE SW2 Q4 HYSTERETIC PHASE CORE SPLITTER COMPARATOR OUT 2 OUT 1 –15– ADP3203 R L1 CS1 V OUT R L2 CS2 R E LOAD C O CURRENT SENSE MUX CS1 ...

Page 16

OUTLINE DIMENSIONS 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters 9.80 9.70 9. 4.50 4.40 4. PIN 1 0.65 1.20 BSC MAX 0.15 0.05 0.30 0.20 0.19 COPLANARITY SEATING 0.09 PLANE 0.10 ...

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