AD9814 Analog Devices, AD9814 Datasheet
AD9814
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AD9814 Summary of contents
Page 1
... The internal regis- ters are programmed through a 3-wire serial interface, and pro- vide adjustment of the gain, offset, and operating mode. The AD9814 operates from a single +5 V power supply, typi- cally consumes 330 mW of power, and is packaged in a 28-lead SOIC. ...
Page 2
... AD9814–SPECIFICATIONS ANALOG SPECIFICATIONS 2 MHz, PGA Gain = 1, Input Range = 4 V, unless otherwise noted.) Parameter CONVERSION RATE 3-Channel Mode with CDS 1-Channel Mode with CDS ACCURACY (Entire Signal Path) ADC Resolution 1 Integral Nonlinearity (INL) INL @ 10 MHz Differential Nonlinearity (DNL) DNL @ 10 MHz No Missing Codes Guaranteed ...
Page 3
... Linear input signal range is from when the CCD’s reference level is clamped the AD9814’s input clamp. A larger reset transient can be tolerated by using the 3 V clamp level instead of the nominal 4 V clamp level. Linear input signal range will be from when using the 3 V clamp level. ...
Page 4
... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9814 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
Page 5
... The ADC output codes’ standard deviation is calculated in LSB, and converted to an equivalent voltage, using the relation- ship 1 LSB = 4 V/16384 = 244 mV. The noise is then referred to the input of the AD9814 by dividing by the PGA gain. CHANNEL-TO-CHANNEL CROSSTALK In an ideal three channel system, the signal in one channel will not influence the signal level of another channel ...
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... AD9814 ANALOG t INPUTS CDSCLK1 t CDSCLK2 t ADCLK t ADCCLK t ADCLK OUTPUT DATA R (N–2) G (N–2) G (N–2) B (N–2) B (N–2) R (N–1) R (N–1) G (N–1) G (N–1) B (N–1) B (N–1) D<7:0> HIGH LOW BYTE BYTE ANALOG INPUTS ...
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... PRB C2ADR t C2ADF t ADCLK t OD PIXEL (N–3) PIXEL (N–3) HIGH BYTE LOW BYTE Figure 4. 1-Channel SHA Mode Timing –7– AD9814 PIXEL (N+1) R (N) R (N) G (N) G (N) HIGH LOW HIGH LOW HIGH LOW BYTE BYTE BYTE BYTE BYTE BYTE PIXEL (N–2) PIXEL (N– ...
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... AD9814 ADCCLK OUTPUT HIGH BYTE DATA DB13–DB6 <D7:D0> PIXEL N OEB R/Wb SDATA SCLK t LS SLOAD SDATA SCLK t LS SLOAD LOW LOW BYTE HIGH BYTE BYTE DB5–DB0 N+1 N+1 PIXEL Figure 5. Digital Output Data Timing ...
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... A voltage applied to this pin will be subtracted from the voltages applied to the red, green and blue inputs in the first amplifier stage of the AD9814. The input clamp is disabled in this mode. For more information, see the Circuit Operation section. Timing for this mode is shown in Figure 2. CDSCLK1 should be grounded in this mode ...
Page 10
... Setting Bit D4 high will enable the CDS mode of operation, and setting this bit low will en- able the SHA mode of operation. Bit D3 sets the dc bias level of the AD9814’s input clamp. This bit should always be set high for the 4 V clamp bias, unless a CCD with a reset feedthrough transient exceeding used ...
Page 11
... Table V. Offset Register Settings • • • • • • –11– AD9814 D1 D0 Gain (V/V) LSB 1.013 • • • 5 5 LSB ...
Page 12
... S4 closes and the internal bias voltage is connected to the analog input. The bias voltage charges the external 0.1 F input capacitor, level-shifting the CCD signal into the AD9814’s input common-mode range. The time constant of the input clamp is determined by the internal 5 k resistance and the external 0 ...
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... R2 Figure 12. SHA-Mode Used with External DC Offset Programmable Gain Amplifiers The AD9814 uses one Programmable Gain Amplifier (PGA) for each channel. Each PGA has a gain range from 1x (0 dB) to 5.8x (15.5 dB), adjustable in 64 steps. Figure 6 shows the PGA gain as a function of the PGA register code. Although the gain curve is approximately “ ...
Page 14
... AD9814. A separate power supply may be used for DRVDD, the digital driver supply, but this supply pin should still be decoupled to the same ground plane as the rest of the AD9814. The loading of the digital outputs should be minimized, either by using short traces to the digital ASIC using external digital buffers ...
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... PIN 1 0.0118 (0.30) 0.0040 (0.10) REV. 0 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead, 300 Mil SOIC (R-28) 0.7125 (18.10) 0.6969 (17.70 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65 0.3937 (10.00) 0.1043 (2.65) 0.0926 (2.35) 0.0500 0.0192 (0.49) SEATING 0.0125 (0.32) (1.27) PLANE 0.0138 (0.35) 0.0091 (0.23) BSC –15– AD9814 0.0291 (0.74) 45 0.0098 (0.25 0.0500 (1.27) 0.0157 (0.40) ...