STA529Q STMicroelectronics, STA529Q Datasheet - Page 35

• Manufacturer Part Number: STA529Q
• Description: IC AMP 2X100MW CLASS D 52VFQFPN
• Manufacturer: STMicroelectronics
• Series: Sound Terminal™r
• Type: Class Dr

Specifications of STA529Q

• Output Type: 2-Channel (Stereo)
• Max Output Power X Channels @ Load: 100mW x 2 @ 16 Ohm
• Voltage - Supply: 1.5 V ~ 1.95 V
• Features: Depop, I²C, I²S, Mute, Volume Control
• Mounting Type: Surface Mount
• Package / Case: 52-VFQFN, 52-VFQFPN
• Ic Function: FFX Audio Codec Analogue & Digital Inputs, Class D Amplifier
• Brief Features: Up To 96dB Dynamic Range, FFX Class-D Driver
• Supply Voltage Range: 1.55V To 1.95V, 1.8V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8879

STA529
11
11.1
Table 22.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x0A
0x0B
0x0C
0x0D
0x14
0x15
0x16
0x17
0x18
0x19
0x1E
0x1F
0x20
0x21
0x22
Address
FFXCFG0
FFXCFG1
MVOL
LVOL
RVOL
TTF0
TTF1
TTP0
TTP1
S2PCFG0
S2PCFG1
P2SCFG0
P2SCFG1
PLLCFG0
PLLCFG1
PLLCFG2
PLLCFG3
PLLPFE
PLLST
ADCCFG
CKOCFG
MISC
PADST0
PADST1
Name
Registers
This section describes the set-up register used in the device.
Summary
Register summary
PLL_DIREC
BYP_ UNL
CLKOUT_
OSC_DIS
UNLOCK
T_PROG
BICLK_
BICLK_
PDATA_LENGTH[1:0]
PDATA_LENGTH[1:0]
MUTE
L1_R2
Bit 7
STRB
STRB
STRB
PLL_
PLL_
DIS
POW_STBY
MUTE_ON_
BICLK2PLL
PLL_PWD_
PGA[2:0]
INVALID
BYPASS
LRCLK_
LRCLK_
FRAC_
STRB_
STATE
Bit 6
CTRL
LEFT
LEFT
CLKOUT_SEL[1:0]
P2P_FS_RANGE[2:0]
PLL_PWDN
Doc ID 13095 Rev 2
PLL_BYP_
SDATAO_
VOL_ON
SHARE_
DITHER_DISABLE[1:0]
SOFT_
STATE
Bit 5
BILR
ACT
PWM_MODE[1:0]
BICLK_OS[1:0]
BICLK_OS[1:0]
MSB_FIRST
MSB_FIRST
BIN_SOFT
SET_VOL_MASTER[7:0]
TIM_TS_POWUP[15:8]
SET_VOL_RIGHT[7:0]
TIM_TS_POWUP[7:0]
START
PFE1A
TIM_TS_FAULT[15:8]
Bit 4
SET_VOL_LEFT[7:0]
INSEL
TIM_TS_FAULT[7:0]
FRAC_INPUT[15:8]
FRAC_INPUT[7:0]
Reserved
Reserved
ADC_FS_RANGE[1:0]
PFE1B
Bit 3
STBY
PWM_SHIFT[1:0]
MAP_L[1:0]
MAP_L[1:0]
NDIV[5:0]
DATA_FORMAT[2:0]
DATA_FORMAT[2:0]
BYPASS_
Reserved
Reserved
PFE2A
TIM_SOFT_VOL[3:0]
CALIB
Bit 2
IDF[3:0]
CLKENBL
P2P_IN_
PFE2B
Bit 1
ADC
MAP_R[1:0]
MAP_R[1:0]
Reserved
Registers
MASTER_
MASTER_
CLKENBL
Reserved
RESET_
CORE_
MODE
MODE
FAULT
Bit 0
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