AD7887 Analog Devices, AD7887 Datasheet

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AD7887

Manufacturer Part Number
AD7887
Description
Manufacturer
Analog Devices
Datasheet

Specifications of AD7887

Resolution (bits)
12bit
# Chan
2
Sample Rate
125kSPS
Interface
Ser,SPI
Analog Input Type
SE-Uni
Ain Range
Uni (Vref)
Adc Architecture
SAR
Pkg Type
SOIC,SOP

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FEATURES
Specified for V
Flexible power/throughput rate management
Shutdown mode: 1 μA max
One or two single-ended inputs
Serial interface: SPI®/QSPI™/MICROWIRE™/DSP compatible
8-lead narrow SOIC and MSOP packages
APPLICATIONS
Battery-powered systems (personal digital assistants,
Instrumentation and control systems
High speed modems
GENERAL DESCRIPTION
The AD7887 is a high speed, low power, 12-bit analog-to-digital
converter (ADC) that operates from a single 2.7 V to 5.25 V
power supply. The AD7887 is capable of 125 kSPS throughput
rate. The input track-and-hold acquires a signal in 500 ns and
features a single-ended sampling scheme. The output coding for
the AD7887 is straight binary, and the part is capable of
converting full power signals of up to 2.5 MHz.
The AD7887 can be configured for either dual- or single-channel
operation via the on-chip control register. There is a default
single-channel mode that allows the AD7887 to be operated as a
read-only ADC. In single-channel operation, there is one
analog input (AIN0) and the AIN1/V
function. This V
internal 2.5 V reference, or the V
external reference to provide the reference voltage for the part.
This external reference voltage has a range of 2.5 V to V
analog input range on AIN0 is 0 to V
In dual-channel operation, the AIN1/V
function, providing a second analog input channel. In this case,
the reference voltage for the part is provided via the V
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
medical instruments, mobile communications)
DD
REF
of 2.7 V to 5.25 V
pin allows the user access to the part’s
REF
pin can be overdriven by an
REF
REF
REF
.
pin assumes its V
pin assumes its AIN1
2.7 V to 5.25 V, Micropower, 2-Channel,
DD
DD
pin. As
125 kSPS, 12-Bit ADC in 8-Lead MSOP
REF
. The
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
a result, the input voltage range on both the AIN0 and AIN1
inputs is 0 to V
CMOS construction ensures low power dissipation of typically
2 mW for normal operation and 3 μW in power-down mode.
The part is available in an 8-lead, 0.15-inch-wide narrow body
SOIC and an 8-lead MSOP package.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
AIN1/
V
AIN0
Smallest 12-bit dual-/single-channel ADC; 8-lead MSOP
package.
Lowest power 12-bit dual-/single-channel ADC.
Flexible power management options, including automatic
power-down after conversion.
Read-only ADC capability.
Analog input range from 0 V to V
Versatile serial input/output port (SPI/QSPI/MICROWIRE/
DSP compatible).
V
REF
DD
FUNCTIONAL BLOCK DIAGRAM
SOFTWARE
AIN1/V
CONTROL
LATCH
DD
.
REF
DIN
©2006 Analog Devices, Inc. All rights reserved.
MUX
REDISTRIBUTION
I/P
CONTROL LOGIC
SAR + ADC
CS
Figure 1.
CHARGE
BUF
SPORT
DAC
2.5V
REF
DOUT
T/H
REF
SCLK
.
AD7887
COMP
AD7887
www.analog.com
GND

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AD7887 Summary of contents

Page 1

... The AD7887 is capable of 125 kSPS throughput rate. The input track-and-hold acquires a signal in 500 ns and features a single-ended sampling scheme. The output coding for the AD7887 is straight binary, and the part is capable of converting full power signals 2.5 MHz. The AD7887 can be configured for either dual- or single-channel operation via the on-chip control register ...

Page 2

... AD7887 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications .................................................................. 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configurations and Function Descriptions ........................... 7 Typical Performance Characteristics ............................................. 8 Terminology ...................................................................................... 9 Control Register.............................................................................. 10 REVISION HISTORY 9/06—Rev Rev. C Updated Format..................................................................Universal Change to Absolute Maximum Ratings ...

Page 3

... Dual-channel mode Single-channel mode, external reference Single-channel mode, internal reference Functional from 1.2 V Very high impedance if internal reference disabled Typically 10 nA 200 μA SOURCE 200 μA SINK AD7887 ...

Page 4

... AD7887 Parameter CONVERSION RATE Throughput Time 2 Track/Hold Acquisition Time Conversion Time POWER REQUIREMENTS Normal Mode (Mode 2) Static Operational (f = 125 kSPS) SAMPLE Using Standby Mode (Mode 4) Using Shutdown Mode (Modes 1, 3) Standby Mode 6 6 Shutdown Mode Normal Mode Power Dissipation ...

Page 5

... Data setup time prior to SCLK rising edge Data valid to SCLK hold time SCLK high pulse width SCLK low pulse width CS rising edge to DOUT high impedance Power-up time from shutdown ) and timed from a voltage level of 1 quoted in the timing characteristics is the true bus relinquish 8 AD7887 SCLK ...

Page 6

... AD7887 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter V to AGND DD Analog Input Voltage to AGND Digital Input Voltage to AGND Digital Output Voltage to AGND REF /REF to AGND IN OUT Input Current to Any Pin Except Supplies Operating Temperature Range Commercial Temperature Range ...

Page 7

... Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7887 and also frames the serial data transfer. When the AD7887 operates in its default mode, the CS pin also acts as the shutdown pin such that with the CS pin high, the AD7887 is in its power-down mode. ...

Page 8

... AD7887 TYPICAL PERFORMANCE CHARACTERISTICS 0 –10 –30 –50 –70 –90 –110 Figure 5. Dynamic Performance 73 EXT REFERENCE 72.5 72.0 71.5 71.0 0.15 10.89 21.14 INPUT FREQUENCY (kHz) Figure 6. SNR vs. Input Frequency 4096 POINT FFT SAMPLING 125kSPS f = 10kHz IN SNR = 71dB = 5V DD 31.59 42.14 Rev Page – 5.5V/2.7V DD –77 100mV p-p SINE WAVE ON V ...

Page 9

... N-bit converter with a sine wave input is given by Signal to (Noise + Distortion) = (6. 1.76) dB Thus for a 12-bit converter, this is 74 dB. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7887 defined ...

Page 10

... CONTROL REGISTER The control register on the AD7887 is an 8-bit, write-only register. Data is loaded from the DIN pin of the AD7887 on the rising edge of SCLK. The data is transferred on the DIN line at the same time as the conversion result is read from the part. This requires 16 serial clocks for every data transfer ...

Page 11

... The AD7887 is a fast, low power, 12-bit, single-supply, single- channel/dual-channel ADC. The part can be operated from (2 3.6 V) supply or from (4. 5.25 V) supply. When operated from either supply, the AD7887 is capable of throughput rates of 125 kSPS when provided with a 2 MHz clock. ...

Page 12

... AIN1/V input impedance of the reference buffer, which is in the region of gigaohms. When the internal reference is enabled, the input impedance seen at the pin is typically 10 kΩ. When the AD7887 is operated in two-channel mode, the reference is taken from V internally, not from the on-chip 2 ...

Page 13

... SCLK edge after the falling edge mode on the 16 The first falling SCLK edge after the CS falling edge causes the part to power up again. When the AD7887 is in Mode 1, that is, PM1 = PM0 = 0, the part enters shutdown on the rising edge of CS and power up from shutdown on the falling edge brought high during the conversion in this mode, the part immediately enters shutdown ...

Page 14

... CS does not have any effect on the power-down status of the AD7887. Figure 18 shows the general diagram of the operation of the AD7887 in this mode. On the first falling SCLK edge after CS goes low, all on-chip circuitry starts to power up. It takes approximately 5 μs for the AD7887 internal circuitry to be fully powered up result, a conversion (or sample-and-hold acquisition) should not be initiated during this 5 μ ...

Page 15

... FOUR LEADING ZEROS + CONVERSION RESULT DIN DATA IN CONTROL REGISTER DATA IS LOADED ON THE FIRST EIGHT CLOCKS. PM1 = 0 AND PM0 = 1 TO KEEP THE PART IN THIS MODE Figure 17. Mode 2 Operation Rev Page THE PART POWERS DOWN ON CS RISING EDGE AS PM1 AND PM0 = AD7887 ...

Page 16

... AD7887 THE PART ENTERS SHUTDOWN AT THE END OF CONVERSION AS PM1 = 1 AND PM0 = SCLK FOUR LEADING ZEROS + CONVERSION RESULT DOUT DATA IN DIN CONTROL REGISTER DATA IS LOADED ON THE FIRST EIGHT CLOCKS. PM1 = 1 AND PM0 = 0 THE PART ENTERS SHUTDOWN AT THE END OF CONVERSION AS PM1 = 1 AND PM0 = 0 ...

Page 17

... CS initiates the data transfer and conversion process. For some modes, the falling edge of CS wakes up the part. In all cases, it gates the serial clock to the AD7887 and puts the on-chip track/hold into track mode. The input signal is sampled on the second rising edge of the SCLK input after the falling edge of CS ...

Page 18

... AD7887 to ADSP-21xx The ADSP-21xx family of DSPs are easily interfaced to the AD7887 with an inverter between the serial clock of the ADSP- 21xx and the AD7887. This is the only glue logic required. The SPORT control register should be set up as follows: Table 7. SPORT0 Control Register Setup ...

Page 19

... P1.1 and P1.2) to shift data in and out—see Figure 26. AD7887 1 ADDITIONAL PINS OMITTED FOR CLARITY. Figure 26. Interfacing to the 8051 Using Input/Output Ports AD7887 to PIC16C6x/PIC16C7x 1 MC68HC11 The PIC16C6x synchronous serial port (SSP) is configured as an SCLK/PD4 SPI master with the clock polarity bit = 1. This is done by writing to MISO/PD2 the synchronous serial port control register (SSPCON) ...

Page 20

... Digital and analog ground planes should be joined in only one place, as close as possible to the GND pin of the AD7887. If the AD7887 system where multiple devices require AGND-to-DGND connections, the connection should still be made at one point only, a star ground point, which should be established as close as possible to the AD7887 ...

Page 21

... AD7887ARM-REEL ±2 AD7887ARM-REEL7 ±2 2 AD7887ARMZ ±2 2 AD7887ARMZ-REEL ±2 2 AD7887ARMZ-REEL7 ±2 AD7887BR ±1 AD7887BR-REEL ±1 AD7887BR-REEL7 ±1 2 AD7887BRZ ±1 AD7887BRZ-REEL 2 ±1 2 AD7887BRZ-REEL7 ±1 3 EVAL-AD7887CB 4 EVAL-CONTROL BRD2 1 Linearity error here refers to integral linearity error Pb-free part, # denotes lead-free product, may be top or bottom marked. ...

Page 22

... AD7887 NOTES Rev Page ...

Page 23

... NOTES Rev Page AD7887 ...

Page 24

... AD7887 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C06191-0-9/06(C) Rev Page ...

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