CS4955-CQ Cirrus Logic, Inc., CS4955-CQ Datasheet
CS4955-CQ
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CS4955-CQ Summary of contents
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... Parallel or high-speed I provided for flexibility in system design. The parallel interface doubles as a general purpose I/O port when the CS4954 mode to help conserve valuable board area. ORDERING INFORMATION CS4954-CQ CS4955-CQ VAA CLK 2 SCL I C Interface SDA 8 ...
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... Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade- marks and service marks can be found at http://www.cirrus.com. 2 CS4954 CS4955 DS278PP4 ...
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... Parallel Interface ................................................................................. 33 8.2. Register Description ............................................................................................... 34 8.2.1. Control Registers ......................................................................................... 34 9. BOARD DESIGN AND LAYOUT CONSIDERATIONS .................................................... 50 9.1. Power and Ground Planes ..................................................................................... 50 9.2. Power Supply Decoupling ...................................................................................... 50 9.3. Digital Interconnect ................................................................................................ 50 9.4. Analog Interconnect ............................................................................................... 50 9.5. Analog Output Protection ....................................................................................... 51 9.6. ESD Protection ....................................................................................................... 51 9.7. External DAC Output Filter ..................................................................................... 51 10. PIN DESCRIPTION ......................................................................................................... 53 11. PACKAGE DRAWING ...................................................................................................... 55 DS278PP4 CS4954 CS4955 3 ...
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... Parallel Host Port Timing: Read-Write/Write-Read Cycle ........................................33 28. 8-bit Parallel Host Port Timing: Address Read Cycle ......................................................33 29. 8-bit Parallel Host Port Timing: Address Write Cycle .......................................................34 30. External Low Pass Filter C 31. Typical Connection Diagram ............................................................................................52 4 should be chosen so that CS4954 CS4955 + C .........................51 2 cable DS278PP4 ...
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... V, all voltages with respect Symbol VAA/VDD (AGND,DGND = 0 V, all voltages with respect to 0 V.) Symbol VAA/VDD (T = 25° C; VAA, VDD = 5 V; GNDA, GNDD = 0 V.) A Symbol VIH VIH VOH VOL VOL CS4954 CS4955 Min Max -0.3 6.0 -10 10 -50 +50 -0.3 VAA + 0.3 -0.3 VDD + 0.3 -55 + 125 ...
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... COUT (Note 1) ODEL (Note 1, 5) TRF VOV (Note 1) UVC VAA, VDD IAA1 Low-Z (Note 6) IAA2 High-Z (Note 7) IAA3 PSRR (Note 1) (Note 1) DNL (Note 1) INL (Note 1) (Note 1) (Note 1) SNR (Note 1) SAT , VREF = 1.232 V. CS4954 CS4955 Min Typ Max IO 32.9 34.7 36.5 IO 8.22 8.68 9.13 IB 32.2 33.9 35.7 IB 8.04 8. ...
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... Clock to Data Set-up Time Clock to Data Hold Time Clock to Data Output Delay CLK T ch V[7:0] HSYNC/VSYNC (Inputs) HSYNC/VSYNC CB/FIELD/INT (Outputs) DS278PP4 T isu Figure 1. Video Pixel Data and Control Port Timing CS4954 CS4955 Symbol Min Typ Max Tch 14.82 18.52 22.58 Tcl 14.82 18.52 22.58 Tisu Tih 0 - ...
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... SCL Low to Data Out Valid SDA SCL sph vdo T T spi si 2 Figure Host Port Timing CS4954 CS4955 Symbol Min Typ Max Fclk 100 1000 Tsph 0.1 Tspl 0.7 Tsh 100 Tssu 100 Tsds 50 Tsr 1 Tsf 0.3 Tss 100 Tbuf ...
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... Write-Read/Read-Write Recovery Time Address from Write Hold Time Reset Timing (Figure 3) Reset Pulse Width RESET* DS278PP4 (Continued) Trd Trpw Tas Trah Trda Trdh Twr Twpw Twds Twdh Trec Twac Tres T res Figure 3. Reset Timing CS4954 CS4955 ...
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... RGB or analog YUV outputs. The CS4954/5 will accept 8-bit YCbCr or 8-bit YUV input data. 10 CS4954 CS4955 The CS4954/5 is completely configured and con- trolled via an 8-bit host interface port compatible serial interface. This host port provides access and control of all CS4954/5 options and fea- tures, such as closed caption insertion, interrupts, etc ...
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... NTSC or PAL. The CS4954/5 generates the color burst frequency based on the DS278PP4 CS4954 CS4955 CLK input (27 MHz). Color burst accuracy and stability are limited by the accuracy of the 27 MHz input. If the frequency varies, then the color burst frequency will also vary accordingly ...
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... R.BT470 specifications also possible to delay the luminance signal, with respect to the chrominance signal CS4954 CS4955 three pixel clocks. This variable delay is useful to offset different propagation delays of the luma baseband and modulated chroma signals. This ad- justable luma delay is available only on the CVBS_1 output ...
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... When enabled, clock run-in, start bit, and data bytes are automati- cally inserted at the appropriate video lines. A con- venient interrupt protocol simplifies the software interface between the host processor and the CS4954/5. CS4954 CS4955 Mode 3 Mode 4 Mode 5 Y CVBS_2 ...
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... All of the control registers are uniquely addressable via the internal address register. The control register bits are initialized during device RESET. 14 CS4954 CS4955 See the Programming section of this data sheet for the individual register bit allocations, bit operation- al descriptions, and initialization states. 4.16. Testability ...
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... CS4954 CS4955 • • • 128 129 • • • 244 245 246 247 • • • 128 129 • • • 264 265 266 ...
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... Digital video input is expected to be delivered to the CS4954/5 V [7:0] pins for 287 lines beginning on active video line 24 and continu- ing through line 310. Field two begins with VSYNC transitioning low after 312.5 lines from the beginning of field one. CS4954 CS4955 DS278PP4 ...
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... VSYNC will transition low at line four to begin field one and will remain low for three lines or 2574 pixel cycles (858 × 3). NTSC interlaced tim- ing is illustrated in Figure 9. In this mode, the CS4954/5 expects digital video input at the V [7:0] CS4954 CS4955 269 ...
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... MHz active CbYCrY data, with start- and end- of-video codes implemented using reserved 00 and FF code sequences within the video feed. As with all modes, V [7:0] are sampled with the rising edge of CLK. The CS4954/5 expects the digital ITU- R.BT656 stream to be error-free. The FIELD out- CS4954 CS4955 270 ...
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... Burst Phase = 225 degrees relative to U Figure 8. PAL Video Interlaced Timing output these timing signals for other purposes. By setting the 656_SYNC_OUT register bit in CONTROL_6 register, HSYNC and VSYNC are output,so that other devices in the system can syn- chronize to these timing signals. CS4954 CS4955 318 ...
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... Analog Field 1 313 Analog Field 2 312 Analog Field 3 313 Analog Field 4 312 Burst Phase = 225 degrees relative to U CS4954 CS4955 ...
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... If the input clock has a tolerance of 200 ppm then the resulting subcarrier will also have a tolerance of 200 ppm. Per the NTSC speci- fication, the final subcarrier tolerance is ±10 Hz CS4954 CS4955 SAV Code 4 Clocks ...
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... F8h F8h F8h E0h E0h E0h 43h 43h 43h CS4954 CS4955 PAL-N PAL- Comb. PAL-M PAL-N (Argent) 41h 61h A1h 30h 12h 30h 07h 07h 07h 78h 78h 78h 15h ...
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... The run-in and start code bits do not have to be loaded into this device, it automatically inserts the correct code at the beginning of transfer. DS278PP4 CS4954 CS4955 5.11. Teletext Support This chip supports several teletext standards, like European teletext, NABTS (North American tele- text), and WST (World Standard Teletext) for NTSC and PAL ...
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... The time t register. CVBS/Y t TTXWin TTXRQ TTXDAT Figure 13. Teletext Timing (Window Mode) CS4954 CS4955 TTX_LINE_DIS2 increases as well. The time dependant on the TTXHD TTXWin TTX textbit #: ...
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... In PAL mode lines and lines 318 -335 are 204 12.0 s used. The VBI encoding mode can be set through 163 10.5 s the CONTROL_3 register. All digital input data is passed through the chip when this mode is enabled therefore the re- sponsibility of the user to ensure appropriate ampli- CS4954 CS4955 ...
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... The GPIO port PDAT [7:0] pins are configured for output GPIO_CTRL_REG [7:0] bits are set. In GPIO out- put mode, the CS4954/5 will output the data in GPIO_DATA_REG [7:0] bit locations onto the corresponding PDAT [7:0] pins when it detects a register address 0×0A through the I CS4954 CS4955 2 C host interface CS4954/5 also contains when ...
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... Figure 15. 1.3 Mhz Chrominance low-pass filter trans- 0 -0.5 -1 -1 Figure 17. 650 kHz Chrominance low-pass filter trans- fer characteristic (passband) CS4954 CS4955 1.3 Mhz. filter passband response frequency (Hz) fer characterstic (passband) 650 Khz. filter passband response ...
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... Figure 19. Luminance interpolation filter transfer char -10 -15 -20 -25 -30 -35 - Figure 21. Chrominance interpolation filter transfer CS4954 CS4955 Luma Output Interpolation Filter Response at 27MHz full scale Frequency (MHz) acteristic RGB datapath filter for rgb_bw = 0 full scale Frequency (MHz) ...
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... Figure 23. Chroma Interpolator for RGB Datapath 0 -5 -10 -15 -20 -25 -30 -35 - Figure 25. Chroma Interpolator for RGB Datapath CS4954 CS4955 RGB datapath filter when rgb_bw = 1 (Reduced Bandwidth Frequency (MHz) when rgb_bw=1 (Reduced Bandwidth) Chroma Output Interpolator Full Scale Frequency (MHz) ...
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... In conjunction with the ISET value, the user can also independently vary the chroma, luma and col- orburst amplitude levels via host addressable con- trol register bits that are used to control internal 30 CS4954 CS4955 digital amplifiers. The DAC output levels are de- fined by the following operations: VREF/RISET = IREF (e.g., 1.232 V/4K ...
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... For load. Reference the a complete disable and lower power operation, the blue DAC can be totally shut down via the B_PD control register bit in Control Register 4 (0×04). In this mode turn-on through the control register will not be instantaneous. CS4954 CS4955 load. load. 31 ...
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... ACK Data ACK 2 C transfers data always with MSB first, LSB last 2 Figure 26 Protocol CS4954 CS4955 Low/High Impedance maximum # of mode active DACs Low Impedance High Impedance Low Impedance High Impedance Table 8. Maximum DAC Numbers Host Control Interface 8-bit parallel operation. The ...
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... Reference the detailed electrical timing parameter section of this data sheet for exact host parallel interface timing characteristics and specifications. T rec rah rpw T T rda T as CS4954 CS4955 T rec rdh 33 ...
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... T wac wds wdh subsequent register description section describe the full register map for the CS4954 only. A complete CS4955 register set description is available only to Macrovision ACP-PPV Licensed Buyers. 8.2.1. Control Registers Register Name control_0 control_1 control_2 control_3 control_4 control_5 control_6 ...
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... CB_AMP CR_AMP Y_AMP R_AMP G_AMP B_AMP BRIGHT_OFFSET TTXHS TTXHD TTXOVS TTXOVE TTXEVS TTXEVE TTX_DIS1 TTX_DIS2 TTX_DIS_3 INT_EN INT_CLR STATUS_0 RESERVED STATUS_1 RESERVED Table 9. Control Registers (Continued) CS4954 CS4955 Type Default value r/w 00h r/w 00h r/w 00h r/w 00h r/w 00h r/w 00h r/w 00h r/w 00h r/w 00h r/w 80h ...
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... PAL-M PAL-N (Argentina) PAL-N (non Argentina) reserved Read/Write LPF_ON delay (default) 1 pixel clock delay 2 pixel clock delay 3 pixel clock delay CS4954 CS4955 Default Value = 01h CCIR656 PROG IN_MODE Function Default Value = 02h RGB_BW FLD ...
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... WST (NTSC FORMAT is NTSC or PAL-M 0: Europe TTX FORMAT is PAL-B, G..., N 1: WST (PAL FORMAT is PAL-B, G, ..., N Enable teletext process (1 = enable) Slave mode 1 pixel sync delay (1 = enable) Crystal oscillator for subcarrier adjustment enable (1 = enable) Chroma burst disable (1 = disable) CS4954 CS4955 TTX EN SYNC_DLY XTAL 0 0 ...
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... DAC 0: power up, 1: power down power down red rgb video DAC 0: power up, 1: power down power down green rgb video DAC 0: power up, 1: power down power down blue rgb video DAC 0: power up, 1: power down CS4954 CS4955 Function ...
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... Read/Write Default Value = 00h COM Function Read/Write Default Value = 00h TTXEN TTXEN TTXEN COM2 COM1 SVID Function CS4954 CS4955 BSYNC DIS GSYNC DIS RSYNC DIS ...
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... Read/Write GPR_CNTRL Read/Write GPIO REG mode. Read/Write PROG VS[4: CS4954 CS4955 Default Value = 03h Function Default Value = 00h Function Default Value = 00h Function 2 C)- This register is only accessible ...
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... Read/Write AMP Read/Write Mnemonic Subcarrier synthesis bits 7 Subcarrier synthesis bits 15 Subcarrier synthesis bits 23: Subcarrier synthesis bits 31: CS4954 CS4955 Default Value = F4h Function Default Value = 00h ADR Function ...
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... Default Value = 00h HUE LSB Read/Write Default Value = 00h RESERVED Read/Write Default Value = 00h Read/Write Default Value = 00h RESERVED CS4954 CS4955 Function MSB Function Function EN_284 Function ...
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... NTSC: don’t care PAL: group 4, bit 13, NTSC: don’t care PAL: group 4, bit 12, NTSC: don’t care PAL: group 4, bit 11, NTSC: bit 20 PAL: group 3, bit 10, NTSC: bit 19 PAL: group 3, bit 9, NTSC: bit 18 PAL: group 3, bit 8, NTSC: bit 17 CS4954 CS4955 Function WSS_18 WSS_17 ...
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... PAL: don’t care, NTSC: bit 5 PAL: don’t care, NTSC: bit 4 PAL: don’t care, NTSC: bit 3 PAL: don’t care, NTSC: bit 2 PAL: don’t care, NTSC: bit 1 Read/Write Default Value = 80h U_AMP CS4954 CS4955 WSS_10 WSS_9 Function WSS_2 ...
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... Function Read/Write Default Value = 80h Y_AMP Function Read/Write Default Value = 80h R_AMP Function Read/Write Default Value = 80h G_AMP Function CS4954 CS4955 ...
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... B_AMP Read/Write BRIGHTNESS_OFFSET Function Read/Write TTXHS Read/Write TTXHD CS4954 CS4955 Default Value = 80h Function Default Value = 00h Default Value = A1h Function Default Value = 02h ...
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... Function Read/Write Default Value = 00h TTXOVE Function Read/Write Default Value = 00h TTXEVS Function Read/Write Default Value = 00h TTXEVE Function CS4954 CS4955 ...
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... LSB is for line 23) 48 Read/Write Default Value = 00h TTX_LINE_DIS1 Read/Write Default Value = 00h TTX_LINE_DIS2 Read/Write Default Value = 00h RESERVED TTX_WINDOW CS4954 CS4955 Function Function TTX_LINE_DIS3 Function ...
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... Field Status bits(001 = field 1,000 = field 8) 2:0 FLD_ST Status Register 1 × Address 0 5A STATUS_1 Bit Number 7 Bit Name Default 0 Bit Mnemonic Device identification: CS4954: 0000 0100, CS4955: 0000 0101 7:0 DEVICE_ID DS278PP4 Read/Write Default Value = 00h RESERVED Read/Write Default Value = 00h ...
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... ESR capac- itor. 50 CS4954 CS4955 Place all decoupling caps as close as possible the the device as possible. Surface mount capacitors generally have lower inductance than radial lead or axial lead components. Surface mount caps should be place on the component side of the PCB to min- imize inductance caused by board vias ...
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... If an output filter is required, the low pass filter shown in Figure 30 can be used. 2 330pF 1 Figure 30. External Low Pass Filter C should be chosen so that CS4954 CS4955 ESD Protection External DAC Output Filter OUT C 2 220pF = cable 51 ...
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... FIELD 12 10 INT HSYNC / RESET VSYNC 37 13 TEST ISET GNDD GNDA Figure 31. Typical Connection Diagram CS4954 CS4955 75 or 300 SCART 300 Connector 75 or 300 CompositeVideo Connector 75 or 300 75 or 300 S-Video Connector 75 or 300 4 k ±1% DS278PP4 ...
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... INT TEST XTAL_OUT XTAL_IN PADR VDD GNDD DS278PP4 CS4954- CS4955- 48-Pin TQFP 7 30 Top View CS4954 CS4955 GNDA ...
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... OUT Teletext request output OUT Interrupt output, active high IN Active low master RESET IN TEST pin. Ground for normal operation 3.3 V supply (must be same as VDD) PS Ground 3.3 V supply (must be same as VAA) PS Ground s Table 10. Device Pin Description CS4954 CS4955 Description DS278PP4 ...
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... Controlling dimension is mm. JEDEC Designation: MS026 DS278PP4 INCHES MIN MAX --- 0.063 0.002 0.006 0.007 0.011 0.343 0.366 0.272 0.280 0.343 0.366 0.272 0.280 0.016 0.024 0.018 0.030 0.000° 7.000° CS4954 CS4955 A A1 MILLIMETERS MIN MAX --- 1.60 0.05 0.15 0.17 0.27 8.70 9.30 6.90 7.10 8.70 9.30 6.90 7.10 0.40 0.60 0.45 0.75 0.00° 7.00° 55 ...
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