CS8900-CQ Cirrus Logic, Inc., CS8900-CQ Datasheet
CS8900-CQ
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CS8900-CQ Summary of contents
Page 1
... Bus A Logic DS271PP4 DESCRIPTION The CS8900A is a low-cost Ethernet LAN Controller op- timized for Industry Standard Architecture (ISA) Personal Computers. Its highly-integrated design elimi- nates the need for costly external components required by other Ethernet controllers. The CS8900A includes on-chip RAM, 10BASE-T transmit and receive filters, and a direct ISA-Bus interface with 24 mA Drivers ...
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... Determining the EEPROM Type ..........................................................20 3.4.3.4 Checking EEPROM for presence of Reset Configuration Block ..........20 3.4.3.5 Determining Number of Bytes in the Reset Configuration Block .........21 3.4.4 TGroups of Configuration Data ............................................................................21 3.4.4.1 Group Header ......................................................................................22 3.4.5 TReset Configuration Block Checksum ...............................................................22 3.4.6 TEEPROM Example ............................................................................................22 3.4.7 TEEPROM Read-out ...........................................................................................22 2 Crystal LAN™ ISA Ethernet Controller .............................................................................................................11 CIRRUS LOGIC PRODUCT DATASHEET CS8900A DS271PP4 ...
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... Programming the EEPROM .............................................................................................23 3.5.1 TEEPROM Commands .......................................................................................23 3.5.2 TEEPROM Command Execution ........................................................................23 3.5.3 TEnabling Access to the EEPROM .....................................................................24 3.5.4 TWriting and Erasing the EEPROM ....................................................................24 3.6 Boot PROM Operation .....................................................................................................24 3.6.1 TAccessing the Boot PROM ................................................................................24 3.6.2 TConfiguring the CS8900A for Boot PROM Operation .......................................24 3.7 Low-Power Modes ..........................................................................................................25 3.7.1 THardware Standby ............................................................................................25 3.7.2 THardware Suspend ...........................................................................................25 3.7.3 TSoftware Suspend .............................................................................................26 3.8 LED Outputs .....................................................................................................................27 3.8.0.1 LANLED ..............................................................................................27 3 ...
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... Memory Mode Operation ..................................................................................................73 4.9.1 TAccesses in Memory Mode ...............................................................................73 4.9.2 TConfiguring the CS8900A for Memory Mode .....................................................73 4.9.3 TBasic Memory Mode Transmit ...........................................................................74 4.9.4 TBasic Memory Mode Receive ............................................................................74 4.9.5 TPolling the CS8900A in Memory Mode ..............................................................75 4.10 I/O Space Operation ......................................................................................................75 4.10.1 TReceive/Transmit Data Ports 0 and 1 ..............................................................75 4 Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET ...
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... TConfiguring the Destination Address Filter ........................................................87 5.3.2 THash Filter .........................................................................................................88 5.3.2.1 Hash Filter Operation ..........................................................................88 5.3.3 TBroadcast Frame Hashing Exception ................................................................88 5.4 Receive DMA ...................................................................................................................89 5.4.1 TOverview ...........................................................................................................89 5.4.2 TConfiguring the CS8900A for DMA Operation ..................................................89 5.4.3 TDMA Receive Buffer Size ..................................................................................89 5.4.4 TReceive-DMA-Only Operation ...........................................................................90 5.4.5 TCommitting Buffer Space to a DMAed Frame ...................................................91 5.4.6 TDMA Buffer Organization ..................................................................................91 5.4.7 TRxDMAFrame Bit ..............................................................................................91 5.4.8 TReceive DMA Example Without Wrap-Around ..................................................91 5 ...
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... TOverview ...........................................................................................................92 5.5.2 TConfiguring the CS8900A for Auto-Switch DMA ...............................................93 5.5.3 TAuto-Switch DMA Operation ..............................................................................93 5.5.4 TDMA Channel Speed vs. Missed Frames ..........................................................94 5.5.5 TExit From DMA ..................................................................................................94 5.5.6 TAuto-Switch DMA Example ...............................................................................95 5.6 StreamTransfer ................................................................................................................95 5.6.1 TOverview ...........................................................................................................95 5.6.2 TConfiguring the CS8900A for StreamTransfer ...................................................95 5.6.3 TStreamTransfer Operation .................................................................................95 5.6.4 TKeeping StreamTransfer Mode Active ...............................................................95 5.6.5 TExample of StreamTransfer ...............................................................................97 5.6.6 TReceive DMA Summary ....................................................................................97 5.7 Transmit Operation ...........................................................................................................98 5 ...
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... The AUI port provides a direct interface to 10BASE-2, 10BASE-5 and 10BASE-FL networks, and is capable of driving a full 50-meter AUI cable. 1.2 System Applications The CS8900A is designed to work well in either motherboard or adapter applications. 1.2.1 Motherboard LANs The CS8900A requires the minimum number of external components needed for a full Ethernet node ...
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... The 10BASE-T transmitter and receiver im- pedance can be adjusted to support 100, 120, or 150 Ohm twisted pair cables. • An external Latchable-Address-bus decode cir- cuit can be added to operate the CS8900A in Upper-Memory space. adapter cards • On-chip LED ports can be used for either op- tional LEDs programmable outputs ...
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... The serial EEPROM port, used for configura- tion and initialization, eliminates the need for expensive switches and jumpers. • The CS8900A is designed to be used layer circuit board instead of a more expensive multilayer board. • The 8900A-based solution offers the smallest footprint available, saving valuable printed cir- cuit board area ...
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... DI- 79 DI+ 39.2 Ω BSTATUS/HCI 680 Ω 100 LANLED 680 Ω 99 LINKLED 17 CSOUT Boot-PROM 27C256 PD[0:7] Figure 3. Typical Connection Diagram CIRRUS LOGIC PRODUCT DATASHEET CS8900A 10 BASE T Isolation Transformer 100 Ω 0.1 µ F ...
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... DVSS1A 10 DMARQ2 11 DMACK2 12 DMARQ1 13 DMACK1 14 DMARQ0 15 DMACK0 16 CSOUT 17 SD15 18 SD14 19 SD13 20 SD12 21 DVDD2 22 DVSS2 23 SD11 24 SD10 25 DS271PP4 CS8900A 100-pin TQFP (Q) Top View CIRRUS LOGIC PRODUCT DATASHEET 75 RESET 74 SD7 73 SD6 72 SD5 71 SD4 70 DVSS4 69 DVDD4 68 SD3 67 SD2 66 SD1 65 SD0 IOCHRDY 64 63 AEN 62 IOW ...
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... I/O register onto the System Data Bus. IOR is ignored if REFRESH is low. IOW - I/O Write, Input PIN 62. When IOW is low and a valid address is detected, the CS8900A writes the data on the System Data Bus into the selected 16-bit I/O register. IOW is ignored if REFRESH is low. ...
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... IOCHRDY - I/O Channel Ready, Open Drain Output PIN 64. When driven low, this open-drain, active-high output extends I/O Read and Memory Read cycles to the CS8900A. This output is functional when the IOCHRDYE bit in the Bus Control register (Register 17) is clear. This pin is always 3-Stated when the IOCHRDYE bit is set. ...
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... Serial output used to send data to the EEPROM. Connects to the DI pin on the EEPROM. When TEST is low, this pin becomes the output for the Boundary Scan Test. CSOUT - Chip Select for External Boot PROM, PIN 17. Active-low output used to select an external Boot PROM when the CS8900A decodes a valid Boot PROM memory address. 10BASE-T Interface TXD+/TXD- - 10BASE-T Transmit, Differential Output Pair PINS 87 and 88 ...
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... When the HCE0 bit of the Self Control register (Register 15) is clear, this active-low output is low when the CS8900A detects the presence of valid link pulses. When the HC0E bit is set, the host may drive this pin low by setting the HCBO in the Self Control register. ...
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... Ethernet frame into the CS8900A’s buffer memory. The first phase be- gins with the host issuing a Transmit Command. This informs the CS8900A that a frame transmitted and tells the chip when to start trans- mission (i.e. after 5, 381, 1021 or all bytes have been transferred) and how the frame should be sent (i ...
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... The CS8900A interfaces directly to the host DMA controller to provide DMA transfers of receive frames from CS8900A memory to host memory. The CS8900A has three pairs of DMA pins that can be connected directly to the three 16-bit DMA channels of the ISA bus. Only one DMA channel is used at a time ...
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... Upon exit, there is a chip-wide reset (see Section 3.7 on page 25 for more information about SW Suspend). 3.3.2 Allowing Time for Reset Operation After a reset, the CS8900A goes through a self con- figuration. This includes calibrating on-chip analog circuitry, and reading EEPROM for validity and configuration. Time required for the reset calibra- tion is typically 10 ms ...
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... EEPROM into its internal registers (see next section). If EEDI is low, an EEPROM is not present and the CS8900A comes out of reset with the default configuration shown in Table 3. A low-cost serial EEPROM can be used to store configuration information that is automatically loaded into the CS8900A after each reset (except EEPROM reset) ...
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... EEPROM words, and a checksum value. All of the words in Pin the Reset Configuration Block are read sequential- Chip Select ly by the CS8900A after each reset, starting with Clock the header and ending with the checksum. Each group of configuration data is used to program a Data In PacketPage register (or set of PacketPage registers in some cases) with an initial non-default value ...
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... FFFFh is a special code indicating that there are no more words in the EEPROM. Table 6. EEPROM Configuration Block Example CS8900A will not attempt to read configuration data from the EEPROM. 3.4.3.5 Determining Number of Bytes in the Reset Configuration Block The low byte of the Reset Configuration Block header is known as the link byte ...
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... EEPROM Read-out If the EEDI pin is asserted high at the end of reset, the CS8900A reads the first word of EEPROM data by: 1) Asserting EECS 2) Clocking out a Read-Register-00h command on EEDO (EESK provides a 1MHz serial clock signal) 3) Clocking the data in on EEDI ...
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... Crystal LAN™ ISA Ethernet Controller ’C46 or ’CS46. If EEDI is high, the EEPROM is a ’C56, ’CS56, ’C66, or ’CS66. 3.4.7.2 Loading Configuration Data The CS8900A reads in the first word from the EE- PROM to determine if configuration data is con- tained in the EEPROM. If configuration data is not stored in the EEPROM, the CS8900A terminates initialization from EEPROM and operates using its default configuration (See Table 3) ...
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... ISA bus. 3.6.2 Configuring the CS8900A for Boot PROM Operation Figure 6 shows how the CS8900A should be con- nected to the Boot PROM and ’245 driver. To con- figure the CS8900A’s internal registers for Boot PROM operation, the Boot PROM Base Address ...
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... LAN is not in use, and then automatically restore Ethernet operation once the cable is reconnected Standby mode, all analog and digital cir- A1 cuitry in the CS8900A is turned off, except for the . ISA . SD(0:7) 10BASE-T receiver which remains active to listen BUS ...
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... SWSuspend bit (Register 15, SelfCTL, bit 8). To exit SW Suspend, the host must write to the CS8900A’s assigned I/O space (the Write is only used to wake the CS8900A, the Write itself is ig- nored). Upon exit, the CS8900A performs a com- plete reset, and then goes through a normal initialization procedure ...
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... Output is low Table 9. LINKLED/HC0 Pin Operation 3.8.0.3 BSTATUS or HC1 BSTATUS or HC1 can be controlled by either the CS8900A or the host. When controlled by the CS8900A, BSTATUS is low whenever the host reads the RxEvent register (PacketPage base + 0124h), signaling the transfer of a receive frame across the ISA bus. To configure this pin for CS8900A control, the HC1E bit (Register 15, Self- CTL, Bit D) must be clear ...
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... Programmable MAC features include automatic retransmission on collision, and padding of transmitted frames. Figure 8 shows how the MAC engine interfaces to other CS8900A functions. On the host side, it inter- faces to the CS8900A’s internal data/address/con- trol bus. On the network side, it interfaces to the internal Manchester encoder/decoder (ENDEC). ...
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... CRC). When Tx- PadDis is set, the CS8900A will not add pad bits and will transmit frames less that 64 bytes frame is received that is less than 64 bytes (includ- ing CRC), the Runt bit (Register 4, RxEvent, Bit D) will be set indicating the arrival of an illegal frame ...
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... If a frame is received with a bad CRC, the CRCer- ror bit (Register 4, RxEvent, Bit C) is set. If the CRCerrorA bit (Register 5, RxCTL, Bit C) is set, the frame will be buffered by CS8900A. If the CRCerroriE bit (Register 3, RxCFG. Bit C) is set, the host is interrupted. 3.9.4.2 Runt Frame If a frame is received that is shorter than 64 bytes, the Runt bit (Register 4, RxEvent, Bit D) is set ...
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... Fig- ure 11 diagrams the simple deferral process. 3.9.5.4 Collision Resolution If a collision is detected while the CS8900A is transmitting, the MAC responds in one of three ways depending on whether normal collision (within the first 512 bits of transmission late collision (after the first 512 bits of transmission): 3 ...
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... MAC immediately terminates transmission, transmits the jam sequence, discards the packet, and sets the Out-of-window bit (Regis- ter 8, TxEvent, Bit 9). The CS8900A does not ini- tiate backoff or attempt to retransmit the frame. For additional information about Late Collisions, see Out-of-Window Error in this section ...
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... CS8900A Crystal LAN™ ISA Ethernet Controller 1.6 µs after the end of transmission. During this pe- riod, the CS8900A ignores receive carrier activity (see SQE Error in this section for more informa- tion). 3.10 Encoder/Decoder (ENDEC) The CS8900A’s integrated encoder/decoder (EN- DEC) circuit is compliant with the relevant por- tions of section 7 of the Ethernet standard (ISO/IEC 8802-3, 1993) ...
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... In Auto-Select mode, the CS8900A automatically selects the 10BASE-T interface and powers down the AUI if valid packets or link pulses are detected by the 10BASE-T receiver. If valid packets and link pulses are not detected, the CS8900A selects 34 Crystal LAN™ ISA Ethernet Controller 10BASE-T Transceiver ...
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... Link- Loss timer is started. As long as a packet or link pulse is received before the Link-Loss timer finish- es (between 25 and 150 ms), the CS8900A main- tains normal operation receive activity is detected, the CS8900A disables packet transmis- sion to prevent "blind" transmissions onto the net- work (link pulses are still sent while packet transmission is disabled) ...
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... PolarityOK bit (Register 14, LineST, bit C) is set. If the polarity is reversed, the PolarityOK bit is clear. If the PolarityDis bit (Reg- ister 13, LineCTL, Bit C) is clear, the CS8900A au- tomatically corrects a reversal. If the PolarityDis bit is set, the CS8900A does not correct a reversal. ...
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... MAC by asserting the internal Collision signal. 3.13 External Clock Oscillator A 20-MHz quartz crystal or CMOS clock input is required by the CS8900A CMOS clock input is used, it should be connected the to XTAL1 pin, with the XTAL2 pin left open. The clock signal should be 20 MHz ±0.01% with a duty cycle be- tween 40% and 60% ...
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... The CS8900A architecture is based on a unique, highly-efficient method of accessing internal regis- ters and buffer memory known as PacketPage. PacketPage provides a unified way of controlling the CS8900A in Memory or I/O space that mini- mizes CPU overhead and simplifies software. It provides a flexible set of performance features and configuration options, allowing designers to devel- op Ethernet circuits that meet their particular sys- tem requirements ...
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... Initiate Transmit Registers Notes: 1. All registers are accessed as words only. 2. Read operation from the reserved location provides undefined data. Writing to a reserved location or undefined bits may result in unpredictable operation of the CS8900A. DS271PP4 4.2 PacketPage Memory Map Table 12 shows the CS8900A PacketPage memory ...
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... Write-only Transmit Frame Location Notes: 1. All registers are accessed as words only. 2. Read operation from the reserved location provides undefined data. Writing to a reserved location or undefined bits may result in unpredictable operation of the CS8900A. Table 12. PacketPage Memory Address Map (continued) 40 Crystal LAN™ ISA Ethernet Controller ...
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... I/O space, which are used to access the PacketPage registers. See Section 4.10 on page 75. The default location is 0300h. After reset EEPROM is found by the CS8900A, then the register has the following initial state EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 18. ...
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... IRQ12 See Section 3.2 on page 17. After reset EEPROM is found by the CS8900A, then the register has the following initial state, which corre- sponds to placing all the INTRQ pins in a high-impedance state EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 18. ...
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... Memory Base Address: The lower three bytes (002Ch, 002Dh, and 002Eh) are used for the 20-bit memory base address. The upper three nibbles are reserved. After reset EEPROM is found by the CS8900A, then the register has the following initial state EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 18. ...
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... Boot PROM base address. The upper three nibbles are reserved. See Section 3.6 on page 24. After reset EEPROM is found by the CS8900A, then the register has the following initial state EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 18. ...
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... CS8900A Crystal LAN™ ISA Ethernet Controller 4.3.11 EEPROM Command (Read/Write, Address: PacketPage base + 0040h Reserved This register is used to control the reading, writing and erasing of the EEPROM. See Section 3.5. ADD7-ADD0 Address of the EEPROM word being accessed. OB1,OB0 Indicates the Opcode of the command being executed. See Table 7. ...
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... Status and Event Registers Status and Event registers report the status of trans- mitted and received frames, as well as information about the configuration of the CS8900A. They are read-only and are designated by even numbers (e.g. Register 2, Register 4, etc.). The Interrupt Status Queue (ISQ special type of Status/Event register ...
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... Provides time domain for locating coax cable faults. Section 4.4.4 on page 48 provides a detailed de- scription of the bits in each register. 4.4.3.1 Act-Once Bits There are four bits that cause the CS8900A to take a certain action only once when set. These "Act- Once" bits are: Skip_1 (Register 3, RxCFG, Bit 6), RESET (Register 15, SelfCTL, Bit 6), ResetRxD- MA (Register 17, BusCTL, Bit 6), and SWint-X (Register B, BufCFG, Bit 6) ...
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... ExtradataiE RuntiE CRCerroriE RxOKiE If one of the above Interrupt Enable bits is set and the corresponding Accept bit is clear, the CS8900A generates an interrupt when the associated receive 48 Crystal LAN™ ISA Ethernet Controller event occurs, but then does not accept the receive frame (the length of the receive frame is set to ze- ro) ...
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... CS8900A Crystal LAN™ ISA Ethernet Controller Control and Configuration Bits Reserved (register contents undefined) Extra RuntiE CRC dataiE erroriE Extra RuntA CRC dataA errorA 16colli E TxPad- Inhibit- Dis CRC RxD- Miss TxCol estiE OvfloiE OvfloiE Reserved (register contents undefined) ...
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... Hashed RxOK Jabber Out-of- TxOK Window Rx128 RxMiss TxUnder- Rdy4Tx RxDMA run 10BT AUI EL EEPRO EEPRO SIBUSY present M OK Mpresent Rdy4Tx NOW CIRRUS LOGIC PRODUCT DATASHEET CS8900A Register Number (Offset) 0 (0120h) 2 Dribble IAHash 4 bits (0124h) Dribble IAHash 4 bits (0124h) 6 SQE ...
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... The Interrupt Status Queue Register is used in both Memory Mode and I/O Mode to provide the host with interrupt information. Whenever an event occurs that triggers an enabled interrupt, the CS8900A sets the appropriate bit(s) in one of five registers, maps the contents of that register to the ISQ register, and drives an IRQ pin high. Three of the registers mapped to ISQ are event registers: RxEvent (Register 4), TxEvent (Register 8), and BufEvent (Register C) ...
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... The operation of this bit is independent of the received packet integrity (good or bad CRC). After reset EEPROM is found by the CS8900A, then the register has the following initial state EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 18. ...
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... CS8900A Crystal LAN™ ISA Ethernet Controller 4.4.7 Register 4: Receiver Event (RxEvent, Read-only, Address: PacketPage base + 0124h Dribblebits IAHash F E Extradata Runt Alternate meaning if bits 8 and 9 are both set (see Section 5.3 on page 86 for exception regarding Broadcast frames Dribblebits IAHash F E Hash Table Index (see Section 5.3 on page 86) RxEvent reports the status of the current received frame ...
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... See Note 5. After reset EEPROM is found by the CS8900A, then the register has the following initial state EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 5.3 on page 86. ...
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... CS8900A stops attempting to transmit that packet. When this bit is set, there is an interrupt upon detecting the 16th collision. After reset EEPROM is found by the CS8900A, then the register has the following initial state EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 18. ...
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... TxCFG, Bit 6) is set, there is an interrupt. SQEerror At the end of a transmission on the AUI, the CS8900A expects to see a collision within 64 bit times. If this does not happen, there is an SQE error and this bit is set. If SQEerroriE (Register 7, TxCFG, Bit 7) is set, there is an interrupt. ...
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... If InhibitCRC is clear, the CS8900A appends the CRC. If InhibitCRC is set, the CS8900A does not append the CRC After reset EEPROM is found by the CS8900A, then the register has the following initial state EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 18. ...
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... BufEvent could be RxDest or Rx128. After 128 bytes are received, the BufEvent changes from RxDest to Rx128. After reset EEPROM is found by the CS8900A, then the register has the following initial state after reset EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 18. ...
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... B, BufCFG, Bit 8) is set, there is an interrupt. (See Section 5.7 on page 98 for a description of the transmit bid process.) TxUnderrun This bit is set if CS8900A runs out of data before it reaches the end of the frame (called a trans- mit underrun). If TxUnderruniE (Register B, BufCFG, Bit 9) is set, there is an interrupt. RxMiss If set, one or more receive frames have been lost due to slow movement of data out of the re- ceive buffers ...
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... RxMISS actually overflows). The RxMISS counter is cleared when read. 010000 These bits provide an internal address used by the CS8900A to identify this as the Receiver Miss Counter. When reading this register, these bits will be 010000, where the LSB corre- sponds to Bit 0. ...
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... TxCOL actually overflows). The TxCOL counter is cleared when read. 010010 These bits provide an internal address used by the CS8900A to identify this as the Transmit Collision Counter. When reading this register, these bits will be 010010, where the LSB corre- sponds to Bit 0. ...
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... After reset EEPROM is found by the CS8900A, then the register has the following initial state EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 18. ...
Page 63
... E CRS LineST reports the status of the Ethernet physical interface. 010100 These bits provide an internal address used by the CS8900A to identify this as the Line Status Register. When reading this register, these bits will be 010100, where the LSB corresponds to Bit 0. LinkOK If set, the 10BASE-T link has not failed. When clear, the link has failed, either because the CS8900A has just come out of reset, or because the receiver has not detected any activity (link pulses or received packets) for at least 50 ms ...
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... HC1 is high. HC1 may drive an LED or a logic gate. When HC1E (Bit D) is clear, this con- trol bit is ignored. After reset EEPROM is found by the CS8900A, then the register has the following initial state EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 18. ...
Page 65
... Status Register. When reading this register, these bits will be 010110, where the LSB corre- sponds to Bit 0. 3,3VActive If the CS8900A is operating on a 3.3V supply, this bit is set. If the CS8900A is operating supply, this bit is clear. INITD If set, the CS8900A initialization, including read-in of the EEPROM, is complete. ...
Page 66
... When cleared, the CS8900A will not generate any interrupts. After reset EEPROM is found by the CS8900A, then the register has the following initial state EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 18. ...
Page 67
... Note that this bit is not set when transmit frames are too short. Rdy4TxNOW Rdy4TxNOW signals the host that the CS8900A is ready to accept a frame from the host for transmission. This bit is similar to Rdy4Tx (Register C, BufEvent, Bit 8) except that there is no interrupt associated with Rdy4TxNOW. The host can poll the CS8900A and check Rdy4TxNOW to determine if the CS8900A is ready for transmit ...
Page 68
... This bit must be set when performing loopback tests on the 10BASE-T port. When clear, the CS8900A is configured for standard half-duplex 10BASE-T operation. At reset EEPROM is found by the CS8900A, then the register has the following initial state EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 18. ...
Page 69
... It counts MHz rate from the beginning of transmission on the AUI to when a col- lision or Loss-of-Carrier error occurs. The TDR counter is cleared when read. 011100 These bits provide an internal address used by the CS8900A to identify this as the Bus Status Register. When reading this register, these bits will be 011100, where the LSB corresponds to Bit 0. ...
Page 70
... When TxPadDis is clear, if the host gives a transmit length less than 60 bytes and InhibitCRC is set, then the CS8900A pads to 60 bytes. If the host gives a transmit length less than 60 bytes and InhibitCRC is clear, then the CS8900A pads to 60 bytes and appends the CRC. ...
Page 71
... The value of this register must be loaded from external storage, for example, from the EEPROM. See Section 3.3 on page 18. If the CS8900A is not able to load the IA from the EEPROM, then after a reset this register is undefined, and the driver must write an address to this register. ...
Page 72
... RxEvent register either directly or through the ISQ register. Reading the RxEvent register sig- nals to the CS8900A that the host is finished with the current frame, and wants to start processing the next frame. In this case, the current frame will no longer be accessible to the host ...
Page 73
... X000h. When the CS8900A comes out of reset, its default configura- tion is I/O Mode. Once Memory Mode is selected, DS271PP4 all of the CS8900A’s registers can be accessed di- rectly. In Memory Mode, the CS8900A supports Standard or Ready Bus cycles without introducing additional wait states ...
Page 74
... If Rdy4TxiE (Register B, BufCFG, Bit 8) is set, the host will be interrupt- ed when Rdy4Tx (Register C, BufEvent, Bit 8) becomes set. 3) Once the CS8900A is ready to accept the frame, the host executes repetitive memory-to- memory move instructions (REP MOVS) to memory base + 0A00h to transfer the entire frame from host memory to CS8900A memory ...
Page 75
... Read/Write 4.10.1 Receive/Transmit Data Ports 0 and 1 These two ports are used when transferring trans- mit data to the CS8900A and receive data from the CS8900A. Port 0 is used for 16-bit operations and Ports 0 and 1 are used for 32-bit operations (lower- order word in Port 0). ...
Page 76
... For an I/O Read or Write operation, the AEN pin must be low, and the 16-bit I/O address on the ISA System Address bus (SA0 - SA15) must match the address space of the CS8900A. For a Read, the IOR pin must be low, and for a Write, the IOW pin must be low. ...
Page 77
... PacketPage Pointer between successive ac- cesses (see Figure 18). 4.10.11 Polling the CS8900A in I/O Mode If interrupts are not used, the host can poll the CS8900A to check if receive frames are present and if memory space is available for transmit. CIRRUS LOGIC PRODUCT DATASHEET 77 ...
Page 78
... Section 4.3 on page 41. An event triggers an interrupt only when the En- ableIRQ bit of the Bus Control register (bit F of register 17) is set. After the CS8900A has generat interrupt, the first read of the ISQ makes the INTRQ output pin go low (inactive). INTRQ re- mains low until the null word (0000h) is read from the ISQ, or for 1 ...
Page 79
... CS8900A Crystal LAN™ ISA Ethernet Controller An enabled interrupt occurs. The selected interrupt request pin is driven high (active) if not already high. The host reads the ISQ. The selected interrupt request pin is driven low. EXIT. Yes Interrupts re-enabled. (Interrupts will be disabled for at least 1 ...
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... Table18. 5.2.2.2 Choosing which Frame Types to Accept The RxCTL register (Register 5) is used to deter- mine which frame types will be accepted by the CS8900A (a receive frame is said to be "accepted" when the frame is buffered, either on chip or in host CIRRUS LOGIC PRODUCT DATASHEET CS8900A ...
Page 81
... CS8900A Crystal LAN™ ISA Ethernet Controller Register 13, LineCTL Bit Bit Name Operation 6 SerRxON When set, reception enabled. 8 AUIonly When set, AUI selected (takes precedence over AutoAUI/10BT). 9 AutoAUI/10BT When set, automatic interface selection enabled. When both bits 8 and 9 are clear, 10BASE-T selected ...
Page 82
... When set, DMA buffer size is 64 Kbytes. When clear, DMA buffer size is 16 Kbytes. Table 22. Receive Frame Pre-Processing 5.2.3 Receive Frame Pre-Processing The CS8900A pre-processes all receive frames us- ing a four step process: 1) Destination Address filtering; 2) Early Interrupt Generation; 3) Acceptance filtering; and, 4) Normal Interrupt Generation. ...
Page 83
... RAM, where it awaits processing by the host. Although this re- ceive frame now occupies on-chip memory, the CS8900A does not commit the memory space to it until one of the following two conditions is true: 1) The entire frame has been received and the host ...
Page 84
... EOF No Received? Yes EOF No Received? Yes Figure 22. Early Interrupt Generation CIRRUS LOGIC PRODUCT DATASHEET CS8900A RxDest cleared and Runt set. If RuntA is set, frame accepted and Host may read frame. RxDest cleared and RxOK or CRCerror set, as appropriate. If RxOKA or CRCerrorA is set, frame accepted and Host may read frame ...
Page 85
... BufEvent reg- ister (Register C), either directly or through the ISQ. When the CS8900A commits buffer space to a par- ticular held receive frame (termed a committed re- ceived frame), no data from subsequent frames can be written to that buffer space until the frame is freed from commitment ...
Page 86
... Ethernet throughput can be achieved by using I/O or memory modes, and by dedicating the CPU to reading this counter, and using the count to read the frame out of the CS8900A at the same time it is being received by the CS8900A from the Ethernet (parallel frame-reception and frame-read-out tasks). ...
Page 87
... Table 25, Broadcast Frames can be ac- cepted as Multicast frames under a very specific set of conditions. 5.3.0.3 Broadcast Frames Frames with DA equal to FFFF FFFF FFFFh are broadcast frames. In addition, the CS8900A can be configured for Promiscuous Mode, in which case it will accept all receive frames, irrespective of DA. IAHashA PromiscuousA MulticastA ...
Page 88
... It may become necessary for the host to change the Destination Address (DA) filter criteria without re- setting the CS8900A. This can be done as follows: 1) Clear SerRxON (Register 13, LineCTL, Bit 6) to prevent any additional receive frames while the filter is being changed. 2) Modify the DA filter bits ( and 6) in the RxCTL register ...
Page 89
... Note: If the RxDMAonly bit and the AutoRxD- MAE bit (Register 3, RxCFG, Bit A) are both set, then RxDMAonly takes precedence, and the CS8900A is in DMA mode for all receive frames. 5.4.3 DMA Receive Buffer Size In receive DMA mode, the CS8900A stores re- ceived frames (along with their status and length circular buffer located in host memory space ...
Page 90
... APPLICATION NOTE result of the PC ar- chitecture, DMA cannot occur across a 128K boundary in memory. Thus, the DMA buffer re- served for the CS8900A must not cross a 128K boundary in host memory if DMA operation is de- sired. Requesting a 64K, rather than a 16K buffer, increases the probability of crossing a 128K bound- ary ...
Page 91
... RxDMAFrame Bit buffer, the The RxDMAFrame bit (Register C, BufEvent, bit 7) is controlled by the CS8900A and is set whenev- er the value in the DMA Frame Count register is non-zero. The host cannot clear RxDMAFrame by reading the BufEvent register (Register C). Table 27 summarizes the criteria used to set and clear RxDMAFrame ...
Page 92
... DMA. The software driver should maintain a pointer (e.g. PDMA_START) that will point to the beginning of a new frame. After the CS8900A is initialized and before any frame is received, pointer PDMA_START points to the beginning of the DMA buffer memory area. The first read of the ...
Page 93
... DMA Figure 25. RxDMA Only Operation 5.5.3 Auto-Switch DMA Operation Whenever a frame begins to be received in Auto- Switch DMA mode, the CS8900A checks to see if there is enough on-chip buffer space to store a max- imum length frame. If there is, the incoming frame is pre-processed and buffered as normal. If there isn’t, the CS8900A’s MAC engine compares the frame’ ...
Page 94
... Frame DMA to transfer partial frames. Also, when a frame Discarded has been committed (see Section 5.2.5 on page 83), the CS8900A will not switch to DMA mode until the committed frame has been transferred com- pletely or skipped. After a complete frame has been moved to host All Frames ...
Page 95
... The host reads a zero value from the DMA Frame Count register (PacketPage base + 0028h). • The CS8900A is not in the process of transfer- ring a frame via DMA. 5.5.6 Auto-Switch DMA Example Figure 27 shows how the CS8900A enters and exits Auto-Switch DMA mode. 5.6 StreamTransfer 5 ...
Page 96
... The host responds to the RxDMAFrame interrupt, and reads the Frame Count register, which is cleared when read. Since there are no receive interrupts pending, the CS8900A exits DMA (assumes Frame 3 is still coming in). Frame 3 is completely buffered in on-chip RAM, and awaits processing by the host. ...
Page 97
... DA of each packet passes the DA filter. If any of these conditions are not met, the CS8900A exits StreamTransfer by generating RxOK and RxDMA interrupts. The CS8900A then returns to either Memory, I/O, or DMA mode, depending on configuration ...
Page 98
... Ethernet frame into the CS8900A’s buffer memory. The first phase be- gins with the host issuing a Transmit Command. This informs the CS8900A that a frame transmitted and tells the chip when (i.e. after 5, 381, or 1021 bytes have been transferred or after the full frame has been transferred to the CS8900A) and how the frame should be sent (i ...
Page 99
... The host must write the frame’s length to the TxLength register (PacketPage base + 0146h). 3) The host must read the BusST register (Regis- ter 18) The information written to the TxCMD register tells the CS8900A how to transmit the next frame. CIRRUS LOGIC PRODUCT DATASHEET Register 9, TxCMD Operation Dis ...
Page 100
... BusST register (Register 18) and checking the Rdy4TxNOW bit (Bit 8) until the bit is set. When the CS8900A is ready to accept the frame, the host transfers the entire frame from host mem- ory to CS8900A memory using “REP” instruction (REP MOVS starting at memory base + 0A00h in memory mode, and REP OUT to Receive/Transmit Data Port (I/O base + 0000h) in I/O mode) ...
Page 101
... Yes CS8900A Commits Buffer Space to Transmit Frame Host Writes Transmit Frame to CS8900A CS8900A Transmits Frame Exit Transmit Process 3) The host reads the BusST register. This read is performed in memory mode by reading Regis- ter 18, at memory base + 0138h. In I/O mode, the host must first set the PacketPage Pointer at ...
Page 102
... CFG, bit 8) is set, the CS8900A generates a corre- sponding interrupt. 5.7.9 Rdy4TxNOW vs. Rdy4Tx The Rdy4TxNOW bit (Register 18, BusST, bit 8) is used to tell the host that the CS8900A is ready to accept a frame for transmission. This bit is used during the Transmit Request process or after the Transmit Request process to signal the host that space has become available when interrupts are not being used (i ...
Page 103
... No Exit WAIT-for-interrupt CS8900A Commits Yes Buffer Space to Transmit Frame Host Writes Transmit Frame to CS8900A CS8900A Transmits Frame Exit Transmit Process Figure 31. Transmit Operation in Interrupt Mode 3) There is a transmit under-run, and the Tx- Underrun bit (Register C, BufEvent, Bit 9) is set. Successful transmission is indicated when the TxOK bit (Register 8, TxEvent, Bit 8) is set ...
Page 104
... Send without pads and without CRC Notes the TxPadDis bit is clear and InhibitCRC is set and the CS8900A is commanded to send a frame of length less than 60 bytes, the CS8900A pads. 9. The CS8900A will not send a frame with TxLength less than 3 bytes. 104 Crystal LAN™ ISA Ethernet Controller this situation is described in the following para- graphs ...
Page 105
... Crystal LAN™ ISA Ethernet Controller 6.0 TEST MODES 6.0.1 Loopback & Collision Diagnostic Tests Internal and external Loopback and Collision tests can be used to verify the CS8900A’s functionality when configured for either 10BASE-T or AUI op- eration. 6.0.2 Internal Tests Internal tests allow the major digital functions to be tested, independent of the analog functions ...
Page 106
... CS8900A enters Boundary Scan test mode and stays in this mode as long as TEST is low; • the CS8900A goes through an internal reset and remains in internal reset as long as TEST is low; • the AEN pin, normally the ISA bus Address Enable, is redefined to become the Boundary Scan shift clock input ...
Page 107
... AEN clock cycles. The first Continuity 97 Cycle can be followed by additional Continuity Cycles by keeping TEST low and continuing to cy- cle AEN. When TEST is driven high, the CS8900A exits Boundary Scan mode and AEN is again used as the ISA-bus Address Enable. Figure 32 shows a complete Boundary Scan Conti- nuity Cycle ...
Page 108
... Crystal LAN™ ISA Ethernet Controller Not in Boundary Scan Test Mode TEST switches low (AEN must be low) ENTER BOUNDARY SCAN: CS8900A resets, all digital output pins and bi-directional pins enter High-Z state, and AEN becomes shift clock AEN switches high AEN switches low ...
Page 109
... CS8900A Crystal LAN™ ISA Ethernet Controller TESTSEL AEN Outputs All outputs tri-state EEDataOut OUTPUTS Hi Z DS271PP4 LINKLED LANLED BSTATUS low low low SLEEP OUTPUT TEST 34 Clocks COMPLETE CONTINUITY CYCLE 85 Clocks Figure 33. Boundary Scan Timing CIRRUS LOGIC PRODUCT DATASHEET RESET ELCS ...
Page 110
... V.) Parameter 5.0V Power Supply CS8900A-CQ & -IQ 3.3V Power Supply CS8900A-CQ3 & -IQ3 Operating Ambient Temperature CS8900A-CQ & -CQ3 Operating Ambient Temperature CS8900A-IQ & -IQ3 7.3 DC CHARACTERISTICS Parameter Crystal (when using external clock - square wave) XTAL1 Input Low Voltage XTAL1 Input High Voltage ...
Page 111
... CS8900A Crystal LAN™ ISA Ethernet Controller DC CHARACTERISTICS Parameter Digital Inputs and Outputs Output Low Voltage Output Low Voltage (all outputs) V Output High Voltage ≤ V Output Leakage Current OUT Input Low Voltage Input High Voltage 0 ≤ ...
Page 112
... Valid Address t IOR1 t IOR4 t t IOR2 t IOR6 t IOR3 Valid Data Figure 34. 16-Bit I/O Read, IOCHRDY not used Valid Address t IOR7 t IOR8 Valid Data t IOR9 Figure 35. 16-Bit I/O Read, with IOCHRDY CIRRUS LOGIC PRODUCT DATASHEET CS8900A = 5 VDD = 3.3V) DD Min Typ Max - - 135 ...
Page 113
... CS8900A Crystal LAN™ ISA Ethernet Controller SWITCHING CHARACTERISTICS Parameter 16-Bit Memory Read, IOCHRDY Not Used SA [19:0], SBHE, CHIPSEL, active to MEMCS16 low Address, SBHE, CHIPSEL active to MEMR active MEMR low to SD valid Address, SBHE, CHIPSEL hold after MEMR inactive MEMR inactive to SD 3-state ...
Page 114
... DMA2 IOR n DMA3 DMA4 Valid Valid Data Data Figure 38. 16-Bit DMA Read Valid Address t IOW1 t IOW7 IOW3 IOW6 IOW2 t IOW4 t IOW5 Valid Data In Figure 39. 16-Bit I/O Write CIRRUS LOGIC PRODUCT DATASHEET CS8900A Min Typ Max 135 - 110 - - 0 ...
Page 115
... CS8900A Crystal LAN™ ISA Ethernet Controller SWITCHING CHARACTERISTICS Parameter 16-Bit Memory Write Address, SBHE, CHIPSEL valid to MEMCS16 low Address, SBHE, CHIPSEL valid to MEMW low MEMW pulse width MEMW low to SD valid SD hold after MEMW high Address hold after MEMW inactive ...
Page 116
... Symbol t TRX1 t TRX2 t TRX3 t TRX4 t TRX5 t LN1 t LN2 t LN3 t LN4 t LN5 t LN6 t TRX4 Figure 42. 10BASE-T Receive t LN2 t LN3 t LN4 Figure 43. 10BASE-T Link Integrity CIRRUS LOGIC PRODUCT DATASHEET CS8900A Min Typ Max - - ±13 ±13.5 - 540 - 270 - 100 200 2 - ...
Page 117
... CS8900A Crystal LAN™ ISA Ethernet Controller SWITCHING CHARACTERISTICS Parameter AUI Transmit DO Pair Rise and Fall Times DO Pair Jitter at Bit Cell Center DO Pair Positive Hold Time at Start of Idle DO Pair Return to ≤ 40 mVp after Last Positive Transition AUI Receive DI Pair Rise and Fall Time ...
Page 118
... Symbol t BPROM1 t BPROM2 t BPROM3 t SKS t CCS t DIS t DIH CSH BPROM1 t BPROM2 Figure 47. External Boot PROM Access t SKS t CSS t DIH t DIS t DH Figure 48. EEPROM CIRRUS LOGIC PRODUCT DATASHEET CS8900A Min Typ Max Unit 100 - - ns 250 - - ns 250 - - ns 500 - ...
Page 119
... If a center tap transformer is used on the RXD+ and RXD- inputs, replace the pair of Rr resistors with a single 2xRr resistor. • The Rt and Rr resistors are ±1% tolerance. The CS8900A supports 100, 120, and 150 Ω unshielded twisted pair cables. The proper values of Rt • and Rr, for a given cable impedance, are shown below: Cable Impedance (Ω) ...
Page 120
... Shunt Capacitance 120 Crystal LAN™ ISA Ethernet Controller 39.2 Ω 39.2 Ω 39.2 Ω 39.2 Ω ( MHz quartz crystal is used, it must meet the Min - -50 - CIRRUS LOGIC PRODUCT DATASHEET CS8900A DB15 +12 V Typ Max Unit 20 - MHz - +50 ...
Page 121
... V.) Parameter 5.0V Power Supply CS8900A-CQ & -IQ 3.3V Power Supply CS8900A-CQ3 & -IQ3 Operating Ambient Temperature CS8900A-CQ & -CQ3 Operating Ambient Temperature CS8900A-IQ & -IQ3 8.3 DC CHARACTERISTICS Parameter Crystal (when using external clock - square wave) XTAL1 Input Low Voltage XTAL1 Input High Voltage ...
Page 122
... V OH B4w, O24ts, O4 ≤ OD24, OD10, B24, O24ts B4w ≤ ISQ V SQL V AOD V AODU V IDLE V AISQ CIRRUS LOGIC PRODUCT DATASHEET CS8900A Min Typ Max Unit - - 0 0 0.4 V 0.425 µ ...
Page 123
... CS8900A Crystal LAN™ ISA Ethernet Controller 8.4 SWITCHING CHARACTERISTICS Parameter 16-Bit I/O Read, IOCHRDY Not Used Address, AEN, SBHE active to IOCS16 low Address, AEN, SBHE active to IOR active IOR low to SD valid Address, AEN, SBHE hold after IOR inactive IOR inactive to active ...
Page 124
... MEMR5 t MEMR6 t MEMR7 t MEMR8 t MEMR9 Valid Address t MEMR1 t MEMR4 t t MEMR6 MEMR2 t t MEMR3 MEMR5 Valid Data Valid Address t MEMR7 t MEMR8 Valid Data t MEMR9 CIRRUS LOGIC PRODUCT DATASHEET CS8900A Min Typ Max Unit - - 135 125 ...
Page 125
... CS8900A Crystal LAN™ ISA Ethernet Controller SWITCHING CHARACTERISTICS Parameter DMA Read DMACKx active to IOR active AEN active to IOR active IOR active to Data Valid IOR inactive to SD 3-state IOR n-1 high to DMARQx inactive DMACKx, AEN hold after IOR high 16-Bit I/O Write Address, AEN, SBHE valid to IOCS16 low ...
Page 126
... MEMW6 t MEMW7 t TTX1 t TTX2 t TTX3 Valid Address t t MEMW1 MEMW6 MEMW2 MEMW7 MEMW3 t MEMW5 t MEMW4 Valid Data In Figure 55. 16-Bit Memory Write t TTX1 Figure 56. 10BASE-T Transmit CIRRUS LOGIC PRODUCT DATASHEET CS8900A Min Typ Max Unit - - 110 - - ...
Page 127
... CS8900A Crystal LAN™ ISA Ethernet Controller SWITCHING CHARACTERISTICS Parameter 10BASE-T Receive Allowable Received Jitter at Bit Cell Center Allowable Received Jitter at Bit Cell Boundary Carrier Sense Assertion Delay Invalid Preamble Bits after Assertion of Carrier Sense Carrier Sense Deassertion Delay 10BASE-T Link Integrity ...
Page 128
... ARX3 t ARX4 t ARX5 t ACL1 t ACL2 t ACL3 t ACL4 t ACL5 ATX2 Figure 59. AUI Transmit ARX2 t ARX4 Figure 60. AUI Receive t ACL1 t t ACL2 ACL2 Figure 61. AUI Collision CIRRUS LOGIC PRODUCT DATASHEET CS8900A Min Typ Max Unit - - 0.5 ns 200 - - 8.0 µ ± 240 - ...
Page 129
... CS8900A Crystal LAN™ ISA Ethernet Controller SWITCHING CHARACTERISTICS Parameter External Boot PROM Access Address active to MEMR MEMR active to CSOUT low MEMR inactive to CSOUT high EEPROM EESK Setup time relative to EECS EECS/ELCS_b Setup time wrt ↑ EESK EEDataOut Setup time wrt ↑ EESK EEDataOut Hold time wrt ↑ ...
Page 130
... If a center tap transformer is used on the RXD+ and RXD- inputs, replace the pair of Rr resistors with a single 2xRr resistor. • The Rt and Rr resistors are ±1% tolerance. The CS8900A supports 100, 120, and 150 Ω unshielded twisted pair cables. The proper values of Rt • and Rr, for a given cable impedance, are shown below: Cable Impedance (Ω) ...
Page 131
... CS8900A Crystal LAN™ ISA Ethernet Controller 8.6 AUI WIRING CS8900A Col 8.7 QUARTZ CRYSTAL REQUIREMENTS following specifications) Parameter Parallel Resonant Frequency Resonant Frequency Error ( pF) L Resonant Frequency Change Over Operating Temperature Crystal Capacitance Motional Crystal Capacitance Series Resistance ...
Page 132
... Crystal LAN™ ISA Ethernet Controller INCHES MIN MAX --- 0.063 0.002 0.006 0.007 0.011 0.618 0.642 15.70 0.547 0.555 13.90 0.618 0.642 15.70 0.547 0.555 13.90 0.016 0.024 0.018 0.030 0.000° 7.000° 0.00° CIRRUS LOGIC PRODUCT DATASHEET CS8900A A A1 MILLIMETERS MIN MAX --- 1.60 0.05 0.15 0.17 0.27 16.30 14.10 16.30 14.10 0.40 0.60 0.45 0.75 7.00° DS271PP4 ...
Page 133
... CS8900A Crystal LAN™ ISA Ethernet Controller 10.0 GLOSSARY OF TERMS 10.1 Acronyms AUI CRC CS CSMA/CD DA EEPROM EOF FCS FDX IA IPG ISA LA LLC MAC MAU MIB RX SA SFD SNMP SOF SQE TDR TX UTP DS271PP4 Attachment Unit Interface Cyclic Redundancy Check Carrier Sense Carrier Sense Multiple Access with Collision Detection ...
Page 134
... Time required for an Ethernet Frame to cross a maximum length Ethernet network. One Slot Time equals 512 bit times. Transmit Collision A transmit collision occurs when the receive inputs, RXD+/RXD- (10BASE-T) or CI+/CI- (AUI) are active while a packet is being transmitted. 134 Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET CS8900A DS271PP4 ...
Page 135
... TxEvent 10.4 Terms Specific to the CS8900A Act-Once bit A control bit that causes the CS8900A to take a certain action once when a logic "1" is written to that bit. To cause the action again, the host must rewrite a "1". Committed Receive Frame A receive frame is said to be "committed" after the frame has been buffered by the CS8900A, and the host has been notified, but the frame has not yet been transferred by the host ...
Page 136
... A feature of the CS8900A used to conserve power. When in Suspend mode, the CS8900A can be awakened only by host command. Transfer The term "transfer" refers to moving frame data across the ISA bus to or from the CS8900A. Transmit Request A Transmit Request is issued by the host to initiate the start of a new packet transmission. A Transmit Request consists of the following three steps in exactly the order shown: 1) The host writes a Transmit Command to the TxCMD register (PacketPage base + 0144h) ...
Page 137
... CS8900A Crystal LAN™ ISA Ethernet Controller 11.0 REVISION HISTORY 12 APR 2001 Page 13 changed to Page 41 Added bit definitions for Revisions C and D Page 56 Page 81 Table 19: Page 86 Table 23: DS271PP4 changed to changed to changed to CIRRUS LOGIC PRODUCT DATASHEET 137 ...
Page 138
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