ML6697CQ Micro Linear, ML6697CQ Datasheet

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ML6697CQ

Manufacturer Part Number
ML6697CQ
Description
100BASE-TX physical layer with MII
Manufacturer
Micro Linear
Datasheet

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GENERAL DESCRIPTION
The ML6697 implements the complete physical layer of
the Fast Ethernet 100BASE-TX standard. The ML6697
offers a single-chip per-port solution for MII-based
repeater applications. The ML6697 interfaces to the
controller through the Media Independent Interface (MII).
The ML6697 functionality includes 4B/5B encoding/
decoding, Stream Cipher scrambling/descrambling,
125MHz clock recovery/generation, receive adaptive
equalization, baseline wander correction, and MLT-3
transmitter.
BLOCK DIAGRAM
18
19
17
10
16
12
14
21
23
1
9
3
4
5
6
7
8
TXD3
TXD0
TXCLKIN
TXD2
TXD1
TXEN
TXER
RXEN
RXCLK
RXD3
RXD2
RXD1
RXD0
RXDV
RXER
TXCLK
CRS
5B/4B DECODER
4B/5B ENCODER
STATE MACHINE
STATE MACHINE
DESCRAMBLER
PCS TRANSMIT
SCRAMBLER
PCS RECEIVE
(PLCC Package)
100BASE-TX Physical Layer with MII
24
MII MANAGEMENT REGISTERS
NRZ TO NRZI ENCODER
NRZI TO NRZ DECODER
25
AND CONTROL LOGIC
CLOCK AND DATA
MLT-3 ENCODER
DESERIALIZER
29
SERIALIZER
RECOVERY
30
FEATURES
CLOCK SYNTHESIZER
31
Single-chip 100BASE-TX physical layer
Compliant to IEEE 802.3u 100BASE-TX standard
Supports MII-based repeater applications
Compliant MII (Media Indendent Interface)
4B/5B encoder/decoder
Stream Cipher scrambler/descrambler
125MHz clock recovery/generation
Baseline wander correction
Adaptive equalization and MLT-3 encoding/decoding
32
33
TWISTED PAIR DRIVER
BLW CORRECTION
MLT-3 DECODER
LOOPBACK MUX
FLP/100BASE-TX
EQUALIZER
ML6697
PRELIMINARY
TPOUTN
LINK100
TPOUTP
CMREF
RGMSET
July 1997
TPINN
TPINP
RTSET
40
45
44
46
36
43
39
37
1

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ML6697CQ Summary of contents

Page 1

GENERAL DESCRIPTION The ML6697 implements the complete physical layer of the Fast Ethernet 100BASE-TX standard. The ML6697 offers a single-chip per-port solution for MII-based repeater applications. The ML6697 interfaces to the controller through the Media Independent Interface (MII). The ML6697 ...

Page 2

ML6697 PIN CONFIGURATION TXER TXCLK RXD3 DGND1 RXD2 DVCC1 RXD1 DGND2 RXD0 RXCLK CRS RXEN DGND3 2 ML6697 52-Pin PLCC (Q52 ...

Page 3

PIN CONFIGURATION (Continued) 64 TXCLK 1 RXD3 2 DGND1A 3 DGND1B 4 RXD2 5 DVCC1A 6 DVCC1B 7 RXD1 8 DGND2A 9 DGND2B 10 RXD0 11 RXCLK 12 CRS 13 RXEN 14 DGND3A 15 DGND3B 16 17 ML6697 64-Pin TQFP ...

Page 4

ML6697 PIN DESCRIPTION (Pin numbers for TQFP package in parentheses) PIN NAME 1 (56) TXCLKIN 2 (58, 57) AGND1 3, 4 (59,60, TXD<3:0> 61,62) 7 (63) TXEN 8 (64) TXER 9 (1) TXCLK 10, 12, (2, 5, RXD<3:0> ...

Page 5

PIN DESCRIPTION (Continued) PIN NAME 25 (21) MDIO 26 (22, 23) DGND4 27 (24, 25) DVCC5 28 (26, 27) DGND5 (28) 29 PHYAD0 (29) 30 PHYAD1 31 (30) PHYAD2 32 (31) PHYAD3 33 (32) PHYAD4 34 (33) AVCC3A 35 (34) ...

Page 6

ML6697 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. V Supply Voltage Range .................. GND –0.3V to ...

Page 7

DC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER POWER SUPPLY CURRENT I Supply Current, Transmitting CC TTL INPUTS (TXD<3:0>, TXCLKIN, MDC, MDIO, TXEN, TXER, RXEN) V Input Low Voltage IL V Input High Voltage IH I Input Low Current IL I Input High ...

Page 8

ML6697 AC ELECTRICAL CHARACTERISTICS Over full range of operating conditions unless otherwise specified (Note 1). SYMBOL PARAMETER TRANSMITTER (Note 3) t TPOUTP-TPOUTN Differential TR/F Rise/Fall Time t TPOUTP-TPOUTN Differential TM Rise/Fall Time Mismatch t TPOUTP-TPOUTN Differential TDC Output Duty Cycle ...

Page 9

AC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER MDC-MDIO (MII Management Interface) t Write Setup Time, MDIO Data SPWS Valid to MDC Rising Edge 1.4V Point t Write Hold Time, MDIO Data SPWH Valid After MDC Rising Edge 1.4V Point t Read Setup ...

Page 10

ML6697 TXCLKIN TXCLK TXD<3:0> TXER TXEN RXCLK RXD<3:0> RXER RXDV MDC MDIO Figure 4. MII Management Interface Write Timing MDC MDIO Figure 5. MII Management Interface Read Timing TPWH TPWL t t TPS TPH Figure 2. MII ...

Page 11

FUNCTIONAL DESCRIPTION TRANSMIT SECTION The transmitter includes everything necessary to accept 4-bit data nibbles clocked in at 25MHz at the MII and output scrambled, 5-bit encoded MLT-3 signals into twisted pair at 100Mbps. The on-chip transmit PLL converts a 25MHz ...

Page 12

ML6697 MII MANAGEMENT INTERFACE REGISTERS TABLE 1: CONTROL REGISTER BIT(s) NAME 0.15 Reset 0.14 Loopback 0.13 Manual Speed Select 0.11 Power down 0.12, Not Used 0.10-0.0 TABLE 2: STATUS REGISTER BIT(s) NAME 1.14 100BASE-TX full duplex 1.13 100BASE-TX half duplex ...

Page 13

AVCC1 TXCLKIN AGND1 TXD3 TXD2 TXD1 TXD0 TXEN Figure 6. Applications Circuit ML6697 PHYAD4 PHYAD3 PHYAD2 PHYAD1 PHYAD0 DGND5 DVCC5 DGND4 MDIO MDC RXER DVCC2 RXDV INTERFACE MII 13 ...

Page 14

ML6697 ML6697 SCHEMATIC Figure 6 shows a general ML6697 design. The inductors L1 and L2 are for the purpose of improving return loss. Capacitor C7 is recommended. It decouples some noise at the inputs of the ML6697, and improves the ...

Page 15

PHYSICAL DIMENSIONS 0.785 - 0.795 (19.94 - 20.19) 0.750 - 0.754 (19.05 - 19.15) 1 PIN 1 ID 0.042 - 0.048 (1.07 - 1.22 0.050 BSC (1.27 BSC) 0.026 - 0.032 (0.66 - 0.81) 0.013 - 0.021 (0.33 ...

Page 16

... BSC (0.50 BSC) ORDERING INFORMATION PART NUMBER ML6697CQ ML6697CH Micro Linear makes no representations or warranties with respect to the accuracy, utility, or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, express or implied, by estoppel or otherwise, to any patents or other intellectual property rights is granted by this document ...

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