PM7328-BI PMC-Sierra Inc, PM7328-BI Datasheet
PM7328-BI
Specifications of PM7328-BI
Related parts for PM7328-BI
PM7328-BI Summary of contents
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... STANDARD PRODUCT DATASHEET PMC-2010142 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 2 PM7328 DATASHEET RELEASED ISSUE 2: JUNE 2001 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... EGRESS CONNECTION IDENTIFICATION .................... 73 8.6 EGRESS CELL PROCESSING .................................................. 75 8.7 PERFORMANCE MONITORING ................................................ 84 8.7.1 PERFORMANCE MONITORING FLOWS........................ 96 8.8 CHANGE OF CONNECTION STATE ......................................... 99 8.9 HEADER TRANSLATION ......................................................... 100 8.10 CELL ROUTING........................................................................ 102 8.11 CELL RATE POLICING............................................................. 102 8.11.1 PER-PHY POLICING...................................................... 109 8.11.2 GUARANTEED FRAME RATE....................................... 113 PROPRIETARY AND CONFIDENTIAL ISSUE 2 i PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... NORMAL MODE REGISTER DESCRIPTION .......................... 167 10 TEST FEATURES DESCRIPTION ...................................................... 436 10.1 TEST MODE 0 DETAILS .......................................................... 439 10.2 JTAG TEST PORT .................................................................... 439 11 OPERATION........................................................................................ 446 11.1 SCI-PHY EXTENDED CELL FORMAT ..................................... 446 11.2 SYNCHRONOUS STATIC RAMS ............................................. 448 11.2.1 INGRESS VC-TABLE SRAM.......................................... 448 PROPRIETARY AND CONFIDENTIAL ISSUE 2 ii PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... INGRESS OUTPUT CELL INTERFACE ................................... 471 12.3 EGRESS INPUT CELL INTERFACE ........................................ 473 12.4 EGRESS OUTPUT CELL INTERFACE .................................... 476 13 ABSOLUTE MAXIMUM RATINGS....................................................... 479 14 D.C. CHARACTERISTICS ................................................................... 480 15 A.C. TIMING CHARACTERISTICS...................................................... 482 16 MECHANICAL INFORMATION ........................................................... 497 PROPRIETARY AND CONFIDENTIAL ISSUE 2 DEACTIVATION ............................................................. 459 DEACTIVATION ............................................................. 461 iii PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... EGRESS VPC END-TO-END AND SEGMENT SOURCE POINT WITH VCC SEGMENT END-POINT AND VCC SEGMENT SOURCE POINT........................................................ 143 INTERMEDIATE POINT. EGRESS VPC END-TO-END AND SEGMENT SOURCE POINT WITH VC INTERMEDIATE POINT AND VC SEGMENT SOURCE POINT. ............................ 143 SINGLE VC RECORD. ................................................................. 456 iv PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... FIGURE 55 ...... INGRESS SRAM INTERFACE TIMING ........................................................... 492 FIGURE 56 ...... EGRESS SRAM INTERFACE TIMING ............................................................ 493 FIGURE 57 ...... JTAG PORT INTERFACE TIMING .................................................................. 494 FIGURE 58 ...... ATLAS-1K800 THETA JA VS. AIR FLOW GRAPH ......................................... 496 FIGURE 59 ...... 432 PIN SBGA – BODY -(B SUFFIX) .......................................... 497 PROPRIETARY AND CONFIDENTIAL ISSUE 2 v PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... TABLE 37 ........ D.C. CHARACTERISTICS ............................................................................... 480 TABLE 38 ........ MICROPROCESSOR INTERFACE READ ACCESS ...................................... 482 TABLE 39 ........ MICROPROCESSOR INTERFACE WRITE ACCESS .................................... 484 TABLE 40 ........ JTAG PORT INTERFACE................................................................................ 493 TABLE 41 ........ ORDERING INFORMATION............................................................................ 495 TABLE 42 ........ THERMAL INFORMATION .............................................................................. 495 PROPRIETARY AND CONFIDENTIAL ISSUE 2 PHYVCCOUNT=0......................................................................... 112 PHYVCCOUNT=1......................................................................... 113 vi PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... PHYID/VPI/VCI address range, programmable dual leaky bucket UPC/NPC, per-connection CLP0 and CLP1 cell counts (programmable), OAM-PM termination, generation and monitoring, and OAM-FM termination, generation and alarm generation (monitoring). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 6 cells/s (one STS-12c or four STS-3c). 1 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... Forward Monitoring and Backward Reporting cells. The following statistics are collected when terminating or monitoring PM flows: 1. Forward Impaired Block. 2. Forward Lost/Misinserted Impaired Block 3. Forward Severely Errored Cell Block (Lost). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 2 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... Backward Lost CLP0+1 cell count. 23. Backward Lost CLP0 cell count. 24. Backward Tagged CLP0 cell count. 25. Backward Misinserted CLP0+1 cell count. 26. Backward Errored cell count. 27. Backward Total Lost CLP0+1 cell count. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 3 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... Provides a generic 16 bit microprocessor bus interface for configuration, control and status monitoring. • Low power 0.35 micron, 3.3 V CMOS technology with a 3.3 V UTOPIA (SCI- PHY), 3.3/5 V Microprocessor I/O interfaces and 3.3 V external synchronous SRAM interfaces. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 4 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... CLP1 cells received. • number of OAM cells received. • number of RM cells received. • number of errored OAM cells. • number of errored RM cells. • number of cells with unassigned/invalid VPI/VCI/PTI. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 5 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... STANDARD PRODUCT DATASHEET PMC-2010142 • number of cells received with a non-zero GFC (ingress UNI only). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 6 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 AnyPhy/ SciPhy S/UNI- VORTEX S/UNI- APEX- 1K800 Context LVDS links to SSRAM S/UNI-Duplex devices Packet/Cell per S/UNI-VORTEX SDRAM 7 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION S/UNI- Phy ATLAS- 1K800 Ingress Host SSRAM CPU Egress SSRAM core card ...
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... STANDARD PRODUCT DATASHEET PMC-2010142 The FPGA performs the task of converting the Utopia to signals compatible with the APEX-1K800 and ATLAS-1K800. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 8 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... May 21, 1990. • PMC-940212, ATM SCI-PHY, “SATURN Compliant Interface for ATM Devices”, July 1994, Issue 2. • ATMF TM4.0 – ATM Forum Traffic Management Specification Version 4.0, af- tm-0056.000, April, 1996. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 9 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 (Slave) (Slave) Interface Level1 SCI-PHY Interface Level1/Level2 SCI-PHY (Master) (Master) Level1/Level2 SCI-PHY Interface Level1/Level2 SCI-PHY 10 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION trstb tms tck tdi tdo esoeb esrwb esadsb [9:0] esa[19:16] esp[3:0] esd[31:0] esysclk halfsecclk busyb edreq ...
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... PHY device) directions. The S/UNI-ATLAS- 1K800 uses external synchronous flow-through SRAM to store the per- connection data structures. The device is capable of supporting up to 1024 connections. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 11 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... The S/UNI-ATLAS-1K800 is packaged in a 432 thermally enhanced BGA -SBGA package having a body size 1.54 mm and a ball pitch of 1.27 mm. This pin diagram can be downloaded from the PMC-Sierra website (http://www.pmc-sierra.com PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 12 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... PHY devices are used, the RAVALID pin need not be connected. Note: In direct addressing mode, the 4-PHY configuration is not recommended. Instead the 4- PHY address-polling mode should be used. This does not apply to the Single or Dual-PHY configurations. RPOLL is assumed static input. 13 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... ATLAS-1K800 will complete the read of an entire cell even if the associated RCA[4:1] input is deasserted during the cell transfer. Sampling of the RCA[4:1] inputs resumes the cycle after the last octet of a cell has been transferred. Note, RCA[ input only. 14 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... When all of the enables are deasserted, no valid data is expected. The RRDENB[4:1] outputs are updated on the rising edge of RFCLK. If the RPOLL pin is high, the RRDENB[4:2] pins are redefined as RADDR[2:0]. The RRDENB[1] pin is used to transfer all cells. The source PHY is selected by the RADDR[4:0] signals. 15 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... RADDR[4:0] bus is asserting a valid PHY address for polling purposes. When this signal is deasserted, the RADDR[4:0] bus is set to 0x1F. RAVALID is not necessary when less than 32 PHY devices are being polled. RAVALID is updated on the rising edge of RFCLK. 16 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... RPRTY signal indicates parity over the RDAT[7:0] data bus. A maskable interrupt status is generated upon a parity error; no other actions are taken. The RPRTY signal is sampled on the rising edge of RFCLK and is considered valid only when one of the RRDENB[4:1] signals so indicates. 17 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... ISD[63:0] pins upon the rising edge of AJ6 ISYSCLK which is written into the SRAM on the next AK6 ISYSCLK rising edge. ISD[63:0] is tristated on the rising edge of ISYSCLK. Contention is avoided by not AL6 performing a write during the cycle after a read burst. AJ7 AH8 18 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... ISD[40] ISD[39] ISD[38] ISD[37] ISD[36] ISD[35] ISD[34] ISD[33] ISD[32] PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 Pin No. Function AK7 Continued AL7 AJ8 AH9 AK8 AL8 AJ9 AK9 AL9 AJ10 AH11 AK10 AL10 AJ11 AH12 AK11 AL11 AJ12 19 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... ISD[26] ISD[25] ISD[24] ISD[23] ISD[22] ISD[21] ISD[20] ISD[19] ISD[18] ISD[17] ISD[16] PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 Pin No. Function AH13 Continued AK12 AL12 AJ13 AK13 AL13 AJ14 AK14 AH15 AJ15 AL16 AK16 AJ16 AH16 AL17 AK17 20 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... ISD[10] ISD[9] ISD[8] ISD[7] ISD[6] ISD[5] ISD[4] ISD[3] ISD[2] ISD[1] ISD[0] PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 Pin No. Function AJ17 Continued AK18 AH17 AJ18 AL19 AK19 AJ19 AL20 AK20 AH19 AJ20 AL21 AK21 AH20 AJ21 AL22 21 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... SRAM, the ATLAS- 1K800 generates correct parity. When data are being read from the SRAM, the ATLAS-1K800 asserts a maskable interrupt indication upon parity error detection. No other action is taken, therefore, the ISP[7:0] may be unconnected if parity protection is not required. 22 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... ISRWB is updated on the rising edge of ISYSCLK. AK23 The Ingress VC Table SRAM Address Strobe (ISADSB) qualifies the address bus. If the ISADSB output is asserted low, an SRAM access is initiated. ISADSB is updated on the rising edge of ISYSCLK. 23 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... FIFO, and output on bus ODAT[15:0]. When ORDENB is sampled high, no read is performed and outputs ODAT[15:0], OPRTY and OSOC are tristated if the OTSEN input is high. ORDENB must operate in conjunction with OFCLK to access the FIFO at a high enough rate to avoid a FIFO overflow. 24 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... ODAT[7:0] data bus. OPRTY is updated on the rising edge of OFCLK. When the Ingress Output Cell Interface is configured for tristate operation using the OTSEN input, tristating of the OPRTY output signal is controlled by the ORDENB input. 25 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... S/UNI-ATLAS-1K800 Egress Input Cell Interface. IFCLK must cycle MHz or lower instantaneous rate. ISOC, IPRTY, IDAT[15:0] and IWRENB[4:1] are sampled on the rising edge of IFCLK. IADDR[4:0], IAVALID and ICA[4:1] are updated on the rising edge of IFCLK. 26 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... ICA[4:1] signal indicating the availability AA31 of space in the Egress Input Cell Interface per-PHY 4 cell FIFO of the ATLAS-1K800. The Egress Input Cell Interface of the ATLAS-1K800 must be programmed to emulate the number of PHY devices to which the ATLAS-1K800 is connected. Note, ICA[ output only. 27 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... If more than one enable is asserted simultaneously, a maskable interrupt is asserted, and the cell transfer is ignored. If the IPOLL pin is high, the IWRENB[4:2] pins are redefined as IADDR[2:0]. The IWRENB[1] pin is used to transfer all cells. The destination PHY is selected by the IADDR[4:0] signals. 28 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... When this signal is deasserted, the IADDR[4:0] bus must be set to 0x1F. If fewer than 32 PHY devices are being polled and the IAVALID pin is not functionally used, then IAVALID must be tied high. IAVALID is sampled on the rising edge of IFCLK. 29 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... IDAT[7:0] data bus. A maskable interrupt status is generated upon a parity error; no other actions are taken. The IPRTY signal is sampled on the rising edge of IFCLK and is considered valid only when one of the IWRENB[4:1] signals so indicates. 28 pins 30 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... The Egress Output Cell Interface start of cell (TSOC) indication signal marks the start of cell on the TDAT[15:0] data bus. When TSOC is high, the first word of the cell structure is present on the TDAT[15:0] bus. TSOC is updated on the rising edge of TFCLK. 31 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... PHY devices need not support the cell availability indication during cell transfer. The selection of a particular PHY device to which a cell will be written is indicated by the state of TADDR[4:0] and when TWRENB[1] is asserted. Note, TCA[ input only. 32 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... TAVALID is logic 0. When this occurs, no PHY device should drive TCA[1] during the following clock cycle. Polling is performed in incrementing sequential order. The PHY device selected for transfer is based on the TADDR[4:0] value present when TWRENB[1] falls. The TADDR[4:0] bus is updated on the rising edge of TFCLK. 33 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... PHY devices. The TDAT[15:0] bus is G2 updated on the rising edge of TFCLK and considered valid only when one of the TWRENB[4:1] signals so G1 indicates. TDAT[15:8] is only valid if the TBUS8 H3 register bit is low PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... ESADSB, ESOEB and ESRWB are updated on the rising edge of ESYSCLK. When ESD[31:0] and ESP[3:0] are outputs, they are updated on the rising edge of ESYSCLK. When ESD[31:0] and ESP[3:0] are inputs, they are sampled on the rising edge of ESYSCLK. 35 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... ESD[31:0] pins upon the rising edge of D16 ESYSCLK which is written into the SRAM on the next A15 ESYSCLK rising edge. ESD[31:0] is tristated on the B15 rising edge of ESYSCLK. Contention is avoided by not performing a write during the cycle after a read C15 burst. B14 D15 C14 36 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... SRAM, the ATLAS- 1K800 generates correct parity. When data are being read from the SRAM, the ATLAS-1K800 asserts a maskable interrupt indication upon parity error detection. No other action is taken, therefore, the ESP[3:0] may be unconnected if parity protection is not required. 37 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... ESRWB is updated on the rising edge of ESYSCLK. B8 The Egress VC Table SRAM Address Strobe (ESADSB) qualifies the address bus. If the ESADSB output is asserted low, the external SRAM samples the address asserted by the S/UNI-ATLAS-1K800. ESADSB is updated on the rising edge of ESYSCLK 38 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... DMAEN register bit in the Ingress MCIF Configuration register is a logic 1. The first read of the Ingress MCIF Data register will return the first word of the cell. IDREQ is deasserted after the last word of the cell has been read or an abort has been signaled. 39 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... ESTANDBY bits in the Master Configuration are set to logic 1, the access time is reduced to less than 5 ISYSCLK or ESYSCLK cycles. The polarity of the BUSYB output is programmable and defaults to active low. The BUSYB signal should be treated as a glitch-free asynchronous output. 40 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... TRS selects between normal and test mode register accesses. TRS is high during test mode register C22 accesses, and is low during normal mode register D21 accesses. B22 A[11: tolerant input bus. A22 C21 D20 B21 A21 C20 41 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... When RSTB is forced low, all ATLAS-1K800 registers are forced to their default states. RSTB tolerant input. L30 The test clock (TCK) signal provides timing for test operations that can be carried out using the IEEE P1149.1 test access port. TCK tolerant input. 42 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... TRSTB tolerant input. B25 +5V Bias (VBIAS). The VBIAS input is used to implement the 5V tolerance on the inputs of the Microprocessor and JTAG interfaces Interface volt tolerance is not required, VBIAS should be connected to the 3.3 volt power supply (i.e. the same as VDD). 43 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... PMC-2010142 Pin Name Type VDD Power PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 Pin No. Function A1 The VDD power pins should be connected to a well- decoupled +3.3V DC supply. A31 B2 B30 C3 C29 D4 D7 D10 D14 D18 D22 D25 D28 G4 G28 K4 K28 44 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... DATASHEET PMC-2010142 Pin Name Type VDD Power PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 Pin No. Function P4 Continued P28 V4 V28 AB4 AE4 AB28 AE28 AH4 AH7 AH10 AH14 AH18 AH22 AH25 AH28 AJ3 AJ29 AK2 AK30 AL1 AL31 45 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... PMC-2010142 Pin Name Type GND Ground A2 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 Pin No. Function The ground pins should be connected to GND. A3 A14 A17 A18 A29 A30 B1 B3 B17 B29 B31 C28 C30 C31 D3 D29 P1 P31 R1 46 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... TTL logic levels. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 Pin No. Function Continued. U30 U31 V1 V31 AH3 AH29 AJ1 AJ2 AJ4 AJ30 AJ28 AJ31 AK1 AK3 AK15 AK29 AK31 AL2 AL3 AL14 AL15 AL18 AL29 AL30 47 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... The VDD power must be applied before input pins are driven or the input current per pin be limited to less than the maximum DC input current specification. (20 mA) 3.3 Power down the device in the reverse sequence. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 48 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... PMC-2010142 8 FUNCTIONAL DESCRIPTION The PM7328 ATM Layer Solution (S/UNI-ATLAS-1K800 or abbreviated as ATLAS- 1K800 monolithic integrated circuit that implements the ATM Layer functions that include fault and performance monitoring, header translation and cell rate policing. The S/UNI-ATLAS-1K800 is a bi-directional part which is intended to be situated between the physical layer (PHY) devices and a switch core in the ingress side, and a traffic shaper and the PHY devices in the egress side ...
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... The Ingress Output Cell Interface can be connected to the switch core through a single PHY extended cell format SCI-PHY compatible bus interface. Cells are stored in a four cell deep FIFO until the downstream devices are ready to accept them. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 50 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... All SCI-PHY interfaces are 3.3 Volt only, the SRAM interfaces are 3.3 Volt only, and the Microprocessor Interface and JTAG pins are 3.3V/5V tolerant. The S/UNI-ATLAS-1K800 is packaged in a 432-pin Super BGA package. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 51 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... The Ingress VC Table is a total of 960 bits per connection, however, not all rows need be used if features are disabled. Unused bits should be set to zero for backward compatibility with future devices within the ATLAS-1K800 family. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 52 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... Action I2 2 (2) 1 (2) (14) Violate GFR Non- (1) State Compliant3 (3) (16) Header (40) PrePo5 PrePo6 PrePo7 (8) (8) (8) Unused (5) 53 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION Right Leaf Right Primary Table (1) Branch (16) Record (16 NNI Field Addr (1) B (11) 1 (1) 1(7) OAM VPC Pointer (16) (9) TAT1 (30) L2 ...
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... START A VC Search Key PHY Prim ay Key PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 Cell Postpend Field B START START START B Length <= 128 Field PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION Cell Header HEC/UDF VPI/VCI 47(NNI 43(UNI) Field B VPI/VCI Secondary Key ...
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... Field bits long and may start anywhere in the Routing Word. Field B parameters include starting position, STARTB and length, L the 28-bit VPI/VCI. This field is always taken from the cell header. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 . The number of bits in Field A plus the A 55 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION . The second field is B ...
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... Primary Search Key. Field B and the VPI/VCI field are concatenated to form the Secondary Search Key. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 Field 0-10 bits <= 10 bits Field 0-11 bits <= 26 bits 56 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION VPI/VCI 16 LSB bits ...
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... The general expression for guaranteed throughput is given below: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 Field B Size & Location Field A Size & Location Field A Prim ary Search Key 57 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION VPI/VCI Secondary Search Key n memory locations, 6 cells/s is ...
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... The Secondary Search Key entry is located at locations with ISA[19:16]=0001 and its size is bounded by the number of virtual connections supported. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE max. binary tre e depth ISYSCLK 1 ( cell word length)(IS YSCLK 58 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION cells/s ) period cells/s period) (LP + LA) words of memory. ...
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... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 Ingress Ingress VC VC Table Table Entry Entry Ingress Ingre Table T able Entry Entry Ingress VC Table Entry 59 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION Ingress Ingress Ingress Ingress Table Table T able Table Entry Entry Entry Entry 0 ...
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... Leaf flags must be a logic 1. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 Left Left Branch Right Leaf (10 LSB of 16 Leaf (1) bit field used)) (1) 60 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION Right Branch Primary Search (10 LSB of 16 Key (10 LSB of bit field used)) 16 bit field used) ...
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... When a new VC is provisioned, the management software must initialize the contents of the VC Table record. Once provisioned, the management software can retrieve the contents of the VC Table record. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION = 0), the root of the single A ...
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... The Excessive Policing bit is a logic 1 if any of the per-VC non-compliant cell counts on this connection is greater than 32767 (i.e. the MSB on one or more of the non-compliant cell counts is set to logic 1). This bit indicates that the non- compliant cell counts should be read and cleared to avoid counter saturation. 62 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... If this bit is a logic 0, the Cell Count 1[31:0] and Cell Count 2[31:0] are programmed from the settings in the Ingress Cell Counting Configuration 1 register 0x236. If this bit is a logic 1, the cell counts are derived from the settings in Ingress Cell Counting Configuration 2 register 0x237. 63 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
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... XPOLI interrupt whenever any of the per-VC non- compliant cell counts on this connection becomes greater than 32767 (i.e. the MSB of one or more of the non-compliant cell counts first set). If this bit is a logic 0, the XPOLI interrupt will not be asserted. 64 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 72
... If this bit is a logic 1, an end-to-end AIS cell is generated once per second (nominally). If this bit is a logic 1, a segment RDI cell is generated once per second (nominally). If this bit is a logic 1, an end-to-end RDI cell is generated once per second (nominally). 65 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 73
... The end-to-end CC cell is generated at an interval of one per second (nominally). If the ForceCC register bit is logic 1, then when the CC_Activate_End_to_End bit is logic 1, an end-to-end CC cell will be generated at an interval of once per second (nominally), regardless of the flow of user cells. ITU-T I.610 9.2.1.1.2, 9.2.2.1.2. 66 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 74
... S/UNI-ATLAS-1K800 writes back a zero at a one second boundary and subsequently reads a zero at the next one second boundary, indicating that no user cells have been sent on this connection), then an End-to-End CC cell is generated, if the 67 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 75
... AIS_end_to_end Alarm is cleared. Description If this bit is logic 1, the Fault Management scenarios listed in Table Fault Management Processing are enabled. If this bit is logic Fault Management cells will be generated as a result of the reception of F4 Fault Management cells. 68 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 76
... Ingress VC table bits or the per-phy RDI register bits, 0x224 and 0x225) or generated by the CC_RDI process, either the local Defect Type field programmed in the Ingress Defect Type registers, 0x226-0x22D unused value (0x6A) will be used. 69 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 77
... Description Indicates the PM session pointed Addr2[6:0] is active. Indicates the PM session pointed Addr1[6:0] is active. Indicates which internal PM RAM Address used for a PM session. Indicates which internal PM RAM Address used for a PM session. 70 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 78
... Alternate Egress Cell Count 1 (32) Alternate Egress Cell Count 2 (32) Received End-to-End AIS Defect Location [95:64] Received End-to-End AIS Defect Location [63:32] Received Segment AIS Defect Location [95:64] Received Segment AIS Defect Location [63:32] 71 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION VPI VCI (12) (16) PM Addr2 ...
Page 79
... If header translation is enabled, all F5 cells received from the Egress Input Cell Interface will have the VCI portion of their header replaced with this VCI field. If the connection connection, the VCI portion of the cell header is passed transparently. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 72 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 80
... The Egress Lookup Address is LSB justified, and the unused MSBs are set to zero. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 Cell Postpend Length <= 128 START A START B START 0<= LengthB <= 10 Length = 10 73 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION Cell Header VPI/VCI HEC/UDF ART 0<= LengthA <= 10 ...
Page 81
... Egress VC Table pointer can be extracted in exactly the same manner as cells received from the Egress Input Cell Interface (this assumes that a direct lookup of the cells is normally performed by extracting a pointer from those same fields). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 74 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 82
... After a direct lookup has been completed for a cell, the resulting actions are dependent upon the cell contents and the Egress VC Table record. Particular features such as cell counting and OAM Processing can be disabled on a global and per-connection basis. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 75 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 83
... Reserved This bit should be set to zero at connection setup. 5 AIS_end_to This bit becomes a logic 1 upon receipt of a single end-to-end AIS cell. The alarm status is cleared upon the receipt of a PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 76 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 84
... This bit becomes a logic user or segment CC, or end- nt alarm to-end CC cell has been received within the last 3.5 +/- 0.5 sec. This bit is cleared upon receipt of a user cell, segment CC cell or end-to-end CC cell PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 77 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 85
... Microprocessor Cell Interface only (not to the Egress Output Cell Interface). The setting of this bit supercedes all other routing bits. If the Drop_UP bit is set, the ATLAS-1K800 will not output generated OAM cells (Fwd PM, Bwd PM and Fault PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 78 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 86
... If both the segment and end-to-end CC alarms are asserted, then both types of RDI cells will be generated (if the ATLAS-1K800 is configured as both a segment end point and an end-to-end point). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 79 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 87
... PTI = 101 are terminated and processed. An End-to-End termination point will also terminate all Segment connections, since by definition the End-to-End point is the end point for all OAM traffic. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 80 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 88
... Seg_RDI_C The Seg_RDI_count is set to a value of 3 (to provide a 2.5 +/- ount[1:0] 0.5 sec count) upon receipt of a segment RDI cell, and decrements at one second intervals. If the Seg_RDI_Count reaches 0, the RDI_segment Alarm is cleared. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 81 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 89
... If this bit is a logic 1, any change of alarm state on this connection will result in a write to the Change of State FIFO (if enabled via the COS register bit of the Egress Cell Processor Configuration register 0x280). If this bit is a logic 0, no writes will be made to the COS FIFO. 82 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 90
... Egress VC table bits or the Per-PHY RDI Cell generation registers 0x28C-0x28D) or generated by the CC_RDI process, either the local Defect Location field programmed in the Egress Cell Processor OAM Defect Location registers 0x29A- 0x2A1or an unused value (0x6A) will be used. 83 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 91
... Bwd TUC0 (16) (16) Fwd Fwd Fwd SECB SECB SECB Errore Lost Misins d (8) (8) (8) Fwd Lost (16) CLP0+1 (16) 84 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION Current Count BLER Fwd CLP0+1 (16) stored BMCS (8) N (8) Fwd TUC0+1 Fwd Unuse (16) FMCS d N (8) (8) Bwd TUC0+1 ...
Page 92
... Bwd Bwd SECB SECB SECB Errore Lost Misins d (8) (8) (8) Bwd Lost (16) CLP0+1 (16) Transmitted CLP0+1 Count (32) 85 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION Bwd Bwd Bwd Tagged SECB SECB CLP0 (16) C (8) C Accum . (8) Bwd Total Lost Bwd Total Lost CLP0 (16) CLP0+1 (16) ...
Page 93
... Reserved. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 86 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 94
... TUC_0, TUC_0+1, TRCC_0 and TRCC_0+1 counts. The Bwd_PM0 bit suppresses accumulation of error counts. If this bit is not set, error counts will be accumulated. The QOS parameters of the internal PM table are described below. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 87 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 95
... It is used along with Fwd TRCC_0+1 to determine the new TRCC_0+1 upon reception of a Forward PM cell, and thus to calculate the Total User Cell Difference CLP0+1. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 88 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 96
... Forward PM cells. This count will be initialized automatically on reception of the first Forward Monitoring cell. When not a monitor point, Fwd TUC_0 will be inserted in the TUC_0 field of generated Backwards Reporting cells. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 89 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 97
... The Forward BR Monitoring Cell Sequence Number is used to determine the MCSN for generated Backwards Reporting cells. The Fwd BMCSN value is incremented each time a Backwards Routing cell is generated. There is no need to initialize this running count. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 90 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 98
... Bwd Lost FM Cells count is incremented by the number of lost FM cells, which is presumed to be equal to the change in FMCSN less the change in BMCSN. Any inference of SECBs due to lost FM cells is left up to the management software. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 91 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 99
... Misinserted (8) SECB Misinserted is incremented whenever the number of Bwd SECB Misinserted cells exceeds MMISINS in the selected threshold Misinserted(8) register. The accumulation of SECB Misinserted inhibits the accumulation of the count of Misinserted Cells. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 92 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 100
... CLP0 user cells during a PM session. The Lost CLP0 cell count Bwd Lost CLP0 is incremented by the lesser of -TUCD_0 and -TUCD_0+1, (16) whenever that number is greater than zero. This count is not incremented if the SECB Lost count is incremented. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 93 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 101
... TUC 0+1 fields of two successive Forward Monitoring cells. If the PM session is configured as an end point source, this count is derived from the actual number of CLP0+1 cells transmitted. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 94 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 102
... FM cells minus the number of lost BR cells. All error (Lost, Misinserted and Errored) counts and the Total Transmitted CLP0 and Total Transmitted CLP0+1 saturate at all ones and will not rollover. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 95 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 103
... OAM Performance Function Management Function Type Specific Fields 4 45x8 FM BR Time Unused Fwd 2x8 Stamp 6AH MCSN 4x8 27x8 1x8 PM Active1 96 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION Reserved EDC 6 (CRC-10 SECBC TRCC_ Block TRCC_ 1x8 0 Error 0+1 2x8 Result 2x8 1x8 ...
Page 104
... Interfac e Egress Cell Egres s Proce ssor O utput Cell Interface Ingres roprocessor M ic roprocessor Interfac e Cell Interfac e 97 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION Generated Backward Reporting PM Cell (4) In gress Output Cell Generated Interfac e Egres s Forward Monitoring Backw ard PM Cell (3) Cell Interface ...
Page 105
... ATLAS-1K800 provides a configurable register set to determine whether or not to include certain VCI values in F4-PM flows, and whether or not to include certain PTI values in F5-PM flows. Changes in ITU-T I.610 and Bellcore GR-1248-CORE should be monitored closely to ensure compliance. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 98 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 106
... FIFO when the COSFULLI interrupt is asserted. When reading out from the FIFO the COSVALID (Ingress register 0x23B and Egress register 0x2D7) signal should always be used to ensure that valid data is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 99 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 107
... If this bit is logic 1, the connection is an end-to-end point. The Status field contains a copy of the Status field contained in the Ingress or Egress VC Table. This field contains the 16-bit connection address with which the change of state is associated. 100 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 108
... HEC byte may be overwritten with the PHYID[4:0] field (LSB justified with the 3 MSBs set to logic 0). This is controlled by the PHYIDinHEC register bit of the Egress Cell Processor Configuration 1 register 0x280. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 101 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 109
... S/UNI-ATLAS-1K800 uses these fields for policing the connection and is responsible for updating them. The Increment and Limit fields must be programmed to the desired traffic rate. These fields relate to the traffic contract parameters as follows: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 102 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 110
... For a Sustained Cell Rate (SCR) conformance definition, the parameters relate as follows: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE ∆ PCR t æ m ö ≤ ç 1 where 0 512 è ≤ τ ∆ t Tolerance (s) 103 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ≤ ≤ m 511 LSB 0 ...
Page 111
... BT SCR è ∆ ∆ (cells/s) at the Peak Cell Rate (cells) æ m ö ç 1 ÷ where 0 512 è ≤ Integer 104 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION 1 ö PCR ≤ ≤ ≤ m 511 LSB 0 LSB Fraction ...
Page 112
... L t max max ∆ .98 cells ì ∆ .49 cells PCR í min ∆ .75 cells ∆ .37 cells/s : î 105 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION cell rate at 622Mbps then L shall max ( ) = PCR ∆ 160 ...
Page 113
... Increment the appropriate non-compliant cell count. 10 Reduce the priority of high priority cells and discard the low priority cells. Increment the appropriate non-compliant cell count. 11 Discard all non-conforming cells. Increment the appropriate non-compliant cell count. 106 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION max ...
Page 114
... Update TAT1 Update TAT2 Update TAT2 Update TAT2 Update TAT1, TAT2 Update TAT2 Update TAT1, TAT2 Update TAT2 Update TAT1, TAT2 107 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION GCRA2 Fail Tag Discard Update TAT1 Update TAT1 Update TAT1, Update TAT1, TAT2 TAT2 No Update ...
Page 115
... No Action Update TAT1 Update TAT1 Update TAT2 Update TAT2 No Update Update TAT2 No Update No Update No Update Definition Non-compliant CLP=0 cells. Non-compliant CLP=0+1 cells. 108 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION GCRA2 Fail Tag Discard Update TAT1 No Update No Update No Update No Update No Update No Update No Update ...
Page 116
... COCUP bit for the connection should be set to logic 1, when per-PHY policing is enabled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 Discarded CLP=0 cells. Discarded CLP=0+1 cells. Definition Non-compliant CLP=0 cells. Non-compliant CLP=0+1 cells. Tagged CLP=0 cells which are not discarded. Discarded CLP=0+1 cells. 109 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 117
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 Per-PHY GCRA Pass No Action Update VC TAT Update VC TAT Update PHY TAT Update PHY TAT No Update Update PHY TAT No Update No Update No Update 110 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION Fail Tag Discard Update VC TAT No Update No Update No Update No Update No Update No Update No Update ...
Page 118
... CLP=0 cells. Increment the appropriate non- compliant cell count. 10 Reduce the priority of high priority cells and discard the low priority cells. Increment the appropriate non-compliant cell count. 11 Discard all non-conforming cells. 111 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION 0 PHY L (14) (16) (16) ...
Page 119
... Definition Non-compliant CLP=0 cells. Non-compliant CLP=0+1 cells. Discarded CLP=0 cells. Discarded CLP=0+1 cells. Definition Non-compliant CLP=0 cells. Non-compliant CLP=0+1 cells. Tagged CLP=0 cells which are not discarded. Discarded CLP=0+1 cells. Per-VC Policing Compliant 112 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION Non-Compliant ...
Page 120
... Per-VC Policing Compliant No update. Update per-VC non- compliant counts. Update per-PHY non- compliant counts 113 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION Update per-VC non- compliant counts Don’t update per-PHY non-compliant counts. Update per-VC non- compliant counts. Update per-PHY non- compliant counts ...
Page 121
... EOM) will be tagged. In other words, the tagging action taken by this conformance test is determined at frame boundaries only. If the MCR conformance test is programmed to discard, the S/UNI-ATLAS-1K800 can discard at any point in the frame and is not restricted by frame boundaries. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 114 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 122
... MCR policing instance). 100: 101: initially being tagged, then entered PPD discard). 110-111: Reserved PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 Complete Packet Discard Partial Packet Discard with Tagging (packet was 115 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 123
... The forced action that is taken is dependent on the state of the Action2[1:0] field of the Ingress VC Table at ISA[19:16]=0100. The Violate field may be encoded as follows: Violate=1 Action2[1:0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 Description Take no forced action Tag all CLP=0 cells. Take no action on CLP=1 cells. 116 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 124
... Two 32-bit cell counts that may be programmed to count any combination of the following: A. CLP0 user cells. B. CLP1 user cells. C. CLP0 OAM cells. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 Tag all CLP=0 cells. Discard all CLP=1 cells Discard all CLP=0+1 cells. 117 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 125
... SECBs). • Number of Severely Errored Cell Blocks for Lost CLP0+1 cells • Number of Severely Errored Cell Blocks for Misinserted cells • Number of Severely Errored Cell Blocks for BIP-16 violations PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 118 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 126
... Function Type cells with an incorrect CRC-10. • (Ingress only) Number of cells with errored headers. These include cells with unassigned/invalid VPI/VCIs or invalid PTI values. • (Ingress only) Last Unknown VPI.VCI value. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 119 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 127
... Note, the per-PHY counts are read only values and therefore cannot be cleared by writing all zeros. The Performance Monitoring counts always saturate and non-compliant per-VC cell counts always saturate. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 120 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 128
... Tables determines how the S/UNI-ATLAS-1K800 will behave with respect to a particular connection. The OAM functionality of the S/UNI-ATLAS-1K800 is symmetric in the Ingress and Egress directions. The OAM Configuration field for both the Ingress and Egress VC Tables is shown below: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 121 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 129
... The end-to-end CC cell is generated at an interval of one per second (nominally). If the ForceCC register bit is logic 1, then when the CC_Activate_End_to_End bit is logic 1, an end-to-end CC cell will be generated at an interval of once per second (nominally), regardless of the flow of user cells. 122 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 130
... For F5 connections (VCCs), all cells with PTI = 101 are terminated and processed. The End-to-End point, by definition, is also the end point for segment cells. Therefore, at End-to-End points all segment cells, as defined above, are also terminated. 123 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 131
... RDI cells will contain the local defect type selected by the Defect_Type field in the configuration field of the Egress VC Table, and will contain the default 0x6A6A pattern in the defect location field. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 124 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 132
... Each connection belonging to a PHY device for which the defect condition is set will generate a Fault Management cell of the appropriate type. For RDI cells, only those connections that are end-to-end points will have RDI cells generated. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 125 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 133
... If the S/UNI-ATLAS-1K800 is not a flow end-point for an OAM flow, all System Management cells are passed to the Ingress/Egress Output Cell Interface. If the S/UNI-ATLAS-1K800 is an OAM flow end-point, the System Management cells are optionally passed to the Ingress/Egress Microprocessor Cell Interface. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 126 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 134
... VPC connections at the Ingress. Note that each VCC connection has its VPC pointer pointing to the Segment F4 OAM connection, and the Segment F4 connection points to the End-to-End F4 OAM connection. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 127 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 135
... Figure OAM Flows VPC VPC Connection The following Fault Management scenarios are supported by the ATLAS- 1K800 at the Ingress direction. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 128 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION VCC1 VCC2 VCCn Ingress VC Table VCC1 VCC2 VCCn ...
Page 136
... AIS_end_to_end alarm bit is asserted for the end-to-end VPC connection). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 VCC1 VCC2 VCC3 VCC4 VCC5 129 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION VCC-AIS-Seg (Connection w ithin a defined segm ent) VCC-AIS-EtE (Connection not w ithin a defined segm ent) VCC-AIS-EtE VCC-RDI-Seg VCC-RDI-EtE VCC-RDI-Seg VCC-RDI-EtE ...
Page 137
... Segm ent End-Point F4 (VPC) VPC-AIS-Seg VPC-RDI-Seg PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 VCC1 VCC2 VCC3 VCC4 VCC5 130 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION VCC-AIS-Seg (Connection w ithin a defined segm ent) VCC-AIS-EtE (Connection not w ithin a defined segm ent) VCC-AIS-EtE VCC-RDI-Seg VCC-RDI-EtE VCC-RDI-Seg VCC-RDI-EtE ...
Page 138
... AIS alarm. VCC5 will continue to generated segment VCC-RDI and end-to-end VCC-RDI cells at a rate of one per second (nominally) while the segment VPC connection is in AIS alarm (i.e. the AIS_end_to_end alarm bit is set). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 131 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 139
... VPC-AIS cell will be generated within 0.5 seconds of entering the VPC Segment AIS alarm condition and once per second (nominally) thereafter until the VPC Segment AIS alarm condition is exited. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 VPC-RD I-Seg (Only generated if APS is not available) VPC-AIS-EtE 132 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 140
... VPC connection exits the AIS alarm state. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 VCC1 VCC2 VCC3 VCC4 VCC5 133 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION VCC-AIS-Seg (Connection w ithin a defined segm ent) VCC-AIS-EtE (Connection not w ithin a defined segm ent) VCC-AIS-EtE VCC-RDI-Seg VCC-RDI-EtE VCC-RDI-Seg VCC-RDI-EtE ...
Page 141
... The end-to-end VPC connection would only terminate the segment VPC-AIS cell and no further action would be taken at the F4 level. The table below summarizes the behavior of the S/UNI-ATLAS-1K800 for Fault Management: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 134 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 142
... Generate VC Generate VC Segment RDI End-to-End RDI (4) (4) (5) Generate VC Generate VC End-to-End AIS Segment RDI (4), (6) (4) 135 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION VC Non End-Point Within a VC Not within a Segment VC Segment Generate VC Generate VC Segment AIS End-to-End (3), (4) AIS (4) Generate VC Generate VC ...
Page 143
... VPC-AIS cell is received, an end-to-end VPC-AIS cell is generated (assuming that end-to-end VPC-AIS cells are not being received). When the APSx register bit is logic 1, an end-to-end VPC-AIS cell is not generated in this circumstance. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 136 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 144
... CC Alarm state. If user or CC cells are not transmitted, the VPC and VCC connections will enter the CC Alarm state, and CC cells can be optionally transmitted to ensure the downstream entities do not enter the CC Alarm state. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 137 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 145
... Segment F4 OAM connection, and the Segment F4 connection points to the End-to-End F4 OAM connection. Figure OAM Flows VPC VPC Connection PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 138 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION VCC1 VCC2 VCCn Egress VC Table VCC1 VCC2 VCCn ...
Page 146
... VPC segment end-point will generate an end-to-end VPC AIS cell within 0.5 seconds and once per second (nominally) thereafter until the VPC Segment AIS alarm condition has exited. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 VPC-RDI-Seg VPC-AIS-EtE (Only generated if APS is not available) 139 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 147
... F52: F5 (VCC) Segment flow. Figure 16 VPC Intermediate Point VP-Interm ediate Point Ingress Egress PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 F41 and F42 F41 or F42 or both Obs AIS G en F41 or F42 or both F41 and F42 AIS G en Obs 140 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 148
... F51 and F52 AIS G en Obs F41 AIS F41 or F42 Gen or both Obs F42 Del F42 F42 RDI F41 AIS F42 AIS, RDI Gen Gen CC Gen Gen 141 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION F42 AIS, CC Gen F41 or F42 or both Obs F42 Del ...
Page 149
... F42 F41 Obs Del F42 Del F41 F42 RDI RDI Gen Gen F41 F42 RDI RDI F41 Gen Gen Del F42 Del 142 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION F52 AIS, CC Gen F51 or F52 or both Obs F52 Del F41 and F42 Obs ...
Page 150
... Create F51 and F52 Obs F41 Del F42 Del F41 or F42 or both RDI Gen F41 and F42 Create 143 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION F51 AIS Gen, F52 AIS,CC Gen F52 Del F52 RDI Gen F51 and F52 F52 RDI Obs ...
Page 151
... AIS/CC cells can be generated. If the Ingress Output Cell Interface is full, this process will be suspended AIS or CC cell is generated, the process will be suspended until the expiry of a user programmable counter threshold. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 144 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 152
... CC cell is generated, the process will be suspended until the expiry of a user programmable counter threshold. Policing is not performed in the Egress path of the S/UNI-ATLAS-1K800, therefore, no TAT updating process needs to be performed. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 145 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 153
... Ingress Backward OAM Cell Interface at the specified insertion rate. The BCIF insertion rate is the minimum rate at which cells will be inserted from the Ingress BCIF. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 146 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 154
... PM and per-PHY policing RAM can be accessed through this port. Test mode registers are used to enhance the testability of the S/UNI-ATLAS-1K800. The interface has a 16-bit wide data bus. Multiplexed address and data operation is supported. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 147 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 155
... The S/UNI-ATLAS-1K800 contains a one cell buffer for the assembly of a cell by the microprocessor for presentation on the Ingress or Egress Output Cell Interface. Optional header translation and CRC-10 protection provides full support of diagnostic and OAM requirements. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 148 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 156
... Write the cell contents to the Ingress/Egress Microprocessor Cell Interface Data register. Each subsequent write enters the next word in the cell. The words shall be written in the following order: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 149 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 157
... Last postpended word, N<6 (optional) ATM Header: GFC, VPI, VCI[15:12] ATM Header: VCI[11:0], PTI, CLP HEC and UDF fields st 1 ATM payload word nd 2 ATM payload word … ATM payload word 150 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 158
... Configuration register. The Egress Cell Processor does not perform a direct lookup of cells inserted when UPHDRX=0, therefore the cell need not belong to a provisioned connection. The per-connection cell counts will not increment as a result of an inserted cell with UPHDRX=0. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 151 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 159
... Ingress/Egress Cell Processor Configuration register. If the UPURS bit is a logic 1, a causation word is prepended to the cell to indicate why the cell was routed to the Ingress/Egress MCIF and provides cell status information. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 LEN[2:0] Buffer Capacity 152 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 160
... PROV is a logic 0. End_to_End_Point Indicates the connection is provisioned as an OAM flow end point. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 Definition PHYID[4] PHYID[3] PHYID[2] PHYID[1] PHYID[0] PROV End_to_End_Point Segment_End_Point TimeOut NNI VPC OAM_Type TYP[3] TYP[2] TYP[1] TYP[0] 153 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 161
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 TYP[3:0] Cell Type 0000 User 0001 AIS 0010 RDI 0011 Continuity Check 0100 Loopback 0101 Forward Monitoring 0110 Backward Reporting 0111 Reserved 1000 Activate/Deactivate 1001 Undefined OAM 1010 System Management OAM 154 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 162
... RUN bit, in register 0x00C, is set. The RUN bit indicates that all DLL’s in the S/UNI- ATLAS-1K800 are operating correctly and have locked-on to the input clock frequency. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 1011 Forward RM 1100 Backward RM 1101 Invalid PTI/VCI 1110 Reserved 1111 OAM cell with errored CRC-10 155 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 163
... EGRESS MICROPROCESSOR INSERT CELL INTERFACE CONTROL AND STATUS ............................................................ 236 EGRESS MICROPROCESSOR CELL DATA .............................. 239 INGRESS RDI BACKWARD OAM CELL INTERFACE CONFIGURATION #1................................................................... 241 RESERVED .................................................................................. 242 RESERVED .................................................................................. 242 RESERVED .................................................................................. 242 RESERVED .................................................................................. 242 INGRESS BACKWARD REPORTING OAM CELL INTERFACE CONFIGURATION #1 ............................................ 243 156 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 164
... FIELD B LOCATION AND LENGTH............................................. 267 INGRESS BACKWARD OAM CELL INTERFACE PACING ........ 268 RESERVED .................................................................................. 269 INGRESS VC TABLE DATA ROW 0, WORD 0 (LSW) (RAM DATA[15:0]) .................................................................................. 270 INGRESS VC TABLE DATA ROW 0, WORD 1 (RAM DATA [31:16]) .......................................................................................... 271 INGRESS VC TABLE DATA ROW 0, WORD 2 (RAM DATA [47:32]) .......................................................................................... 272 157 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 165
... INGRESS VC TABLE DATA ROW 6, WORD 2 (RAM DATA [47:32]) .......................................................................................... 275 INGRESS VC TABLE DATA ROW 6, WORD 3 (MSW) (RAM DATA [63:48]) ............................................................................... 275 INGRESS VC TABLE DATA ROW 7, WORD 0 (LSW) (RAM DATA [15:0]) ................................................................................. 276 INGRESS VC TABLE DATA ROW 7, WORD 1 (RAM DATA [31:16]) .......................................................................................... 276 158 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 166
... DATA[15:0]) .................................................................................. 278 INGRESS VC TABLE DATA ROW 13 WORD 1 (RAM DATA [31:16]) .......................................................................................... 278 INGRESS VC TABLE DATA ROW 13 WORD 2 (RAM DATA [47:32]) .......................................................................................... 278 INGRESS VC TABLE DATA ROW 13 WORD 3 (MSW) (RAM DATA [63:48]) ............................................................................... 278 INGRESS VC TABLE DATA ROW 14 WORD 0 (LSW) (RAM DATA[15:0]) .................................................................................. 278 159 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 167
... INGRESS PER-PHY AIS CELL GENERATION CONTROL 1 ..... 315 INGRESS PER-PHY AIS CELL GENERATION CONTROL 2 ..... 316 INGRESS PER-PHY RDI CELL GENERATION CONTROL 1 ..... 317 INGRESS PER-PHY RDI CELL GENERATION CONTROL 2 ..... 318 INGRESS OAM DEFECT TYPE0 AND 1 ..................................... 319 INGRESS OAM DEFECT TYPE 2 AND 3 .................................... 320 160 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 168
... EGRESS OAM DEFECT TYPE 0 AND 1 ..................................... 371 EGRESS OAM DEFECT TYPE 2 AND 3 ..................................... 372 EGRESS OAM DEFECT TYPE 4 AND 5 ..................................... 372 EGRESS OAM DEFECT TYPE 6 AND 7 ..................................... 372 EGRESS OAM DEFECT TYPE 8 AND 9 ..................................... 372 EGRESS OAM DEFECT TYPE 10 AND 11 ................................. 372 161 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 169
... EGRESS VC TABLE RECORD ROW 4, WORD 0 (LSW) RAM DATA ............................................................................................ 388 EGRESS VC TABLE RECORD ROW 4, WORD 1 (MSW) RAM DATA ................................................................................... 388 EGRESS VC TABLE RECORD ROW 5, WORD 0 (LSW) RAM DATA ............................................................................................ 388 EGRESS VC TABLE RECORD ROW 5, WORD 1 (MSW) RAM DATA ................................................................................... 388 162 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 170
... EGRESS PERFORMANCE MONITORING RAM WRITE MASK ............................................................................................ 393 EGRESS PERFORMANCE MONITORING RAM DATA WORD 0 (LSW) ............................................................................ 394 EGRESS PERFORMANCE MONITORING RAM DATA WORD 1 ....................................................................................... 395 EGRESS PERFORMANCE MONITORING RAM DATA WORD 2 ....................................................................................... 396 EGRESS PERFORMANCE MONITORING RAM DATA WORD3 ........................................................................................ 397 163 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 171
... PHY2 INGRESS ERRORED OAM/RM CELL COUNT................. 418 PHY2 INGRESS INVALID VPI/VCI/PTI CELL COUNT ................ 418 PHY2 INGRESS NON-ZERO GFC CELL COUNT....................... 418 PHY2 INGRESS LAST UNKNOWN VPI.VCI (VCI VALUE) ......... 418 PHY2 INGRESS LAST UNKNOWN VPI.VCI (VPI VALUE) ......... 418 164 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 172
... PHY2 EGRESS CLP1 CELL COUNT (LSB)................................. 433 PHY2 EGRESS CLP1 CELL COUNT (MSB)................................ 433 PHY2 EGRESS VALID OAM CELL COUNT ................................ 433 PHY2 EGRESS VALID RM CELL COUNT................................... 433 PHY2 EGRESS ERRORED OAM/RM CELL COUNT .................. 433 PHY2 EGRESS INVALID VCI/PTI CELL COUNT ........................ 433 165 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 173
... STANDARD PRODUCT DATASHEET PMC-2010142 REGISTER 0X7E0-0X7E9: PHY31 EGRESS STATUS AND COUNTS................................... 435 REGISTER 0X7F0-0X7F9: PHY32 EGRESS STATUS AND COUNTS................................... 435 REGISTER 0X800: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 MASTER TEST............................................................................. 437 166 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 174
... Certain register bits are reserved. These bits are associated with megacell functions that are unused in this application. To ensure that the S/UNI-ATLAS-1K800 operates, as intended, reserved register bits must only be written with the value indicated. Similarly, writing to reserved registers should be avoided. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 167 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 175
... The ID bits can be read to provide a binary number indicating the S/UNI- ATLAS-1K800 feature version. NOTE 1: Rev A ID[3:0] = 0000 Rev B ID[3:0] = 0001 Rev C ID[3:0] = 0010 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 Function Default RESET 0 Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X TYPE[2] 0 TYPE[1] 0 TYPE[0] 1 ID[3] Note 1 ID[2] Note 1 ID[1] Note 1 ID[0] Note 1 168 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 176
... A hardware reset clears the RESET bit, thus negating the software reset. Otherwise, the effect of the software reset is equivalent to that of the hardware reset. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 169 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 177
... S/UNI-ATLAS-1K800. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 Function Default Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X BUSYPOL 0 DREQINV 0 SEL1SEC 0 CLKRATE[1] 0 CLKRATE[0] 0 ESTANDBY 1 ISTANDBY 1 170 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 178
... The DREQINV bit inverts the polarity of the IDREQ and EDREQ primary outputs. If DREQINV is logic 0, the IDREQ and EDREQ outputs are active high. If DREQINV is logic 1, the IDREQ and EDREQ outputs are active low. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 Assumed ISYSCLK frequency 25 MHz 50 MHz 52 MHz Reserved 171 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 179
... STANDARD PRODUCT DATASHEET PMC-2010142 BUSYPOL: The BUSYPOL bit sets the polarity of the BUSYB primary output. If BUSYPOL is logic 0, the BUSYB primary output is active low. If BUSYPOL is logic 1, the BUSYB output is active high. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 172 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 180
... This bit is cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 Function Default REG6I X REG5I X REG4I X REG3I X I_XFERI X I_XPOLI X I_POLI X I_END_RDII X I_SEG_RDII X I_END_AISI X I_SEG_AISI X I_END_CCI X I_SEG_CCI X I_OAMERRI X I_PTIVCII X I_INVALI X 173 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 181
... Table) has changed state. When logic 1, the I_SEG_RDII bit indicates the Segment RDI Alarm bit in the Ingress VC Table has changed state for one or more virtual connections. This bit is cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 174 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 182
... The REG5I bit indicates that at least one bit in register 0x005, S/UNI-ATLAS- 1K800 Master Interrupt Status #4, is currently asserted. REG6I: The REG6I bit indicates that at least one bit in register 0x006, S/UNI-ATLAS- 1K800 Master Interrupt Status #5, is currently asserted. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 175 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 183
... FIFO overflow occurs. This bit is cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 Function Default REG6I X REG5I X REG4I X I_XCOSI X I_COSFULLI X I_PHYXPOLI X I_PHYPOLI X I_BCIFFULLI X I_SRCHERRI X I_PCELLI X I_RPRTYI X I_RSOCI X I_INSRDYI X I_UPCAI X I_UPFOVRI X I_FULLI X 176 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 184
... If the I_BADVCtoUP register bit is a logic 1, the cell associated with the failed search is routed to the Ingress Microprocessor Cell Interface Extract FIFO. This bit is cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 177 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 185
... FIFO space becomes free the responsibility of the management software to ensure this FIFO is read often enough to ensure the notification of changes of state are compliant with Bellcore and ITU standards. This bit is cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 178 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 186
... The REG5I bit indicates that at least one bit in Register 0x005, S/UNI-ATLAS- 1K800 Master Interrupt Status #4 is currently asserted. REG6I: The REG6I bit indicates that at least one bit in Register 0x006, S/UNI-ATLAS- 1K800 Master Interrupt Status #5 is currently asserted. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 179 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 187
... Parity error over inputs ISD[7:0] All bits are cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 Function Default REG6I X REG5I X Unused X Unused X E_SPRTYI[3] X E_SPRTYI[2] X E_SPRTYI[1] X E_SPRTYI[0] X I_SPRTYI[7] X I_SPRTYI[6] X I_SPRTYI[5] X I_SPRTYI[4] X I_SPRTYI[3] X I_SPRTYI[2] X I_SPRTYI[1] X I_SPRTYI[0] X 180 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 188
... The REG5I bit indicates that at least one bit in Register 0x005, S/UNI-ATLAS- 1K800 Master Interrupt Status #4, is currently asserted. REG6I: The REG6I bit indicates that at least one bit in Register 0x006, S/UNI-ATLAS- 1K800 Master Interrupt Status #5, is currently asserted. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 181 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 189
... This bit is cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 Function Default REG6I X E_PCELLI X E_IOVRI X E_INSRDYI X E_UPCAI X E_UPFOVRI X E_FULLI X E_End_RDII X E_Seg_RDII X E_End_AISI X E_Seg_AISI X E_END_CCI X E_SEG_CCI X E_OAMERRI X E_PTIVCII X E_XFERI x 182 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 190
... Table) has changed state. When logic 1, the E_SEG_RDII bit indicates the Segment RDI Alarm bit in the Egress VC Table has changed state for one or more virtual connections. This bit is cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 183 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 191
... Egress Input Cell Interface. When logic 1, the E_PCELLI bit indicates one or more cells with an all zero VPI and VCI value and a CLP=1 have been received at the Egress Input Cell Interface. This bit is cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 184 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 192
... STANDARD PRODUCT DATASHEET PMC-2010142 REG6I: The REG6I bit indicates that at least one bit in Register 0x006, S/UNI-ATLAS- 1K800 Master Interrupt Status #5, is currently asserted. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 185 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 193
... The E_IWRENBI bit indicates more than one of the E_IWRENB[4:1] inputs were asserted simultaneously attempt to write a new cell with a PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 Function Default Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X E_SEARCHEI X E_XCOSI X E_COSFULLI X E_BCIFFULLI X E_IWRENBI X E_IPRTYI X E_ISOCI X 186 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 194
... If a parity error is detected, interrupt is asserted. If the BADVCtoUP register bit is a logic 1, the cell associated with the failed search is routed to the Egress Microprocessor Cell Interface Extract FIFO. This bit is cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 187 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 195
... INTB output is asserted low when the corresponding interrupt status bit is a logic 1. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 Function Default Unused X Unused X Unused X Unused X I_XFERE 0 I_XPOLE 0 I_POLE 0 I_END_RDIE 0 I_SEG_RDIE 0 I_END_AISE 0 I_SEG_AISE 0 I_END_CCE 0 I_SEG_CCE 0 I_OAMERRE 0 I_PTIVCIE 0 I_INVALE 0 188 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 196
... INTB output is asserted low when the corresponding interrupt status bit is a logic 1. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 Function Default Unused X Unused X Unused X I_XCOSE 0 I_COSFULLE 0 I_PHYXPOLE 0 I_PHYPOLE 0 I_BCIFFULLE 0 I_SRCHERRE 0 I_PCELLE 0 I_RPRTYE 0 I_RSOCE 0 I_INSRDYE 0 I_UPCAE 0 I_UPFOVRE 0 I_FULLE 0 189 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 197
... INTB output is asserted low when the corresponding interrupt status bit is a logic 1. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 Function Default Unused X Unused X Unused X Unused X E_SPRYTE[3] 0 E_SPRYTE[2] 0 E_SPRYTE[1] 0 E_SPRYTE[0] 0 I_SPRYTE[7] 0 I_SPRYTE[6] 0 I_SPRYTE[5] 0 I_SPRYTE[4] 0 I_SPRYTE[3] 0 I_SPRYTE[2] 0 I_SPRYTE[1] 0 I_SPRYTE[0] 0 190 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 198
... INTB output is asserted low when the corresponding interrupt status bit is a logic 1. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 Function Default Unused X E_PCELLE 0 E_IOVRE 0 E_INSRDYE 0 E_UPCAE 0 E_UPFOVRE 0 E_FULLE 0 E_END_RDIE 0 E_SEG_RDIE 0 E_END_AISE 0 E_SEG_AISE 0 E_END_CCE 0 E_SEG_CCE 0 E_OAMERRE 0 E_PTIVCIE 0 E_XFERE 0 191 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 199
... INTB output is asserted low when the corresponding interrupt status bit is a logic 1. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 Function Default Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X E_SEARCHE 0 E_XCOSE 0 E_COSFULLE 0 E_BCIFFULLE 0 E_IWRENBE 0 E_IPRTYE 0 E_ISOCE 0 192 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...
Page 200
... ISYSCLK input. ISYSCLKA is set high on a rising edge of ISYSCLK, and is set low when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC ISSUE 2 Function Default DLLRUN X RSTDLL 0 Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X TFCLKA X IFCLKA X ESYSCKLA X OFCLKA X RFCLKA X ISYSCLKA X 193 PM7328 S/UNI-ATLAS-1K800 ATM LAYER SOLUTION ...