KM44C4005CS-6 Samsung, KM44C4005CS-6 Datasheet

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KM44C4005CS-6

Manufacturer Part Number
KM44C4005CS-6
Description
4M x 4bit CMOS quad CAS DRAM with extended data out, 60ns
Manufacturer
Samsung
Datasheet

Specifications of KM44C4005CS-6

Case
TSOP

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Part Number:
KM44C4005CS-6
Manufacturer:
SAMSUNG
Quantity:
8
This is a family of 4,194,304 x 4 bit Quad CAS with Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high
speed random access of memory cells within the same row, so called Hyper Page Mode. Refresh cycle (2K Ref. or 4K Ref.), access
time (-5 or -6), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of
this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is avail-
able in L-version. Four separate CAS pins provide for seperate I/O operation allowing this device to operate in parity mode.
This 4Mx4 Extended Data Out Quad CAS DRAM family is fabricated using Samsung s advanced CMOS process to realize high band-
width, low power consumption and high reliability.
FEATURES
• Part Identification
• Active Power Dissipation
• Refresh Cycles
• Performance Range
KM44C4005C, KM44C4105C
Speed
C4005C
C4105C
Speed
- KM44C4005C/C-L (5V, 4K Ref.)
- KM44C4105C/C-L (5V, 2K Ref.)
-5
-6
Part
NO.
-5
-6
50ns
60ns
t
RAC
Refresh
cycle
4K
2K
495
440
4M x 4Bit CMOS Quad CAS DRAM with Extended Data Out
4K
13ns
15ns
t
CAC
Refresh Cycle
Normal
64ms
32ms
Refresh period
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
104ns
84ns
t
RC
605
550
2K
128ms
Unit : mW
L-ver
20ns
25ns
t
HPC
DESCRIPTION
(A0 - A10)
(A0 - A10)
CAS0 - 3
A0-A11
A0 - A9
RAS
Note)
W
*1
*1
*1
: 2K Refresh
FUNCTIONAL BLOCK DIAGRAM
• Extended Data Out mode operation
• Four separate CAS pins provide for separate I/O operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
• TTL compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic SOJ and TSOP(II) packages
• Single +5V 10% power supply
(Fast Page Mode with Extended Data Out)
Control
Clocks
Row Address Buffer
Col. Address Buffer
Refresh Counter
Refresh Control
Refresh Timer
VBB Generator
Column Decoder
Memory Array
4,194,304 x 4
Row Decoder
Cells
CMOS DRAM
Vcc
Vss
Data out
Data in
Buffer
Buffer
OE
DQ0
DQ3
to

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KM44C4005CS-6 Summary of contents

Page 1

... L-version. Four separate CAS pins provide for seperate I/O operation allowing this device to operate in parity mode. This 4Mx4 Extended Data Out Quad CAS DRAM family is fabricated using Samsung s advanced CMOS process to realize high band- width, low power consumption and high reliability. ...

Page 2

KM44C4005C, KM44C4105C •KM44C40(1)05CK V CC DQ0 DQ1 W RAS *A11(N.C) CAS0 CAS1 A10 *A11 is N.C for KM44C4105C(5V, 2K Ref. product 300mil 28 SOJ S : 300mil 28 TSOP II PIN CONFIGURATION ...

Page 3

KM44C4005C, KM44C4105C ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative Voltage on V supply relative Storage Temperature Power Dissipation Short Circuit Output Current * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" ...

Page 4

KM44C4005C, KM44C4105C DC AND OPERATING CHARACTERISTICS Symbol Power I Don t care CC1 Normal I Don t care CC2 L I Don t care CC3 I Don t care CC4 Normal I Don t care CC5 L I Don t ...

Page 5

KM44C4005C, KM44C4105C CAPACITANCE (T = Parameter Input capacitance [A0 ~ A11] Input capacitance [RAS, CASx, W, OE] Output capacitance [DQ0 - DQ3] AC CHARACTERISTICS ( Test condition : V =5.0V 10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V CC Parameter ...

Page 6

KM44C4005C, KM44C4105C AC CHARACTERISTICS (Continued) Parameter Data set-up time Data hold time Refresh period (2K, Normal) Refresh period (4K, Normal) Refresh period (L-ver) Write command set-up time CAS to W delay time RAS to W delay time Column address to ...

Page 7

KM44C4005C, KM44C4105C TEST MODE CYCLE Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address RAS pulse width CAS pulse width RAS hold time CAS hold time ...

Page 8

KM44C4005C, KM44C4105C NOTES An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles 1. before proper device operation is achieved (min) and V (max) are reference levels for measuring ...

Page 9

KM44C4005C, KM44C4105C READ CYCLE RAS CRP CAS0 CRP CAS1 CRP CAS2 CRP ...

Page 10

KM44C4005C, KM44C4105C WRITE CYCLE ( EARLY WRITE ) NOTE : D = OPEN OUT RAS CRP CAS0 CRP CAS1 ...

Page 11

KM44C4005C, KM44C4105C WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : D = OPEN OUT RAS CRP CAS0 CRP CAS1 ...

Page 12

KM44C4005C, KM44C4105C READ - MODIFY - WRTIE CYCLE RAS CRP CAS0 CRP CAS1 CRP CAS2 V ...

Page 13

KM44C4005C, KM44C4105C HYPER PAGE MODE READ CYCLE RAS CRP CAS0 CAS1 CAS2 ...

Page 14

KM44C4005C, KM44C4105C HYPER PAGE MODE WRITE CYCLE ( EARLY WRITE ) NOTE : D = OPEN OUT RAS CRP CAS0 CAS1 ...

Page 15

KM44C4005C, KM44C4105C HYPER PAGE READ - MODIFY - WRITE CYCLE RAS CAS0 CAS1 CAS2 ...

Page 16

KM44C4005C, KM44C4105C RAS - ONLY REFRESH CYCLE* NOTE : W, OE Don t care OPEN OUT RAS CRP CASX ASR V ...

Page 17

KM44C4005C, KM44C4105C HIDDEN REFRESH CYCLE ( READ ) RAS CRP CASX ASR ADDRESS ...

Page 18

KM44C4005C, KM44C4105C HIDDEN REFRESH CYCLE ( WRITE ) NOTE : D = OPEN OUT RAS CRP CASX ASR ADDRESS ...

Page 19

KM44C4005C, KM44C4105C CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE Don t care, WE=Vcc-0. RAS CASX DQ0 ~ DQ3 ...

Page 20

KM44C4005C, KM44C4105C PACKAGE DIMENSION 28 SOJ 300mil #28 #1 0.0375 (0.95) 28 TSOP(II) 300mil 0.037 (0.95) 0.741 (18.82) MAX 0.720 (18.30) 0.730 (18.54) 0.050 (1.27) 0.026 (0.66) 0.032 (0.81) 0.015 (0.38) 0.021 (0.53) 0.741 (18.81) MAX 0.721 (18.31) 0.047 (1.20) ...

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