AD1896YRS Analog Devices, AD1896YRS Datasheet
AD1896YRS
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AD1896YRS Summary of contents
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... PRODUCT OVERVIEW The AD1896 is a 24-bit, high-performance, single-chip, second- generation asynchronous sample rate converter. Based upon Analog Devices Inc. experience with its first asynchronous sample rate converter, the AD1890, the AD1896 offers improved performance and additional features. This improved performance includes a THD + N range of –117 dB to –133 dB depending ...
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AD1896–SPECIFICATIONS TEST CONDITIONS UNLESS OTHERWISE NOTED Supply Voltages VDD_CORE 3.3 V VDD_IO 5 3.3 V Ambient Temperature 25°C Input Clock 30.0 MHz Input Signal 1.000 kHz, 0 dBFS Measurement Bandwidth S_OUT Word Width 24 Bits ...
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DIGITAL TIMING (–40 C < T < +105 C, VDD_CORE = 3 Parameter t MCLK_I Period MCLKI f MCLK_I Frequency MCLK t MCLK_I Pulsewidth High MPWH t MCLK_I Pulsewidth Low MPWL Input Serial Port Timing t LRCLK_I ...
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AD1896–SPECIFICATIONS DIGITAL FILTERS (VDD_CORE = 3.3 V Parameter Passband Passband Ripple Transition Band Stop Band Stop Band Attenuation Group Delay Specifications subject to change without notice. DIGITAL I/O CHARACTERISTICS (VDD_CORE = 3.3 V Parameter Input Voltage ...
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... Model Temperature Range AD1896YRS –40°C to +105°C AD1896YRSRL –40°C to +105°C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1896 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges ...
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AD1896 Pin No. IN/OUT Mnemonic 1 IN GRPDLYS 2 IN MCLK_IN 3 OUT MCLK_OUT 4 IN SDATA_I 5 IN/OUT SCLK_I 6 IN/OUT LRCLK_I 7 IN VDD_IO 8 IN DGND 9 IN BYPASS 10 IN SMODE_IN_0 11 IN SMODE_IN_1 12 IN ...
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FREQUENCY – kHz 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 –200 2.5 5.0 7.5 10.0 12.5 15.0 17.5 FREQUENCY ...
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AD1896 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 –200 2.5 5.0 7.5 10.0 12.5 FREQUENCY – kHz –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 –180 –190 –200 2.5 5.0 7.5 10.0 ...
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FREQUENCY – kHz –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 –180 ...
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AD1896 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 –200 FREQUENCY – kHz 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 –200 2.5 5.0 7.5 10.0 12.5 15.0 FREQUENCY – kHz ...
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OUTPUT SAMPLE RATE – kHz –119 –121 –123 –125 –127 –129 –131 –133 –135 105 130 155 OUTPUT SAMPLE RATE – kHz ...
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AD1896 –130 –131 –132 –133 –134 –135 –136 –137 –138 –139 –140 105 130 OUTPUT SAMPLE RATE – kHz 0 –20 –40 192kHz:96kHz –60 192kHz:48kHz –80 –100 192kHz:32kHz –120 –140 FREQUENCY – kHz ...
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INPUT LEVEL – dBFS –1 –2 –3 –4 –5 – – ...
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AD1896 –110 –115 –120 –125 –130 –135 –140 –145 –150 –155 –160 –165 –170 –175 –180 –140 –120 –100 –80 –60 INPUT LEVEL – dBFS –110 –115 –120 –125 –130 –135 –140 –145 –150 –155 –160 –165 –170 –175 –180 ...
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FREQUENCY – kHz –110 –115 –120 –125 –130 –135 –140 –145 –150 –155 –160 –165 –170 –175 –180 2.5 5.0 ...
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AD1896 ASRC FUNCTIONAL OVERVIEW THEORY OF OPERATION Asynchronous sample rate conversion is converting data from one clock source at some sample rate to another clock source at the same or different sample rate. The simplest approach to asynchronous sample rate ...
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IN INTERPOLATE LOW-PASS BY N FILTER f S_IN FREQUENCY DOMAIN OF SAMPLES AT f FREQUENCY DOMAIN OF THE INTERPOLATION SIN(X)/X OF ZERO-ORDER HOLD FREQUENCY DOMAIN OF f RESAMPLING S_OUT FREQUENCY DOMAIN AFTER RESAMPLING HARDWARE MODEL The output rate of the ...
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AD1896 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 –180 –190 –200 –210 –220 0.01 0.1 The digital servo loop is essentially a ramp filter that provides the initial ...
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However, the hysteresis of the f /f S_OUT S_IN phase mismatching between two AD1896s operating with the same input clock and the same output clock. Since the hyster- esis requires a difference of more than two ratio ...
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AD1896 AD1896 MCLK_I C1 AD1896 MCLK_I MCLK_O There are, of course, maximum and minimum operating fre- quencies for the AD1896 master clock. The maximum master clock frequency at which the AD1896 is guaranteed to operate ...
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... AD1896 SDATA_O TDM_IN LRCLK_O SCLK_O PHASE-MASTER SHARC is a registered trademark of Analog Devices, Inc. LEFT CHANNEL MSB MSB LSB LEFT JUSTIFIED MODE – BITS PER CHANNEL LEFT CHANNEL MSB LSB MSB MODE – BITS PER CHANNEL ...
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AD1896 AD1896 TDM_IN SDATA_O LRCLK_O SCLK_O CLOCK-MASTER AND PHASE-MASTER MATCHED PHASE MODE (NON-TDM MODE) APPLICATION LRCLK ( S_IN SCLK I AD1896 PHASE-MASTER TDM_IN SDATA_I SDATA_O LRCLK_I LRCLK_O SCLK_O SCLK_I MCLK RESET M2 ...
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Matched-Phase Mode The matched-phase mode is the mode discussed in the Theory of Operation section that eliminates the phase mismatch between multiple AD1896s. The master AD1896 device transmits its f /f ratio through the SDATA_O pin to the slave S_OUT ...
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AD1896 PIN 1 0.079 (2.00) MAX 0.002 (0.05) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Shrink Small Outline Package (SSOP) (RS-28) 0.413 (10.50) 0.402 (10.20) 0.390 (9.90 0.220 (5.60) 0.209 (5.30) 0.197 (5.00) 0.323 (8.20) 0.307 ...