PM8315-PI PMC-Sierra Inc, PM8315-PI Datasheet
PM8315-PI
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PM8315-PI Summary of contents
Page 1
... HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 7 PM8315 TEMUX MULTIPLEXER DATASHEET ISSUE 7: MAY 2001 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... PERFORMANCE MONITOR COUNTERS (T1/E1-PMON)......... 77 1.4 BIT ORIENTED CODE DETECTOR (RBOC).............................. 78 1.5 HDLC RECEIVER (RDLC) .......................................................... 78 1.6 T1 ALARM INTEGRATOR (ALMI)............................................... 79 1.7 ELASTIC STORE (ELST)............................................................ 80 1.8 SIGNALING ELASTIC STORES (RX-SIG-ELST AND TX_SIG-ELST) ............................................................................ 80 PROPRIETARY AND CONFIDENTIAL ISSUE 7 i PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... DS3 TRANSMITTER (DS3-TRAN).............................................. 96 1.25 M23 MULTIPLEXER (MX23) ....................................................... 97 1.26 DS2 FRAMER (DS2-FRMR) ....................................................... 98 1.27 M12 MULTIPLEXER (MX12) ..................................................... 100 1.28 TRIBUTARY PAYLOAD PROCESSOR (VTPP) ........................ 101 1.29 RECEIVE TRIBUTARY PATH OVERHEAD PROCESSOR (RTOP) ...................................................................................... 104 PROPRIETARY AND CONFIDENTIAL ISSUE 7 ii PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... JTAG TEST ACCESS PORT..................................................... 131 1.45 MICROPROCESSOR INTERFACE .......................................... 131 10 NORMAL MODE REGISTER DESCRIPTION ..................................... 162 11 TEST FEATURES DESCRIPTION ...................................................... 163 11.1 JTAG TEST PORT .................................................................... 172 12 OPERATION ........................................................................................ 185 12.1 DS3 FRAME FORMAT.............................................................. 185 PROPRIETARY AND CONFIDENTIAL ISSUE 7 iii PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... SONET/SDH SERIAL ALARM PORT TIMING .......................... 257 13.6 SBI DROP BUS INTERFACE TIMING ...................................... 259 13.7 SBI ADD BUS INTERFACE TIMING ......................................... 260 13.8 EGRESS H-MVIP LINK TIMING ............................................... 260 13.9 INGRESS H-MVIP LINK TIMING .............................................. 261 PROPRIETARY AND CONFIDENTIAL ISSUE 7 iv PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... DJAT JITTER TOLERANCE T1 MODES .................................. 88 FIGURE 10 - DJAT JITTER TOLERANCE E1 MODES .................................. 89 FIGURE 11 - DJAT MINIMUM JITTER TOLERANCE VS. XCLK ACCURACY T1 MODES ....................................................................................... 90 FIGURE 12 - DJAT MINIMUM JITTER TOLERANCE VS. XCLK ACCURACY E1 MODES ....................................................................................... 90 PROPRIETARY AND CONFIDENTIAL ISSUE 7 v PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... FIGURE 35 - CRCE COUNT VS. BER (T1 ESF MODE) .............................. 191 FIGURE 36 - CRCE COUNT VS. BER (T1 SF MODE) ................................ 192 FIGURE 37 - TYPICAL DATA FRAME .......................................................... 199 FIGURE 38 - EXAMPLE MULTI-PACKET OPERATIONAL SEQUENCE ..... 199 FIGURE 39 - T1/E1 LINE LOOPBACK......................................................... 205 PROPRIETARY AND CONFIDENTIAL ISSUE 7 vi PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... FIGURE 59 - FRAMER MODE DS3 TRANSMIT INPUT STREAM WITH TGAPCLK ................................................................................. 251 FIGURE 60 - FRAMER MODE DS3 RECEIVE OUTPUT STREAM ............. 252 FIGURE 61 - FRAMER MODE DS3 RECEIVE OUTPUT STREAM WITH RGAPCLK ................................................................................. 252 PROPRIETARY AND CONFIDENTIAL ISSUE 7 vii PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... FIGURE EGRESS INTERFACE CLOCK SLAVE : EFP ENABLED MODE........................................................................................ 263 FIGURE EGRESS INTERFACE CLOCK SLAVE: EXTERNAL SIGNALING MODE ................................................................... 264 FIGURE EGRESS INTERFACE CLOCK SLAVE : EXTERNAL SIGNALING MODE ................................................................... 264 PROPRIETARY AND CONFIDENTIAL ISSUE 7 viii PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... FIGURE 94 - TELECOM BUS OUTPUT TIMING ......................................... 287 FIGURE 95 - TELECOM BUS TRISTATE OUTPUT TIMING ....................... 287 FIGURE 96 - SBI ADD BUS TIMING ............................................................ 289 FIGURE 97 - SBI DROP BUS TIMING ......................................................... 291 PROPRIETARY AND CONFIDENTIAL ISSUE 7 ix PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... FIGURE 112 - JTAG PORT INTERFACE TIMING.......................................... 310 FIGURE 113 - 324 PIN PBGA 23X23MM BODY ............................................ 312 LIST OF TABLES TABLE 1 - E1-FRMR FRAMING STATES .................................................. 75 TABLE 2 - PATH SIGNAL LABEL MISMATCH STATE ............................. 105 PROPRIETARY AND CONFIDENTIAL ISSUE 7 x PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... T1/TVT1.5 TRIBUTARY COLUMN NUMBERING ................... 213 TABLE 21 - E1/TVT2 TRIBUTARY COLUMN NUMBERING...................... 214 TABLE 22 - SBI T1/E1 LINK RATE INFORMATION................................... 217 TABLE 23 - SBI T1/E1 CLOCK RATE ENCODING.................................... 217 TABLE 24 - DS3 LINK RATE INFORMATION ............................................ 218 PROPRIETARY AND CONFIDENTIAL ISSUE 7 xi PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... REPETITIVE PATTERN GENERATION (PS BIT = 1)............. 240 TABLE 43 - ABSOLUTE MAXIMUM RATINGS ......................................... 271 TABLE 44 - D.C. CHARACTERISTICS ...................................................... 272 TABLE 45 - MICROPROCESSOR INTERFACE READ ACCESS.............. 275 TABLE 46 - MICROPROCESSOR INTERFACE WRITE ACCESS ............ 277 PROPRIETARY AND CONFIDENTIAL ISSUE 7 xii PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... INGRESS INTERFACE TIMING - CLOCK SLAVE MODES (FIGURE 108) ........................................................................... 303 TABLE 64 - INGRESS INTERFACE TIMING - CLOCK MASTER MODES (FIGURE 109) ........................................................................... 305 TABLE 65 - TRANSMIT LINE INTERFACE TIMING (FIGURE 110)........... 306 PROPRIETARY AND CONFIDENTIAL ISSUE 7 xiii PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... REMOTE SERIAL ALARM PORT TIMING.............................. 307 TABLE 67 - JTAG PORT INTERFACE ....................................................... 309 TABLE 68 - ORDERING AND THERMAL INFORMATION..........................311 TABLE 69 - THERMAL INFORMATION – THETA JA VS. AIRFLOW ..........311 PROPRIETARY AND CONFIDENTIAL ISSUE 7 xiv PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... streams multiplexed into a DS3 following the ITU-T G.747 recommendation. This E1 mode of operation is restricted to using the serial clock and data or HMVIP system interfaces. PROPRIETARY AND CONFIDENTIAL ISSUE 7 1 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... Provides robbed bit signaling extraction and insertion on a per-DS0 basis. • Provides programmable idle code substitution, data and sign inversion, and digital milliwatt code insertion on a per-DS0 basis. PROPRIETARY AND CONFIDENTIAL ISSUE 7 2 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... Provides ESF bit-oriented code detection and an HDLC/LAPD interface for terminating the ESF facility data link. • Indicates signaling state change, and two superframes of signaling debounce on a per-DS0 basis. PROPRIETARY AND CONFIDENTIAL ISSUE operation. 3 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... Extracts 4-bit codewords from the E1 national use bits as specified in ETS 300 233. • V5.2 link indication signal detection. PROPRIETARY AND CONFIDENTIAL ISSUE 7 4 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX –1, 2 – ...
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... Supports transmission of the alarm indication signal (AIS) or the Yellow alarm signal in both SF and ESF formats. PROPRIETARY AND CONFIDENTIAL ISSUE 7 5 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX – ...
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... E1 stream in either the ingress or egress directions. The pseudo-random sequence can be inserted into the entire E1 or any combination of timeslots within the framed E1. PROPRIETARY AND CONFIDENTIAL ISSUE 7 6 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX – ...
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... Detects assertion and removal of tributary extended remote defect indications (RDI) for each tributary and optionally generates interrupts. PROPRIETARY AND CONFIDENTIAL ISSUE 7 7 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... Stuff control bits are dithered to produce fractional mapping jitter at the receiving desynchronizer. • Sets all fixed stuff bits for asynchronous mappings to zeros or ones per microprocessor control PROPRIETARY AND CONFIDENTIAL ISSUE 7 8 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... Frames to a DS3 signal with a maximum average reframe time of less than 1.5 ms (as required by TR-TSY-000009 Section 4.1.2 and TR-TSY-000191 Section 5.2). • Decodes a B3ZS-encoded signal and indicates line code violations. The definition of line code violation is software selectable. PROPRIETARY AND CONFIDENTIAL ISSUE 7 9 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... Provides optional automatic insertion of far end receive failure (FERF) on detection of loss of signal (LOS), out of frame (OOF), alarm indication signal (AIS) or red alarm condition. PROPRIETARY AND CONFIDENTIAL ISSUE 7 10 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX -3 bit error rate.Extracts ...
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... Allows DS2 alarm indication signal (AIS activated or cleared in the demultiplex direction automatically upon loss of DS3 frame alignment or signal. • Supports C-bit parity DS3 format. PROPRIETARY AND CONFIDENTIAL ISSUE 7 11 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... C-bits to be activated under microprocessor control. • Allows per tributary alarm indication signal (AIS activated or cleared for either direction under microprocessor control. PROPRIETARY AND CONFIDENTIAL ISSUE 7 12 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... T1s, 63 E1s or 3 DS3s, equivalent to three TEMUXs, with multiple payload or link layer processors. • External devices can access unframed DS3, framed unchannelized DS3, unframed (clear channel) T1s, framed T1s, unframed (clear channel) E1s, PROPRIETARY AND CONFIDENTIAL ISSUE 7 13 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... Transmit timing is mastered either by the TEMUX or a layer 2 device connecting to the SBI bus. Timing mastership is selectable on a per tributary basis, where a tributary is either an individual T1 DS3. PROPRIETARY AND CONFIDENTIAL ISSUE 7 14 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... SONET/SDH Add Drop Multiplexers • SONET/SDH Terminal Multiplexers • M23 Based M13 Multiplexer • C-Bit Parity Based M13 Multiplexer • Channelized and Unchannelized DS3 Frame Relay Interfaces PROPRIETARY AND CONFIDENTIAL ISSUE 7 15 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... Bell Communications Research - Wideband and Broadband Digital Cross- Connect Systems Generic Criteria, TR-NWT-000233, Issue 3, November 1993 • Bellcore GR-253-CORE – “SONET Transport Systems: Common Criteria,” Issue 2, Revision 1, December 1997. PROPRIETARY AND CONFIDENTIAL ISSUE 7 16 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... ITU-T - Recommendation G.704 - Synchronous Frame Structures Used at Primary Hierarchical Levels, July 1995. • ITU-T - Recommendation G.706 - Frame Alignment and CRC Procedures Relating to G.704 Frame Structures, 1991. PROPRIETARY AND CONFIDENTIAL ISSUE 7 17 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... ITU-T Recommendation Q.921 - ISDN User-Network Interface Data Link Layer Specification, March 1993 • International Organization for Standardization, ISO 3309:1984 - High-Level Data Link Control procedures - Frame Structure PROPRIETARY AND CONFIDENTIAL ISSUE 7 18 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... Nippon Telegraph and Telephone Corporation - Technical Reference for High- Speed Digital Leased Circuit Services, Third Edition, 1990. • GO-MVIP, Multi-Vendor Integration Protocol, MVIP-90, Release 1.1, 1994 • GO-MVIP, H-MVIP Standard, Release1.1a, 1997 PROPRIETARY AND CONFIDENTIAL ISSUE 7 19 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... M13 Mux, DS3 framer PM8315 TEMUX 28 T1/21 E1 Framer M13 Mux, DS3 framer PM8315 TEMUX 28 T1/21 E1 Framer M13 Mux, DS3 framer PM8315 TEMUX #3 PM8315 TEMUX #2 PM8315 TEMUX #1 in VT1.5 or VT2.0 Mapper Mode T1 Framer #28 … Framer #21 Mapper and Telecom Bus I Framer #1 ...
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... DS3 mapped into the SONET/SDH telecom bus. Unchannelized DS3 system side access is available through a serial clock and data interface or the SBI bus, both shown at the top of the diagram. PROPRIETARY AND CONFIDENTIAL ISSUE 7 21 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... STANDARD PRODUCT DATASHEET PMC-1981125 Figure 3 - TEMUX Block Diagram PROPRIETARY AND CONFIDENTIAL ISSUE 7 22 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... MUX/ Framer A ttenuator Extraction DEMUX Elastic One of Seven FRAM FRMR/M12s Framer RAM One Fram ers 23 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX XCLK CTCLK CM V8M CLK CM VFPB MVED [1:7] CASED[1: ESIF P er-DS 0 Egress CCSED ...
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... SIPO TTOP Transmit Serial to Transmit Tributary Parallel Remote Mapper Converter Alarm & Tributary PathO/H Processors 24 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX TJAT Digital Jitter Attenuator PMON ALMI Performance Alarm Monitor Integrator Counters T1/E1-FRMR Framer: Frame Alignment, ...
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... R x HDLC PROPRIETARY AND CONFIDENTIAL ISSUE TRAN DS3 Transm it Fram er FRM R DS3 R eceive Fram Perf. M onitor 25 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX TFP O/TMFPO /TG APC LK TFP I APCLK/RSCLK RD ATO RFPO /R MFPO RO VRHD ...
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... DATASHEET PMC-1981125 6 DESCRIPTION The PM8315 High Density T1/E1 Framer with Integrated VT/TU Mapper and M13 Multiplexer (TEMUX feature-rich device for use in any applications requiring high density link termination over T1 channelized DS3 or T1 and E1 channelized SONET/SDH facilities. The TEMUX supports asynchronous multiplexing and demultiplexing of 28 DS1s into a DS3 signal as specified by ANSI T1 ...
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... E1 basis. The TEMUX can generate a low jitter transmit clock from a variety of clock references, and also provides jitter attenuation in the receive path. Two low jitter PROPRIETARY AND CONFIDENTIAL ISSUE 7 27 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... OOF. The counters are intended to be polled once per second, and are sized so as not to saturate PROPRIETARY AND CONFIDENTIAL ISSUE 7 28 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX -3 bit error rate and detects ...
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... Tributary frequency deviations are accommodated using internal FIFOs and bit stuffing. The C-bits are set appropriately, with the option of inserting DS1 loopback requests. Interrupts can be generated upon detection of loopback PROPRIETARY AND CONFIDENTIAL ISSUE 7 29 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... The TEMUX is configured, controlled and monitored via a generic 8-bit microprocessor bus through which all internal registers are accessed. All sources of interrupts can be masked and acknowledged through the microprocessor interface. PROPRIETARY AND CONFIDENTIAL ISSUE 7 30 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Bottom View 31 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX VSS VSS VSS VSS VSS VSS ...
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... RCLK by default and may be enabled to be sampled on the falling edge of RCLK by setting the RFALL bit in the DS3 Master Receive Line Options register. circuitry downstream of the DS3 transmitter of the TEMUX. TCLK is nominally a 44.736 MHz, 50% duty cycle clock. 32 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... MHz, 50% duty cycle clock. This clock is only required when using the DS3 transmitter, either with the DS3 line side interface or the DS3 mapper. When not used this clock input should be connected to ground. 33 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... MHz ± 32ppm, 50% duty cycle clock when configured for E1 modes. This clock is required for all operating modes of the TEMUX. Test Vector Clock (VCLK). This signal is used during production testing. 34 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... Interface Options register. By default RDATO will be updated on the falling edge of RGAPCLK or RSCLK. This signal shares a signal pin with ID[1] and MVID[1]. This signal will be RDATO only when enabled for unchannelized DS3 operation. 35 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... RSCLK depending on the setting of the RSCLKR bit in the DS3 Master Unchannelized Interface Options register. This signal shares a signal pin with ID[2] and CASID[1]. This signal will be ROVRHD only when enabled for unchannelized DS3 operation. 36 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... TGAPCLK is used to sample TDATI and TFPI/TMFPI when TXGAPEN is set to 1. This signal shares a signal pin with ECLK[1]. When enabled for unchannelized DS3 operation this signal will be TFPO/TMFPO/TGAPCLK, otherwise it will be ECLK[1]. 37 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... TDATIFALL bit to 1in the DS3 Master Unchannelized Interface Options register. This signal shares a signal pin with ED[2] and CASED[1]. This signal will be TFPI/TMFPI only when enabled for unchannelized DS3 operation. 38 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... H19 CICLK. G19 E19 F21 In E1 mode only ICLK[1:21] and ISIG[1:21] are used ICLK[1]/ISIG[1] shares a pin with the DS3 system E3 interface signal RGAPCLK/RSCLK PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... IFP[1] shares a pin with the DS3 system interface K20 signal RFPO/RMFPO. IFP[20,27,28] shares pins with J19 the SBI interface signals SDDP, SDPL, SDV5 U19 R22 J22 J20 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... DS3 system interface signal RDATO. U2 ID[2] shares a pin with the DS3 system interface signal V4 ROVRHD. ID[15,16,19,20,23,24,27,28] shares pins D11 with the SBI interface bus SDDATA[7:0]. A11 M19 L19 D10 A10 J1 H4 B10 C10 41 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... CIFP a maximum of once every frame (nominally 193 or 256 bit times). CIFP is sampled on the active edge of CICLK as selected by the CIFE bit in the Master Common Ingress Serial and H-MVIP Interface Configuration register. 42 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... ED[x] are sampled on the active edge of CECLK. CECLK is a nominal 1.544 or 2.048 MHz clock +/- 50ppm with a 50% duty cycle. This signal shares a pin with the H-MVIP signal CMV8MCLK. By default this input is CECLK. 43 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 59
... CEFE bit in the Master Common Egress Serial and H-MVIP Interface Configuration register. CEFP has no effect in the Clock Master egress modes. This signal shares a pin with the H-MVIP signal CMVFPB. By default this input is CEFP. 44 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... DS3 system interface signal C7 TDATI. ED[2] shares a pin with the DS3 system P2 interface signal TFPI/TMFPI. M1 ED[7,8,11,12,15,16,19,20,23,24,27,28] shares pins D4 with the SBI interface add bus signals. B6 C20 E22 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... CEFP. ESIG[x] is sampled on the active edge of CECLK. ECLK[1]/EFP[1]/ESIG[1] shares a pin with the DS3 system interface output signal TFPO/TMFPO/TGAPCLK. 46 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 62
... CMV8MCLK with no more than ±10ns skew. The H-MVIP interfaces are enabled via the SYSOPT[2:0] bits in the Global Configuration register. This signal shares a pin with CICLK. By default this input is CICLK. 47 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 63
... CMV8MCLK is selected via the CMVIDE bit in the Master Common Ingress Serial and H-MVIP Interface Configuration register mode only MVID[1:6] are used. MVID[1:7] shares the same pins as ID[1,5,9,13,17,21,25]. 48 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... CMV8MCLK as fixed by the common MVIP frame pulse clock, CMVFPC. The updating edge of CMV8MCLK is selected via the CMVIDE bit in the Master Common Ingress Serial and H-MVIP Interface Configuration register. 49 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 65
... MVIP frame pulse clock, CMVFPC. The sampling edge of CMV8MCLK is selected via the CMVEDE bit in the Master Common Ingress Serial and H-MVIP Interface Configuration register. CASED[1:7] shares the same pins as ED[2,6,10,14,18,22,26]. 50 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... LAOE are updated on the rising edge of LREFCLK. This clock is nominally a 19.44MHz +/-20ppm clock with a 50% duty cycle. This clock can be external connected to SREFCLK. When in Transparent VT mode this clock must be connected to SREFCLK. 51 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 67
... All devices must be configured via the LOCK0 bits in the Master SONET/SDH Configuration and TTMP Telecom Interface Configuartion registers for the same J1 location corresponding to a pointer offset 522. LAC1J1V1 is updated on the rising edge of LREFCLK. 52 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 68
... LADATA[7:0] is only asserted during the SONET/SDH tributaries assigned to this device as determined by the LAOE bit in the TTMP Tributary Control registers. LADATA[7:0] is updated on the rising edge of LREFCLK. 53 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 69
... W14 byte serial format. LDDATA[7] is the most significant AB14 bit, corresponding to bit 1 of each serial word, the bit W15 transmitted first. W16 LDDATA[7:0] is sampled on the rising edge of AB15 LREFCLK. W17 54 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 70
... LDPL is set high during the H3 byte to indicate a negative pointer justification and low during the byte following H3 to indicate a positive pointer justification event. LDPL is sampled on the rising edge of LREFCLK. 55 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 71
... It is nominally a 9.72 MHz clock, but can range from 1.344 MHz to 10 MHz. Inputs RADEASTFP and RADEAST are sampled on the rising edge of RADEASTCK. 56 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 72
... It is nominally a 9.72 MHz clock, but can range from 1.344 MHz to 10 MHz. Inputs RADWESTFP and RADWEST are sampled on the rising edge of RADWESTCK. 57 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 73
... DS3 from the SBI bus interface. This clock has two nominal values. The first is a nominal 51.84MHz 50% duty cycle clock. The second is a nominal 44.928MHz 50% duty cycle clock. When this clock is not used this input must be connected to ground. 58 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 74
... SREFCLK. It normally indicates SBI mutiframe alignment by pulsing high once every 9720 SREFCLK cycles. In synchronous SBI mode, however, SC1FP is used to indicate T1/E1 signaling multiframe alignment by pulsing once every 12 SBI mutiframes (48 T1/E1 frames or 116640 SREFCLK cycles). 59 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 75
... SBI bus structure. The TEMUX only monitors the add bus payload active signal during the tributary timeslots assigned to this device. SAPL is sampled on the rising edge of SREFCLK. This signal shares a pin with signal ED[12]. 60 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 76
... octet of the next multi-frame. The TEMUX only drives the justification request signal during the tributary timeslots assigned to this device. SAJUST_REQ is updated on the rising edge of SREFCLK. 61 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 77
... SBI bus structure. The TEMUX only drives the payload active signal during the tributary timeslots assigned to this device. SDPL is updated on the rising edge of SREFCLK. This signal shares a pin with IFP[27]. 62 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 78
... SBIACT. When collisions occur the SBI drivers are disabled and an interrupt is generated to signal the collision. These signals are sampled on the rising edge of SREFCLK. SBIDET[1] is shared with serial interface signal ED[7]. 63 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 79
... A18 A19 A20 C18 B19 B20 A21 C19 B21 A22 Active Low Reset (RSTB). This signal provides an asynchronous TEMUX reset. RSTB is a Schmitt triggered input with an integral pull up resistor. 64 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 80
... AA2 TEMUX Mode Select (TEMUXSELB). The TEMUX Mode Select pin is used for internal testing and must be connected to ground for proper operation. TEMUXSELB has an integral pull up resistor A1 No Connect. These pins are not connected to any B2 internal logic. 65 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 81
... C12 AA9 AA14 Y18 U20 M21 F20 C17 B11 D5 Power (VDD2.5[8:1]). The VDD2.5[8:1] pins should R2 be connected to a well-decoupled +2.5V DC power AA8 supply. AA15 R21 H21 A15 C9 66 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 82
... E21 B18 D15 C11 B8 C6 Ground (VSSQ[4:1]). The VSSQ[4:1] pins should be Y12 connected to GND. L20 B12 J3 Ground (VSS2.5[8:1]). The VSS2.5[8:1] pins should R3 be connected to GND. Y8 Y15 R20 H20 B15 B9 67 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 83
... J12 conductivity. J11 J10 J9 K14 K13 K12 K11 K10 K9 L14 L13 L12 L11 L10 L9 M14 M13 M12 M11 M10 M9 N14 N13 N12 N11 N10 N9 P14 P13 P12 P11 P10 P9 68 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 84
... Power to the VDD3.3 and VDDQ pins should be applied before power to the VDD2.5 pins is applied. Similarly, power to the VDD2.5 pins should be removed before power to the VDD3.3 and VDDQ pins are removed. 9. All TEMUX inputs are 5V tolerant. PROPRIETARY AND CONFIDENTIAL ISSUE 7 69 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 85
... PCM data is continuously monitored for CAS multiframe alignment pattern errors. The E1-FRMR also detects and indicates loss of basic frame, loss of CRC multiframe, and loss of CAS multiframe, based PROPRIETARY AND CONFIDENTIAL ISSUE 7 70 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 86
... Additionally, interrupts may be generated every frame, CRC submultiframe, CRC multiframe or signaling multiframe. Basic Frame Alignment Procedure The E1-FRMR searches for basic frame alignment using the algorithm defined in ITU-T Recommendation G.706 sections 4.1.2 and 4.2. PROPRIETARY AND CONFIDENTIAL ISSUE 7 71 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 87
... International bits (bit NFAS frames follow the CRC multiframe alignment pattern. Multiframe alignment is declared if at least two valid CRC PROPRIETARY AND CONFIDENTIAL ISSUE 7 72 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX -3 bit error rate. The ...
Page 88
... CRC-4 multiframe alignment within the subsequent 400 ms, the distant end is assumed non CRC-4 interface. The details of this algorithm are illustrated in the state diagram in Figure 8. PROPRIETARY AND CONFIDENTIAL ISSUE 7 73 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 89
... BFA_Par 8m s expire and NOT( 400 ms exp ire FA_ Par CRCto non-C RC Interworking CR CM FA_ Par (Op tional setting) 74 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX NF AS not found nex t fram not found nex t fram e Start 8ms timer ...
Page 90
... CRC-to-non-CRC interworking. In this mode, the E1-FRMR may be PROPRIETARY AND CONFIDENTIAL ISSUE 7 Out of Frame Yes Yes Yes PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX Out of Offline Frame Yes Yes Yes No No ...
Page 91
... CAS multiframe alignment is also declared if basic frame alignment has been lost. National Bit Extraction The E1-FRMR extracts and assembles the submultiframe-aligned National bit codewords Sa4[1:4] , Sa5[1:4] , Sa6[1:4] , Sa7[1:4] and Sa8[1:4]. The PROPRIETARY AND CONFIDENTIAL ISSUE 7 -3 bit error rate. 76 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 92
... When the transfer clock signal is applied, the PMON transfers the counter values into PROPRIETARY AND CONFIDENTIAL ISSUE 7 77 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX -3 mean bit error rate. ...
Page 93
... The RDLC detects the change from flag characters to the first byte of data, removes stuffed zeros on the incoming data stream, receives packet data, and calculates the CRC-CCITT frame check sequence (FCS). PROPRIETARY AND CONFIDENTIAL ISSUE 7 Th code (111111) is similar to the 78 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 94
... Alarm indication is provided through internal register bits. PROPRIETARY AND CONFIDENTIAL ISSUE 7 79 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX -3 bit error rate. ...
Page 95
... There are two additional elastic stores used to adapt the differences in rate between the CAS or CCS H-MVIP signaling rates and the serial clock and data or SBI data rates when in simultaneous SBI or serial clock and data with PROPRIETARY AND CONFIDENTIAL ISSUE 7 80 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 96
... The SIGX block provides one superframe or signaling-multiframe of signal freezing on the occurrence of slips. When a slip event occurs, the SIGX freezes PROPRIETARY AND CONFIDENTIAL ISSUE 7 81 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 97
... Transmit Framing and Bypass Options register. When transmitting ESF formatted data, the framing bit, datalink bit, or the CRC-6 bit from the egress stream can be by-passed to the output data stream via the same T1/E1 Transmit PROPRIETARY AND CONFIDENTIAL ISSUE 7 82 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 98
... When enabled, the Signaling Aligner is positioned in the egress path before the T1-XBAS. Its purpose is to ensure that if the signaling on ESIG[x] is changed in the middle of a superframe, the XBAS completes transmitting the A,B,C, and D PROPRIETARY AND CONFIDENTIAL ISSUE 7 83 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 99
... The default procedure provides automatic transmission of data once a complete packet is written. All complete packets of data will be transmitted. After the last data byte of a packet, the CRC word (if CRC insertion has been enabled) and a PROPRIETARY AND CONFIDENTIAL ISSUE 7 84 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 100
... The performance report takes precedence over incompletely written packets, but it does not pre-empt packets already being transmitted. See the Operation section for details on the performance report encoding. PROPRIETARY AND CONFIDENTIAL ISSUE 7 85 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 101
... The divisors are set using the TJAT and RJAT Jitter Attenuator Divider N1 and N2 registers. The following formula must be met in order to select the values of N1 and N2: Fin/( Fout/( PROPRIETARY AND CONFIDENTIAL ISSUE 7 86 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 102
... II customer interface given in ANSI T1.403 to be met. The DJAT meets the E1 jitter attenuation requirements of the ITU-T Recommendations G.737, G.738, G.739 and G.742. PROPRIETARY AND CONFIDENTIAL ISSUE 7 87 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 103
... XCLK divided by 24 and that of the input data clock. Figure 9 - DJAT Jitter Tolerance T1 Modes 100 28 10 Jitter Amplitude, UIpp 1.0 0.1 0.01 1 PROPRIETARY AND CONFIDENTIAL ISSUE 7 10 4.9 100 0.3k Jitter Frequency PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX DJAT minimum tolerance acceptable unacceptable 1k 10k 29 0.2 100k ...
Page 104
... An XCLK input accuracy of ±100 ppm is only acceptable if an accurate line rate reference is provided. If TJAT is left to free-run without a reference, or referenced to a derivative of XCLK, then XCLK accuracy must be ±32 ppm. PROPRIETARY AND CONFIDENTIAL ISSUE 7 89 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 105
... Jitter PROPRIETARY AND CONFIDENTIAL ISSUE 7 200 250 100 200 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX 300 354 Hz 100 ± ppm 42.4 39 34.9 300 308 Hz 100 ± ...
Page 106
... Jitter frequencies above 8.8 Hz are attenuated at a level per octave, as shown in Figure 14. PROPRIETARY AND CONFIDENTIAL ISSUE 7 62411 max DJAT response 10 100 6.6 Jitter Frequency PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX 43802 max 1k 10k ...
Page 107
... TJAT block, the reference clock for the TJAT digital PLL, and the clock source used to derive the transmit clock to the M13 mux or SONET/SDH mapper. PROPRIETARY AND CONFIDENTIAL ISSUE 7 92 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 108
... The DS3 Framer (DS3-FRMR) Block integrates circuitry required for decoding a B3ZS-encoded signal and framing to the resulting DS3 bit stream. The DS3-FRMR is directly compatible with the M23 and C-bit parity DS3 applications. PROPRIETARY AND CONFIDENTIAL ISSUE 7 93 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 109
... M-frame intervals. For the RED alarm, an M-frame is said "valid" interval if it contains a RED defect, defined as an occurrence of an OOF or LOS event during that M-frame. For AIS and IDLE, an M-frame PROPRIETARY AND CONFIDENTIAL ISSUE 7 94 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 110
... Parity FEBE upon detection of receive C-bit parity error. The DS3-FRMR may be configured to generate interrupts on error events or status changes. All sources of interrupts can be masked or acknowledged via PROPRIETARY AND CONFIDENTIAL ISSUE 7 95 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX -3 bit error rate. For AIS, ...
Page 111
... The DS3 Transmitter (DS3-TRAN) Block integrates circuitry required to insert the overhead bits into a DS3 bit stream and produce a B3ZS-encoded signal. The T3-TRAN is directly compatible with the M23 and C-bit parity DS3 formats. PROPRIETARY AND CONFIDENTIAL ISSUE 7 96 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 112
... DS2 payload loopback requests encoded in the C-bits. As per ANSI T1.107a Section 8.2.1 and TR-TSY-000009 Section 3.7, the loopback command is identified as C3 being the inverse of C1 and C2. Because TR-TSY- PROPRIETARY AND CONFIDENTIAL ISSUE 7 97 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 113
... DS2 format and in 6.9 ms for G.747 format. The framer employs a simple integration algorithm (with a 1:1 slope) that is based on the occurrence of "valid" DS2 M-frame or G.747 frame intervals. For the RED alarm, a DS2 M- PROPRIETARY AND CONFIDENTIAL ISSUE 7 98 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 114
... The DS2 FRMR may be configured to generate interrupts on error events or status changes. All sources of interrupts can be masked or acknowledged via internal registers. Internal registers are also used to configure the DS2 FRMR. PROPRIETARY AND CONFIDENTIAL ISSUE 7 99 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 115
... Remote Alarm Indication (RAI), high speed signal AIS, and the reserved bit. A diagnostic option is provided to invert the transmitted frame alignment signal and parity bit. PROPRIETARY AND CONFIDENTIAL ISSUE 7 100 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 116
... The identification of specific tributaries allows the pointer interpreter to be time-sliced across the mix of tributaries present in the incoming data stream. The identification of the V1-V3 bytes of VTs, or TUs allows the pointer interpreter to function. PROPRIETARY AND CONFIDENTIAL ISSUE 7 101 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 117
... FIFO buffer is provided for each of the (up to 28) tributaries. Address information is also passed through the payload buffer to allow FIFO fill status to be determined by the pointer generator. PROPRIETARY AND CONFIDENTIAL ISSUE 7 102 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 118
... TUG3 to be all-zeros or all-ones also possible to force an inverted new data flag on individual tributaries for the purpose of diagnosing downstream pointer processors. Tributary path AIS is automatically inserted into outgoing tributaries PROPRIETARY AND CONFIDENTIAL ISSUE 7 103 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 119
... The error monitor block contains a set of 12-bit counters that are used to accumulate tributary path BIP-2 errors, and a set of 11-bit counters to accumulate far end block errors (FEBE). PROPRIETARY AND CONFIDENTIAL ISSUE 7 104 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 120
... PDI Code XXX ≠ 000, 001, PDI Code 000 001 PDI Code XXX ≠ 000, 001, PDI Code 000 105 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX PSLM State UNEQ State (Unequipped) Match Inactive Mismatch Inactive ...
Page 121
... PROPRIETARY AND CONFIDENTIAL ISSUE 7 Accepted PSL 001 PDI Code XXX ≠ 000, 001, PDI Code 000 001 XXX YYY 106 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX PSLM State UNEQ State (Unequipped) Match Inactive Match Inactive Mismatch ...
Page 122
... I: T1 payload information Table 4 - Asynchronous E1 Tributary Mapping bytes - OOOORR bytes – OOOORR bytes – RRRRRS 1 2 PROPRIETARY AND CONFIDENTIAL ISSUE 107 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 123
... Parallel In to Serial Out Converter (PISO) The Parallel In to Serial Out Converter (PISO) serializes tributaries which have been demapped from the STS-1 SPE or STM-1AU3 or PROPRIETARY AND CONFIDENTIAL ISSUE 7 108 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 124
... PROPRIETARY AND CONFIDENTIAL ISSUE 7 Slow T1 Overall Fast E1 Cycles T1 Cycles Cycles 468 771 456 772 444 773 109 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX Slow Overall E1 E1 Cycles Cycles 510 513 1023 520 504 1024 530 495 ...
Page 125
... CCRRRRRR CCRRRRRR CCRRRRRR CCRRRRRR 110 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX CCRROORS CCRROORS ...
Page 126
... (0) F ( (0) F (0) C ( ( (0) 111 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX (0) C (0) F (1) ...
Page 127
... DS3 AIS, faster and slower status. The faster pattern is used to drain the elastic store to avoid overflows. The slower pattern is used to allow the elastic store to fill to avoid underflows. PROPRIETARY AND CONFIDENTIAL ISSUE 7 112 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 128
... PROPRIETARY AND CONFIDENTIAL ISSUE 7 Run Faster 621 621 622 621 621 622 621 621 622 113 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX Run Slower 621 621 621 621 622 622 621 621 622 621 ...
Page 129
... RDI and Extended RDI. This selection is made on a per-tributary basis by setting the ERDI bits of the TRAP Control registers and the TTOP control registers. In Non-extended RDI mode, RDI indications are encoded as a one bit PROPRIETARY AND CONFIDENTIAL ISSUE 7 114 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 130
... The Tributary Mapper compensates for phase and frequency offsets using bit stuffing. A jitter-reducing control loop is used to monitor the Payload Buffer depth PROPRIETARY AND CONFIDENTIAL ISSUE 7 Non-extended RDI (ERDI=0) REI RDI 115 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX Extended RDI (ERDI=1) REI RDI RDI RFI NOT(RFI) ...
Page 131
... Fixed stuff bytes are used to fill the remaining bytes. Please refer to section 9.32 for a description of the DS3 mapping. 9.37.1 DS3 Mapper Serializer High speed serial data from the DS3-TRAN block is deserialized and written into the Elastic Store. PROPRIETARY AND CONFIDENTIAL ISSUE 7 116 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 132
... The 8kHz STS-1 (STM-0/AU3) frame interval is subdivided into 9 rows. Each row contains one stuff opportunity. Table 9 illustrates the stuffing implementation where S means stuff bit and I means an information bit (DS3 data). PROPRIETARY AND CONFIDENTIAL ISSUE 7 117 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 133
... H-MVIP interface all with PROPRIETARY AND CONFIDENTIAL ISSUE 7 Normal or DS3 AIS Run Faster 118 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX Run Slower ...
Page 134
... ISSUE 7 T1-XBAS/E1-TRAN BasicTransm itter: Fram e Gene ration, Alarm Insertio n, Signaling Insertion, Trunk Conditioning Line Coding 119 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX Receive CLK[1:28] T JAT Transmit C LK[1 :28] Digital PLL Transm it D ata[1 :28] TRANSM ITTER Receive CLK[1:28] ...
Page 135
... Trunk Conditioning Line Coding T1-XBAS/E1-TRAN BasicTransm itter: Frame Generation, Alarm Insertion, Signaling Insertion, Trunk Conditioning Line Coding 120 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX TRANSMITTER TJAT Digital PLL Transmit C LK[1:28] TJAT FIFO Transm it D ata[1:28] TRANSMITTER ...
Page 136
... PROPRIETARY AND CONFIDENTIAL ISSUE 7 T1-XBAS/E1-TRAN BasicTransm itte r: Frame Generation, Alarm Insertio n, Signaling Insertion, Trunk Co nditioning Line Coding 121 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX TRANSMITTER TJAT Transmit C LK[1:28] Digital PLL TJAT FIFO Transm it D ata[1:28] TRANSMITTER ...
Page 137
... When accessing the CAS or CCS signaling via the H-MVIP interface in parallel with the SBI interface a transmit signaling elastic store is used to adapt any timing differences between the data interface and the CAS or CCS H-MVIP interface. PROPRIETARY AND CONFIDENTIAL ISSUE 7 122 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 138
... H-MVIP CAS signals CASED[1:7]. PROPRIETARY AND CONFIDENTIAL ISSUE 7 T1-XBAS/E1-TRAN BasicTransmitter: Frame Generation, Alarm Insertion, Signaling Insertion, Trunk Conditioning Line Coding 123 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX TRANSMITTER TJAT Transmit CLK[1:28] Digital PLL TJAT FIFO Transmit Data[1:28] ...
Page 139
... ID[x] and the ingress frame alignment is indicated by PROPRIETARY AND CONFIDENTIAL ISSUE 7 FRAM Framer: Slip Bu ffer RAM FRM R Framer: Fram e Alignmen t, Alarm Extraction 124 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX RECEIVER RJAT Receive Data[1:28] Digita l Jitter Attenuator Receive CLK[1:28] ...
Page 140
... ICLK[ 1:28] PROPRIETARY AND CONFIDENTIAL ISSUE 7 FRAM Fram er: Slip Bu ffer RAM FRM R Framer: Fram e Alignmen t, Alarm Extraction 125 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX RECEIVER RJAT Receive Data[1:28] Digita l Jitter Attenuator Receive CLK[1:28] RECEIVER RJAT Receive Data[1:28] ...
Page 141
... ELST Elas tic FRAM Store Framer: Slip Bu ffer RA M FRMR Framer: Frame A lignmen t, Alarm Ext raction 126 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX RECEIVER RJAT Receive Data[1:28] Digita l Jitter Attenuator Receive CLK[1:28] RECEIVER RJAT Receive Data[1:28] ...
Page 142
... Data Interface with CCS H-MVIP Interface”, or the SBI Add bus when SYSOPT[2:0] is set to “SBI Interface with CAS or CCS H-MVIP Interface” and the ICCSSEL bit is set to 1. PROPRIETARY AND CONFIDENTIAL ISSUE 7 127 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 143
... MVIP data signals MVID[1:7]. ID[2,6,10,14,18,22,26] share pins with the H- PROPRIETARY AND CONFIDENTIAL ISSUE 7 ELST Elastic FRAM Store Framer: Slip Buffer RAM FRMR Framer: Frame Alignment, Alarm Extraction 128 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX RECEIVER RJAT Receive Data[1:28] Digital Jitter Attenuator Receive CLK[1:28] ...
Page 144
... Channelized T1s extracted from the SBI bus optionally have the channel associated signaling (CAS) bits explicitly defined and carried in parallel with the PROPRIETARY AND CONFIDENTIAL ISSUE 7 129 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 145
... SBI bus. In clock master mode the SBIPISO controls the bit rate by accepting data from the EXSBI at the rate of the individual T1 DS3 clocks sourced into it. PROPRIETARY AND CONFIDENTIAL ISSUE 7 130 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 146
... SBI Drop bus tristated. By default interrupts will not be enabled, automatic alarm generation is disabled, a dual rail DS3 LIU interface is expected and an external transmit reference clock is required. PROPRIETARY AND CONFIDENTIAL ISSUE 7 131 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 147
... Master Interrupt Status T1/E1 #17-24 0024H Master Interrupt Status T1 #25-28 0025H Master Interrupt Status SDH 0026H Master Interrupt Status Source SBI 0027H Reserved 0028H Master Interrupt Status DS3 PROPRIETARY AND CONFIDENTIAL ISSUE 7 132 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 148
... T1/E1 Interrupt Source #1 008CH T1/E1 Interrupt Source #2 008DH T1/E1 Diagnostics 008EH T1/E1 PRBS Positioning and HDLC Control 008FH Reserved 0090H RJAT Interrupt Status 0091H RJAT Reference Clock Divisor N1 Control PROPRIETARY AND CONFIDENTIAL ISSUE 7 133 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 149
... RPSC µP Access Status 00B2H RPSC Channel Indirect Address/Control 00B3H RPSC Channel Indirect Data Buffer 00B4H TPSC Configuration 00B5H TPSC µP Access Status 00B6H TPSC Channel Indirect Address/Control PROPRIETARY AND CONFIDENTIAL ISSUE 7 134 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 150
... TDPR Interrupt Status/UDR Clear 00CDH TDPR Transmit Data 00CEH- Reserved 00CFH 00D0H PRBS Generator/Checker Control 00D1H PRBS Checker Interrupt Enable/Status 00D2H PRBS Pattern Select 00D3H PRBS Reserved PROPRIETARY AND CONFIDENTIAL ISSUE 7 135 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 151
... T1 RBOC Code Status 00E8H T1 XBAS Configuration 00E9H T1 XBAS Alarm Transmit 00EAH- T1 XBAS Reserved 00EBH 00ECH T1 FRMR Configuration 00EDH T1 FRMR Interrupt Enable 00EEH T1 FRMR Interrupt Status PROPRIETARY AND CONFIDENTIAL ISSUE 7 136 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 152
... E1 FRMR National Bit Codewords 00EEH E1 FRMR Frame Pulse/Alarm Interrupt Enables 00EFH E1 FRMR Frame Pulse/Alarm Interrupt 00F0H E1 TRAN Configuration 00F1H E1 TRAN Transmit Alarm/Diagnostic Control 00F2H E1 TRAN International Control PROPRIETARY AND CONFIDENTIAL ISSUE 7 137 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 153
... T1/E1 Framer Slice #8 047FH 0480H- T1/E1 Framer Slice #9 04FFH 0500H- T1/E1 Framer Slice #10 057FH 0580H- T1/E1 Framer Slice #11 05FFH 0600H- T1/E1 Framer Slice #12 067FH 0680H- T1/E1 Framer Slice #13 06FFH PROPRIETARY AND CONFIDENTIAL ISSUE 7 138 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 154
... T1/E1 Master Ingress Parity and Alarm Enable 0B08H T1/E1 Master Egress Parity Enable 0B09H T1/E1 Master Serial Interface Configuration 0B0AH T1/E1 Transmit Framing and Bypass Options 0B0BH T1/E1 Interrupt Source #1 0B0CH T1/E1 Interrupt Source #2 PROPRIETARY AND CONFIDENTIAL ISSUE 7 139 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 155
... TXCI Egress Data Link Control 0B29H TXCI Egress Data Link Bit Select 0B2AH- TXCI Reserved 0B2FH 0B30H RPSC Configuration 0B31H RPSC µP Access Status PROPRIETARY AND CONFIDENTIAL ISSUE 7 140 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 156
... TDPR Configuration 0B49H TDPR Upper Transmit Threshold 0B4AH TDPR Lower Transmit Threshold 0B4BH TDPR Interrupt Enable 0B4CH TDPR Interrupt Status/UDR Clear 0B4DH TDPR Transmit Data PROPRIETARY AND CONFIDENTIAL ISSUE 7 141 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 157
... T1 ALMI Interrupt Status 0B63H T1 ALMI Alarm Detection Status 0B64H T1 XBOC Control 0B65H T1 XBOC Code 0B66H T1 RBOC Enable 0B67H T1 RBOC Code Status 0B68H T1 XBAS Configuration PROPRIETARY AND CONFIDENTIAL ISSUE 7 142 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 158
... T1 Framer Slice #23 0BFFH 0C00H- T1 Framer Slice #24 0C7FH 0C80H- T1 Framer Slice #25 0CFFH 0D00H- T1 Framer Slice #26 0D7FH 0D80H- T1 Framer Slice #27 0DFFH 0E00H- T1 Framer Slice #28 0E7FH 0E80H- Reserved 0FFFH PROPRIETARY AND CONFIDENTIAL ISSUE 7 143 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 159
... DS3 PMON Framing Bit Error Event Count MSB 1018H DS3 PMON Excessive Zeros LSB 1019H DS3 PMON Excessive Zeros MSB 101AH DS3 PMON Parity Error Event Count LSB PROPRIETARY AND CONFIDENTIAL ISSUE 7 144 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 160
... PRGD Control 1031H PRGD Interrupt Enable/Status 1032H PRGD Length 1033H PRGD Tap 1034H PRGD Error Insertion 1035H- PRGD Reserved 1037H 1038H PRGD Pattern Insertion Register #1 PROPRIETARY AND CONFIDENTIAL ISSUE 7 145 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 161
... DS2 FRMR #1 Interrupt Status 1063H DS2 FRMR #1 Status 1064H DS2 FRMR #1 Monitor Interrupt Enable/Status 1065H DS2 FRMR #1 FERR Count 1066H DS2 FRMR #1 PERR Count (LSB) PROPRIETARY AND CONFIDENTIAL ISSUE 7 146 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 162
... Reserved 109FH 10A0H- DS2 FRMR #3 Registers 10A7H 10A8H- Reserved 10AFH 10B0H- MX12 #3 Registers 10B7H 10B8H- Reserved 10BFH 10C0H- DS2 FRMR #4 Registers 10C7H 10C8H- Reserved 10CFH PROPRIETARY AND CONFIDENTIAL ISSUE 7 147 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 163
... MX12 #7 Registers 1137H 1138H- Reserved 11FFH 1200H- SONET/SDH Mapper and Demapper 16FFH 1200H SONET/SDH Master Configuration 1201H SONET/SDH Master Ingress Configuration 1202H SONET/SDH Master Egress Configuration PROPRIETARY AND CONFIDENTIAL ISSUE 7 148 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 164
... VTPP Ingress TUG2 #6, Configuration and Status 124BH VTPP Ingress TUG2 #6, Alarm Status 124CH VTPP Ingress TUG2 #7, Configuration and Status 124DH VTPP Ingress TUG2 #7, Alarm Status PROPRIETARY AND CONFIDENTIAL ISSUE 7 149 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 165
... RTDM TUG2 #7 of TUG3 #1, Control 1287H RTDM Reserved 1288H- RTDM TUG2 #1 to TUG#7 of TUG3 #1, Control 128EH 128FH RTDM Reserved 1290H- RTDM TUG2 #1 to TUG#7 of TUG3 #1, Control 1296H PROPRIETARY AND CONFIDENTIAL ISSUE 7 150 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 166
... RTOP TUG2 #1, Configuration and Alarm Status 1302H RTOP TUG2 #1, Expected Path Signal Label 1303H RTOP TUG2 #1, Accepted Path Signal Label 1304H RTOP TUG2 #1, BIP-2 Error Count LSB PROPRIETARY AND CONFIDENTIAL ISSUE 7 151 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 167
... RTOP TUG2 #2, Configuration and Status 134FH Registers 1350H- RTOP TUG2 #3, Configuration and Status 1357H Registers 1358H- RTOP TUG2 #4, Configuration and Status 135FH Registers PROPRIETARY AND CONFIDENTIAL ISSUE 7 152 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 168
... Registers 13B8H RTOP TUG2 #1 to TUG2 #7, COPSL Interrupt 13B9H RTOP TUG2 #1 to TUG2 #7, PSLM Interrupt 13BAH RTOP TUG2 #1 to TUG2 #7, PSLU Interrupt PROPRIETARY AND CONFIDENTIAL ISSUE 7 153 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 169
... RTOP Reserved 13FFH 1400H VTPP Egress TUG2 #1, Configuration and Status 1401H VTPP Egress TUG2 #1, Alarm Status 1402H VTPP Egress TUG2 #2, Configuration and Status PROPRIETARY AND CONFIDENTIAL ISSUE 7 154 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 170
... Configuration and Status/Alarm Status 143EH VTPP Egress TUG2 #1 to TUG2 #7, LOP Interrupt 143FH VTPP Egress TUG2 #1 to TUG2 #7, AIS Interrupt 1440H- Reserved 147FH PROPRIETARY AND CONFIDENTIAL ISSUE 7 155 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 171
... TRAP Indirect Remote Alarm Page Address 14E 1H TRAP Indirect Remote Alarm Tributary Address 14E2H TRAP Indirect Datapath Tributary Data 14E3H TRAP RDI Control 14E4H- TRAP Reserved 14E7H PROPRIETARY AND CONFIDENTIAL ISSUE 7 156 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 172
... TTOP TUG2 #1 to TUG2 #7 of TUG3 #1,BIP Diagnostic Control 1518H- TTOP TUG2 #1 to TUG#7 of TUG3 #1, Control 151EH 151FH TTOP TUG2 #1 to TUG2 #7 of TUG3 #1, BIP Diagnostic Control PROPRIETARY AND CONFIDENTIAL ISSUE 7 157 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 173
... Control 158FH Reserved 1590H- TTMP TUG2 #1 to TUG#7 of TUG3 #1, Tributary 1596H Control 1597H Reserved 1598H- TTMP TUG2 #1 to TUG#7 of TUG3 #1, Tributary 159EH Control PROPRIETARY AND CONFIDENTIAL ISSUE 7 158 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 174
... D3MD Interrupt Status 1642H D3MD Interrupt Enable 1643H Reserved 1644H D3MA Control 1645H D3MA Interrupt Status 1646H D3MA Interrupt Enable 1647H Reserved 1648H- Reserved 16FFH PROPRIETARY AND CONFIDENTIAL ISSUE 7 159 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 175
... INSBI Tributary Register Indirect Access Control 1725H INSBI Reserved 1726H INSBI Tributary Control Indirect Access Data 1727H- INSBI Reserved 172FH 1731H INSBI Depth Check Interrupt Status PROPRIETARY AND CONFIDENTIAL ISSUE 7 160 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 176
... INSBI Insert External ReSynch Interrupt Status 1733H- INSBI Reserved 173FH 1740H- SBI SIPO Reserved 175FH 1780H- SBI PISO Reserved 179FH 1780H- Reserved 1FFFH For all register accesses, CSB must be low. PROPRIETARY AND CONFIDENTIAL ISSUE 7 161 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 177
... Writing into read-only normal mode register bit locations does not affect TEMUX operation unless otherwise noted. The register descriptions are contained in a separate TEMUX register description document. PROPRIETARY AND CONFIDENTIAL ISSUE 7 162 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 178
... TX-ELST Test Registers 209FH 20A0H- RXCE Test Registers 20A7H 20A8H- TXCI Test Registers 20AFH 20B0H- RPSC Test Registers 20B3H 20B4H- TPSC Test Registers 20B7H PROPRIETARY AND CONFIDENTIAL ISSUE 7 163 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 179
... T1 APRM Test Registers 20F7H 20E0H- E1 FRMR Test Registers 20EFH 20F0H- E1 TRAN Test Registers 20F7H 20F8H- Reserved 20FFH 2100H- T1/E1 Framer Slice #2 217FH 2180H- T1/E1 Framer Slice #3 21FFH PROPRIETARY AND CONFIDENTIAL ISSUE 7 164 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 180
... T1/E1 Framer Slice #15 27FFH 2800H- T1/E1 Framer Slice #16 287FH 2880H- T1/E1 Framer Slice #17 28FFH 2900H- T1/E1 Framer Slice #18 297FH 2980H- T1/E1 Framer Slice #19 29FFH 2A00H- T1/E1 Framer Slice #20 2A7FH PROPRIETARY AND CONFIDENTIAL ISSUE 7 165 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 181
... DS3 FRMR Test Registers 300FH 3010H- DS3 PMON Test Registers 301FH 3020H- DS3 TDPR Test Registers 3027H 3028H- DS3 RDLC Test Registers 3029H 3030H- PRGD Test Registers 303FH PROPRIETARY AND CONFIDENTIAL ISSUE 7 166 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 182
... DS2 FRMR #3 Test Registers 30A7H 30A8H- Reserved 30AFH 30B0H- MX12 #3 Test Registers 30B7H 30B8H- Reserved 30BFH 30C0H- DS2 FRMR #4 Test Registers 30C7H 30C8H- Reserved 30CFH PROPRIETARY AND CONFIDENTIAL ISSUE 7 167 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 183
... Reserved 312FH 3130H- MX12 #7 Test Registers 3137H 3138H- Reserved 31FFH 3200H- SONET/SDH Mapper and Demapper 36FFH 3200H- Reserved 321F 3220H- PISO Test Registers 323FH PROPRIETARY AND CONFIDENTIAL ISSUE 7 168 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 184
... Reserved 370FH 3710H- EXSBI Test Registers 371FH 3720H- INSBI Test Registers 373FH 3740H- SBI SIPO Test Registers 375FH 3780H- SBI PISO Test Registers 379FH PROPRIETARY AND CONFIDENTIAL ISSUE 7 169 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 185
... Writeable register bits are not initialized upon reset unless otherwise noted. PROPRIETARY AND CONFIDENTIAL ISSUE 7 170 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 186
... When IOTST is a logic 1, all blocks are held in test mode and the microprocessor may write to a block's test mode 0 registers to PROPRIETARY AND CONFIDENTIAL ISSUE 7 Function Default Unused X Unused X Unused X PMCTST X DBCTRL X IOTST X HIZDATA X HIZIO X 171 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 187
... Identification SAMPLE Boundary Scan BYPASS Bypass BYPASS Bypass STCTEST Boundary Scan BYPASS Bypass BYPASS Bypass PROPRIETARY AND CONFIDENTIAL ISSUE 7 Instruction Code IR[2:0] 000 001 010 011 100 101 110 111 172 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 188
... PROPRIETARY AND CONFIDENTIAL ISSUE 7 32 bits 5H 8315H 0CDH 583150CDH Register Bit 173 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX Cell Type Device I.D. OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - IO_CELL - OUT_CELL - IO_CELL ...
Page 189
... PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX Cell Type Device I.D. IO_CELL - OUT_CELL - IO_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - ...
Page 190
... PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX Cell Type Device I.D. IN_CELL - IN_CELL - IN_CELL - OUT_CELL - OUT_CELL - IO_CELL - OUT_CELL - IO_CELL - OUT_CELL - IO_CELL - IN_CELL - OUT_CELL - ...
Page 191
... PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX Cell Type Device I.D. OUT_CELL - IN_CELL - OUT_CELL - IO_CELL - IN_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - IN_CELL - IN_CELL - IN_CELL - ...
Page 192
... PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX Cell Type Device I.D. OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL ...
Page 193
... PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX Cell Type Device I.D. IN_CELL - IN_CELL - IN_CELL - IN_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL ...
Page 194
... PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX Cell Type Device I.D. IO_CELL - OUT_CELL - IO_CELL - OUT_CELL - IO_CELL - OUT_CELL - IO_CELL - OUT_CELL ...
Page 195
... PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX Cell Type Device I.D. OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL - OUT_CELL ...
Page 196
... PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX Cell Type Device I.D. IN_CELL - IN_CELL - IN_CELL - IN_CELL - IN_CELL - IN_CELL - IN_CELL - IN_CELL ...
Page 197
... PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX Cell Type Device I.D. IO_CELL - OUT_CELL - IO_CELL - OUT_CELL - IO_CELL - OUT_CELL - OUT_CELL - OUT_CELL ...
Page 198
... PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX Cell Type Device I.D. OUT_CELL 0 OUT_CELL 1 OUT_CELL 0 IN_CELL 1 IN_CELL 0 IN_CELL 0 OUT_CELL 0 IO_CELL ...
Page 199
... STANDARD PRODUCT DATASHEET PMC-1981125 3. Enable cell HIZ, tristates all pins that do not have an individual pinname_OEN enable signal. PROPRIETARY AND CONFIDENTIAL ISSUE 7 184 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 200
... 185 PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX 84 bits 84 bits 84 bits ...