KM416C256DT-6 Samsung, KM416C256DT-6 Datasheet

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KM416C256DT-6

Manufacturer Part Number
KM416C256DT-6
Description
256K x 16Bit CMOS dynamic RAM with fast page mode, 60ns, 5V
Manufacturer
Samsung
Datasheet
1.KM416C256DT-5.pdf (8 pages)
¡Ü
KM416C256D, KM416V256D
This is a family of 262,144 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells
within the same row. Power supply voltage (+5.0V or +3.3V), access time (-5,-6,-7), power consumption(Normal or Low power) and
package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and
Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 256Kx16 fast page mode DRAM family is
fabricated using Samsung's advanced CMOS process to realize high band-width, low power consumption and high reliability.
It may be used as graphic memory unit for microcomputer, personal computer and portable machines.
FEATURES
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Speed
C256D
V256D
Performance Range:
Active Power Dissipation
Refresh Cycles
Part Identification
-5
-6
-7
Part
NO.
- KM416C256D/DL (5V, 512K Ref.)
- KM416V256D/DL (3.3V, 512K Ref.)
Speed
-5
-6
-7
50ns
60ns
70ns
t
RAC
3.3V
V
5V
CC
3.3V(512 Ref.)
15ns
15ns
20ns
t
CAC
256K x 16Bit CMOS Dynamic RAM with Fast Page Mode
Refresh
cycle
512K
325
290
-
130ns
90ns
10ns
t
RC
Normal
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
8ms
Refresh period
35ns
40ns
45ns
5V(512 Ref.)
t
PC
605
495
440
Unit : mW
128ms
5V/3.3V
5V/3.3V
Remark
5V only
L-ver
DESCRIPTION
UCAS
LCAS
RAS
W
A0
A8
.
.
FUNCTIONAL BLOCK DIAGRAM
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Triple +5V ¡¾ 10% power supply(5V product)
Triple +3.3V ¡¾ 0.3V power supply(3.3V product)
TSOP(II) 400mil packages
Fast Page Mode operation
Available in 40-pin SOJ 400mil and44(40)-pin
2 CAS Byte/Wrod Read/Write operation
CAS-before-RAS refresh capability
RAS-only and Hidden refresh capability
Self-refresh capability (L-ver only)
TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
Early Write or output enable controlled write
JEDEC Standard pinout
Control
Clocks
Row Address Buffer
Col. Address Buffer
Refresh Counter
Refresh Control
Refresh Timer
VBB Generator
Column Decoder
Row Decoder
Memory Array
262,144 x16
Cells
CMOS DRAM
Vcc
Vss
Data out
Data out
Data in
Data in
Lower
Buffer
Lower
Buffer
Upper
Buffer
Upper
Buffer
OE
DQ15
DQ0
DQ7
DQ8
to
to

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KM416C256DT-6 Summary of contents

Page 1

... Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 256Kx16 fast page mode DRAM family is fabricated using Samsung's advanced CMOS process to realize high band-width, low power consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal computer and portable machines. ...

Page 2

KM416C256D, KM416V256D KM416C/V256DJ ¡Ü DQ0 DQ1 DQ2 DQ3 V CC DQ4 DQ5 DQ6 DQ7 N.C N.C W RAS N PIN CONFIGURATION (Top Views ¡Û DQ15 3 ...

Page 3

KM416C256D, KM416V256D ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative Voltage on V supply relative Storage Temperature Power Dissipation Short Circuit Output Current * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" ...

Page 4

KM416C256D, KM416V256D DC AND OPERATING CHARACTERISTICS Symbol Power I Don't care CC1 I Don't care Don't care CC2 I Don't care CC3 I Don't care CC4 Normal I Don't care CC5 L I Don't care CC6 I L Don't care ...

Page 5

KM416C256D, KM416V256D CAPACITANCE =25 ¡É Parameter Input capacitance [A0 ~ A8] Input capacitance [RAS, UCAS, LCAS, W, OE] Output capacitance [DQ0 - DQ15] (0 ¡É¡Â CHARACTERISTICS =5.0V ¡¾ 10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V Test condition (5V ...

Page 6

KM416C256D, KM416V256D AC CHARACTERISTICS (Continued) Parameter Data set-up time Data hold time Refresh period (Normal) Refresh period (L-ver) CAS to W delay time RAS to W delay time Column address to W delay time CAS precharge to W delay time ...

Page 7

KM416C256D, KM416V256D NOTES An initial pause of 200us is required after power-up followed by any 8 ROR or CBR cycles before proper device operation is 1. achieved. Input voltage levels are Vih/Vil Transition times are measured between V ...

Page 8

KM416C256D, KM416V256D 512cycle of burst refresh must be executed within 8ms before and after self refresh in order to meet refresh specification (L- 11. version). 12. tASC, tCAH are referenced to the earlier CAS rising edge. 13. tCP is specified ...

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