CY7C372I-83JC Cypress Semiconductor Corporation., CY7C372I-83JC Datasheet
CY7C372I-83JC
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CY7C372I-83JC Summary of contents
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Features • 64 macrocells in four logic blocks • 64 I/O pins • 5 dedicated inputs including 4 clock pins • In-System Reprogrammable™ (ISR™) Flash technology — JTAG interface • Bus Hold capabilities on all I/Os and dedicated inputs • ...
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Pin Configurations I/O I/O I/O /SCLK 10 I/O I/O I/O I/O I/O CLK V CCIO GND CLK I/O I/O I/O I/O I/O I/O I/O I/O GND 1 SCLK GND I/O ...
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Functional Description The 64 macrocells in the CY7C373i are divided between four logic blocks. Each logic block includes 16 macrocells product term array, and an intelligent product term allocator. The logic blocks in the F 370i ...
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Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ...................................–65°C to +150°C Ambient Temperature with Power Applied...............................................–55°C to +125°C Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC Voltage Applied ...
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Capacitance Parameter Description [9] C Input Capacitance IN C Clock Signal Capacitance CLK [7] Inductance Parameter Description L Maximum Pin Inductance [7] Endurance Characteristics Parameter Description N Maximum Reprogramming Cycles AC Test Loads and Waveforms 238Ω (COM'L) 5V OUTPUT ...
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Switching Characteristics Over the Operating Range Parameter Description Combinatorial Mode Parameters t Input to Combinatorial Output PD t Input to Output Through Transparent Input or PDL [1] Output Latch t Input to Output Through Transparent Input and PDLL [1] Output ...
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Switching Characteristics Over the Operating Range Parameter Description Pipelined Mode Parameters t Input Register Clock to Output Register Clock ICS f Maximum Frequency in Pipelined Mode (Least MAX4 of 1/( 1/t , 1/( ICS [7] ...
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Switching Waveforms (continued) Latched Output INPUT LATCH ENABLE LATCHED OUTPUT Clock to Clock REGISTERED INPUT INPUT REGISTER CLOCK OUTPUT REGISTER CLOCK Latched Input LATCHED INPUT LATCH ENABLE COMBINATORIAL OUTPUT LATCH ENABLE Document #: 38-03030 Rev. *A USE ULTRA37000 TM FOR ...
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Switching Waveforms (continued) Latched Input and Output LATCHED INPUT LATCHED OUTPUT INPUT LATCH ENABLE OUTPUT LATCH ENABLE LATCH ENABLE Asynchronous Reset INPUT REGISTERED OUTPUT CLOCK Asynchronous Preset INPUT REGISTERED OUTPUT CLOCK Document #: 38-03030 Rev. *A USE ULTRA37000 TM FOR ...
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Switching Waveforms (continued) Output Enable/Disable INPUT OUTPUTS Ordering Information Speed (MHz) Ordering Code 125 CY7C373i–125AC CY7C373i–125JC 100 CY7C373i–100AC CY7C373i–100JC CY7C373i–100AI CY7C373i–100JI 83 CY7C373i–83AC CY7C373i–83JC CY7C373i–83AI CY7C373i–83JI CY7C373iL–83JC 66 CY7C373i–66AC CY7C373i–66JC CY7C373i–66AI CY7C373i–66JI CY7C373iL–66JC Document #: 38-03030 Rev. *A USE ULTRA37000 ...
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... Package Diagrams 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 Warp is a registered trademark and Ultra37000, F are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-03030 Rev. *A © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product ...
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Document History Page Document Title: CY7C373i UltraLogic™ 64-Macrocell Flash CPLD Document Number: 38-03030 REV. ECN NO. Issue Date ** 106375 09/17/01 *A 213375 See ECN Document #: 38-03030 Rev. *A USE ULTRA37000 TM FOR ALL NEW DESIGNS Orig. of Change ...