ST70135 STMicroelectronics, ST70135 Datasheet
ST70135
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ST70135 Summary of contents
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... ANSI T1.413 ”Issue 2” DMT ADSL specification. The chip supports UTOPIA level 1 and UTOPIA level 2 interface and a non ATM synchronous bit-stream interface. The ST70135A can be split up into two different sections. The DMT modulation, demodulation, Reed-Solomon encoding, bit interleaving and 4D trellis coding. ...
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... ST70135A Figure 1 : Block Diagram TEST SIGNALS TEST MODULE DSP AFE INTERFACE FRONT-END AFE CONTROL AFE INTERFACE CONTROL TRANSIENT ENERGY CAPABILITIES ESD ESD (Electronic Discharged) tests have been performed for the Human Body Model (HBM) and for the Charged Device Model (CDM). The pins of ...
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... ST70135A ST70135A 108 VDD 107 SLT_REQ_F 106 SLT_DAT_S0 105 SLT_DAT_S1 104 SLT_DAT_F0 103 SLT_DAT_F1 102 VSS 101 SLT_FRAME_F SLAT_CLOCK 100 ...
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... ST70135A PIN FUNCTIONS Pin Name Type Supply 1 VSS 2 AD_0 B VDD 3 AD_1 B VDD 4 AD_2 B VDD 5 VDD 6 AD_3 B VDD 7 AD_4 B VDD 8 VSS 9 AD_5 B VDD 10 AD_6 B VDD 11 VDD 12 AD_7 B VDD 13 AD_8 B VDD 14 AD_9 B VDD 15 VSS 16 AD_10 B VDD 17 AD_11 B VDD 18 VDD 19 AD_12 B VDD 20 VSS 21 PCLK ...
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... ATM device (VSS + 3.3V) Power Supply IBUF Utopia RX Clock BD8SCR Utopia RX Start of Cell BD8SCR Utopia RX Cell Available IBUF Utopia RX Enable 0V Ground IBUF Utopia TX Clock IBUF Utopia TX Start of Cell BD8SCR Utopia TX Cell Available IBUF Utopia TX Enable (VSS + 3.3V) Power Supply ST70135A 5/29 ...
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... ST70135A PIN FUNCTIONS (continued) Pin Name Type Supply 73 VSS 74 U_TxData_7 I VDD 75 U_TxData_6 I VDD 76 VDD 77 U_TxData_5 I VDD 78 U_TxData_4 I VDD 79 U_TxData_3 I VDD 80 U_TxData_2 I VDD 81 VDD 82 U_TxData_1 I VDD 83 U_TxData_0 I VDD 84 U_TxADDR_4 I VDD 85 U_TxADDR_3 I VDD 86 VDD 87 U_TxADDR_2 I VDD 88 U_TxADDR_1 I VDD 89 U_TxADDR_0 I VDD 90 SLR_ FRAME_F O VDD ...
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... Transmit echo nibble 0V Ground BT4CR O Transmit echo nibble BT4CR O Transmit echo nibble (VSS + 3.3V) Power Supply IBUF none Test pin, active high BT4CR O Transmit data nibble BT4CR O Transmit data nibble 0V Ground BT4CR O Transmit data nibble BT4CR O Transmit data nibble (VSS + 3.3V) Power Supply ST70135A 7/29 ...
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... ST70135A I/O DRIVER FUNCTION Driver BD4CR CMOS bidirectional, 4mA, slew rate control BD8SCR CMOS bidirectional, 8mA, slew rate control, Schmitt trigger IBUF CMOS input IBUFDQ CMOS input, pull down, IDDq control IBUFUQ CMOS input, pull up, IDDq control PIN SUMMARY Mnemonic Type Power Supply ...
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... ATM device I 1 8kHz reference clock from ATM device General purpose input O 1 General purpose output I I Hard reset none none Enable scan test mode none none Test pin, active high ST70135A Function 9/29 ...
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... ST70135A I = Input, CMOS levels I-PU = Input with pull-up resistance, CMOS levels I-PD = Input with pull-down CMOS levels I-TTL = Input TTL levels O = Push-pull output OZ = Push-pull output with high-impedance state IO = Input / Tristate Push-pull output BS cell = Boundary-Scan cell I = Input cell O = Output cell B = Bidirectional cell C = Clock Main Block Description The following drawings describe the sequence of functions performed by the chip ...
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... FFT to a block of bits. This means to identify a point QAM constellation plane. The Demapper supports Trellis coded demodulation and provides a Viterbi maximum likelihood estimator. When the Trellis is active, the Demapper receives an indication for the most likely constellation subset to be used. ST70135A To/From TC 11/29 ...
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... ST70135A In the transmit direction, the mapper receives a bit stream from the Trellis encoder and modulates the bit stream on a set of carriers (up to 256). It generates coordinates for 2n QAM constellation, where n < 15 for all carriers. The Mapper performs the inverse operation, mapping a block of bits into one constellation point (in a complex x+jy representation) which is passed to the IFFT block ...
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... SLAP (Synchronous Link Access Protocol) interface. Only one type of interface can be enabled in a specific configuration. BER CELL INSERTION/ HEC FILTER To Interface Module CELL INSERTION/ HEC FILTER BER SLAP LEVEL UTOPIA 1 LEVEL UTOPIA 2 LEVEL UTOPIA 1 LEVEL UTOPIA 2 SLAP ST70135A 13/29 ...
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... A0 is always zero value. The interrupt request pin to the processor is INTB, and is an Open Drain output. The ST70135A supports both little and big endian. The default feature is big endian. Figure 9 : ST70135A Interfaces and ...
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... Master clock Timing T alew ale2Z Trd2cs T avs T avh T T wr2d dvh T wdvd T csrd T wrw T csrs T T csre rdy2dr Minimum Typical 1/2Tmclk - -10 ST70135A T mclk Maximum Unit 900 Tmclk 15/29 ...
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... Utopia Level 2 – Bitstream based on a proprietary exchange The interface selection is programmed by writing the Utopia PHY address register. Only one interface can be enabled in a ST70135A configuration. Utopia Level 1 supports only one PHY device. Utopia Level 2 supports multi-PHY devices (See Utopia Level 2 specifications). ...
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... Note 1. Active low signal When RxEnb is asserted, the ST70135A reads data from its internal fifo and presents it on RxData and RxSOC on each low-to-high transition of RxClk, ie the ATM layer chip samples all RxData and RxSOC on the rising edge of RxSOC on the rising edge of RxClk. ...
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... ST70135A The ST70135A samples TxData and TxSOC signals on the rising edge of TxClk, if TxEnb is asserted. TxClk, RxClk, AC Electrical Characteristics Symbol Parameters Min F Clock frequency 1.5 Tc Clock duty cycle 40 Tj Clock peak to peak jitter Trf Clock rise fall time L Load TxData, TxSOC, AC Electrical Characteristics ...
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... TxClav and 1 RxClav”. PHY Device Identification The ST70135A holds 2 PHY layer Utopia ports, one is dedicated to the fast data channel, the other one to the interleaved data channel. The associated PHY address is specified by the PHY_ADDR_x fields in the Utopia PHY address register ...
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... ST70135A Beware that an incorrect address configuration may lead to bus conflicts. A feature is defined to disable (tri-state) all outputs of the Utopia interface enabled by the TRI_STATE_EN bit in the Rx_interface control register. Pin Description Utopia 2 (Receive Interface) Name Type Meaning RxClav O Receive Cell available RxEnb* ...
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... SLAP (Synchronous Link Access Protocol) Interface The SLAP interface is a point to point bitstream interface. The ST70135A is the bus master of the interface. The interface is synchronous, a common clock (SLAP_CLOCK) is used. The basic idea is illustrated in Figure 17. The SLAP interface dumps the data of the fast and interleaved channels on 2 separate sub interfaces ...
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... ST70135A The implementation must guarantee that all active SLR_Valid signals must be separated by at least 8 clock cycles. Refer to Figure 20. The SLR_FRAME signals are asserted when the first pair of bits of a frame are transferred. For the fast channel a frame is defined as a superframe timebase. ...
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... CLWD AFRXD Cycle1 Cycle0 GP_IN(0) Test0 Test1 The ST70135A fetches the 16 bit word to be multiplexed on AFTXD from the Tx Digital Front-End module. Receive Interface The 16 bit receive word is multiplexed on 4 AFRXD input signals result 4 cycles are needed to transfer 1 word. Refer to Table 2 for the bit / pin allocation for the 4 cycles ...
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... ST70135A Figure 26 : Transmit Interface MCLK Tv AFTXD AFTXED Tc CLWD Figure 27 : Receive Interface MCLK Ts Th AFRXD Table 3 : Master Clock (MCLK) AC Electrical Characteristics Symbol Parameter F Clock Frequency Tper Clock Period Th Clock Duty Cycle Table 4 : AFTXD, AFTXED, CLWD AC Electrical Characteristics Symbol Parameter Tv Data Valid Time ...
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... U_RxCLAV B 66 U_RxENBB B 68 U_TxCLK B 69 U_TxSOC B 70 U_TxCLAV I 71 U_TxENBB B 74 U_TxData_7 B 75 U_TxData_6 B 77 U_TxData_5 I 78 U_TxData_4 C 79 U_TxData_3 I 80 U_TxData_2 I 82 U_TxData_1 O ST70135A Pin BS Type 25/29 ...
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... RW [2] Bits from are reserved Reset Initialization The ST70135A supports two reset modes: – A ’hardware’ reset is activated by the RESETB pin (active low). A hard reset occurs when a low input value is detected at the RESETB input. The low level must be applied for at least 1ms to none guarantee a correct reset operation ...
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... SCHMITx I = XmA* OUT I = XmA* 0. OUT DD Test Conditio n Minimum Typical 2.0 Slow edge < 1V/ s 0.9 Slow edge < 1V/ s 1.3 Slow edge < 1V XmA* OUT I = XmA* 2.4 OUT ST70135A Maximum Unit -125 mA 125 Maximum Unit 0 0 Maximum Unit 0.8 ...
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... ST70135A PQFP144 PACKAGE MECHANICAL DATA Figure 28 : Package Outline PQFP144 108 109 144 1 e Millimeter Dimension Minimum Typical A A1 0.25 A2 3.17 B 0.22 C 0.13 D 30.95 31.20 D1 27.90 28.00 D3 22. 30.95 31.20 E1 27.90 28.00 E3 22. 28/ PQFP144 Maximum Minimum 4.07 0.010 3.42 3.67 0.125 0.38 0.009 0.23 0.005 31.45 1.219 28.10 1.098 0.65 31.45 1.219 28.10 1.098 0.80 0.95 0.026 1.60 0 (minimum), 7 (maximum) ...
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... STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2000 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http ://www.st.com ST70135A 29/29 ...
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