IDT72261L12PF Integrated Device Technology, Inc., IDT72261L12PF Datasheet

IDT72261L12PF

Manufacturer Part Number

IDT72261L12PF

Description

CMOS supersync FIFO 16,384 x 9, 768 x 9

Manufacturer

Integrated Device Technology, Inc.

Datasheet

1.IDT72271L15PF.pdf (30 pages)

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FEATURES:

• 16,384 x 9-bit storage capacity (IDT72261)

• 32,768 x 9-bit storage capacity (IDT72271)

• 10ns read/write cycle time (8ns access time)

• Retransmit Capability

• Auto power down reduces power consumption

• Master Reset clears entire FIFO, Partial Reset clears

• Empty, Full and Half-full flags signal FIFO status

• Programmable Almost Empty and Almost Full flags, each

• Program partial flags by either serial or parallel means

• Select IDT Standard timing (using

• Easily expandable in depth and width

• Independent read and write clocks (permit simultaneous

• Available in the 64-pin Thin Quad Flat Pack (TQFP), 64-

• Output enable puts data outputs into high impedance

• High-performance submicron CMOS technology

• Industrial temperature range (-40

FUNCTIONAL BLOCK DIAGRAM

SuperSyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

1997 Integrated Device Technology, Inc

MRS

PRS

data, but retains programmable settings

flag can default to one of two preselected offsets

First Word Fall Through timing (using

reading and writing with one clock signal

pin Slim Thin Quad Flat Pack (STQFP) and the 68-pin

Pin Grid Array (PGA)

able, tested to military electrical specifications

Integrated Device Technology, Inc.

WRITE CONTROL

WRITE POINTER

WEN

RESET LOGIC

•

TIMING

LOGIC

WCLK

•

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

C to +85

•

and

CMOS SUPERSYNC FIFO

16,384 x 9, 32,768 x 9

and

C) is avail-

OUTPUT REGISTER

flags) or

INPUT REGISTER

RAM ARRAY

flags)

16,384 x 9

32,768 x 9

Q0-Q8

D0-D8

•

DESCRIPTION:

ity, high speed, low power first-in, first-out (FIFO) memories

with clocked read and write controls. These FIFOs are

applicable for a wide variety of data buffering needs, such as

optical disk controllers, local area networks (LANs), and inter-

processor communication.

port (Q

(WCLK) and a data input enable pin (

into the synchronous FIFO on every clock when

asserted. The output port is controlled by another clock pin

(RCLK) and enable pin (

the write clock for single clock operation or the two clocks can

run asynchronously for dual clock operation.

enable pin (

control of the outputs.

IDT Standard Mode , the first word written to the FIFO is

deposited into the memory array. A read operation is required

to access that word. In the First Word Fall Through Mode

(FWFT), the first word written to an empty FIFO appears

automatically on the outputs, no read operation required. The

The IDT72261/72271 are monolithic, CMOS, high capac-

Both FIFOs have a 9-bit input port (D

The IDT72261/72271 have two modes of operation: In the

). The input port is controlled by a free-running clock

) is provided on the read port for three-state

OFFSET REGISTER

REN

READ POINTER

). The read clock can be tied to

LOGIC

FLAG

CONTROL

•

LOGIC

READ

WEN

•

SEN

) and a 9-bit output

). Data is written

RCLK

IDT72261

IDT72271

REN

MAY 1997

PAF

PAE

FWFT/SI

An output

3036 drw 01

WEN

DSC-3036/6

Related parts for IDT72261L12PF

IDT72261L12PF Summary of contents

Page 1

... RESET LOGIC PRS TIMING FS SuperSyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. 1997 Integrated Device Technology, Inc CMOS SUPERSYNC FIFO ...

Page 2

IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 state of the FWFT/SI pin during Master Reset determines the mode in use. The IDT72261/72271 FIFOs have five flag functions, OR (Empty Flag or Output Ready), HF Ready), and (Half-full Flag). The ...

Page 3

IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 The Retransmit function allows the read pointer to be reset to the first location in the RAM array synchronized to RT RCLK when is LOW. This feature is convenient for ...

Page 4

IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 PIN DESCRIPTION Symbol Name D –D Data Inputs 0 8 MRS Master Reset PRS Partial Reset RT Retransmit FWFT/SI First Word Fall Through/Serial In WCLK Write Clock WEN Write Enable RCLK Read ...

Page 5

IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 ABSOLUTE MAXIMUM RATINGS Symbol Rating Commercial V Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 TERM with respect to GND T Operating 0 to +70 A Temperature T Temperature Under –55 to ...

Page 6

IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 ELECTRICAL CHARACTERISTICS (Commercial 10 +70 C; Military Symbol Parameter f Clock Cycle Frequency S t Data Access Time A t ...

Page 7

IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 SIGNAL DESCRIPTIONS: INPUTS: DATA Data inputs for 9-bit wide data. CONTROLS: MRS MRS MASTER RESET ( ) A Master Reset is accomplished whenever the Master ...

Page 8

IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 When goes LOW, Retransmit Setup is complete; at the same time, the contents of the first location are automatically displayed on the outputs. Since FWFT Mode is selected, the first word ...

Page 9

IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 SEN SEN SERIAL ENABLE ( ) SEN Serial Enable enable used only for serial programming of the offset registers. The serial programming method must be selected during ...

Page 10

IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 two pointers operate independently; however, a read and a write should not be performed simultaneously to the offset registers. A Master Reset initializes both pointers to the Empty Offset (LSB) register. A ...

Page 11

IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 equal to or less than the cycle period of the non-selected clock. The selected clock must be continuous. It is, however, permissible to stop the non-selected clock. Note, so long as EF ...

Page 12

IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 FWFT Mode, the Ouput Ready ( OR goes LOW at the same time that the first word written to an empty FIFO appears valid on the outputs. cycle after RCLK shifts ...

Page 13

IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 PAF LOW, then m = 07FH and the switching threshold is 127 LD words from the Full boundary, if PAF and the switching threshold is 1023 words away from the Full boundary. ...

Page 14

IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 MRS REN WEN t FWFT FWFT/SI LD (1) RT SEN PAE PAF MILITARY AND COMMERCIAL TEMPERATURE RANGES t RS ...

Page 15

IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 PRS REN WEN RT SEN PAE PAF RSS RSR t t RSS RSR t RSS ...

Page 16

IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 CLK t CLKH 1 WCLK WEN FF (1) t SKEW1 RCLK REN NOTES the minimum time between a rising RCLK edge and a ...

Page 17

IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 RCLK t t ENS REN OLZ OE WCLK WEN NOTES contributes a variable delay to the overall first ...

Page 18

IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 WCLK first valid write t ENS WEN t FWL1 RCLK EF REN NOTES max. (in ...

Page 19

IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 WRITE WCLK 1 (1) t SKEW1 WEN RCLK t ENH t ENS REN OE LOW DATA IN OUTPUT REGISTER 0 ...

Page 20

IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 WCLK t DS DATA WRITE ENH ENS WEN (1) t FWL1 RCLK EF REN OE LOW DATA IN OUTPUT REGISTER ...

Page 21

IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 WCLK t t ENS ENH SEN t t LDS LDH BIT 0 EMPTY OFFSET (LSB) Figure 11. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT modes) ...

Page 22

IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 CLK t t CLKH CLKL RCLK t LDS LD t ENS REN DATA IN OUTPUT REGISTER Figure 13. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT ...

Page 23

IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 CLKL t CLKH WCLK t t ENS ENH WEN PAF D - (m+1) words in FIFO memory RCLK REN NOTES: PAF 1. offset = 16,384 for IDT72261, 32,768 ...

Page 24

IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 WCLK ENH RTS ENS WEN RCLK t t ENS t ENH RTS REN ...

Page 25

IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES 25 ...

Page 26

IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES 26 ...

Page 27

IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 WCLK ENH RTS ENS WEN RCLK t t ENS t ENH RTS REN ...

Page 28

IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 OPERATING CONFIGURATIONS SINGLE DEVICE CONFIGURATION A single IDT72261/722171 may be used when the applica- WRITE CLOCK (WCLK) WRITE ENABLE ( FIRST WORD FALL THROUGH/SERIAL INPUT FULL FLAG/INPUT READY ( PROGRAMMABLE ALMOST FULL ...

Page 29

IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 PRS PARTIAL RESET ( ) MRS MASTER RESET ( ) FIRST WORD FALL THROUGH/ SERIAL INPUT (FWFT/SI) RT RETRANSMIT ( ) DATA IN (Dn) 18 WRITE CLOCK (WCLK) WRITE ENABLE ( LOAD ...

Page 30

IDT72261/72271 SyncFIFO 16,384 x 9, 32,768 x 9 where T is the RCLK period and T RCLK the WCLK period, whichever is shorter. The maximum amount of time it takes for a word to pass from the inputs of the ...

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