STV0299 STMicroelectronics, STV0299 Datasheet
STV0299
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STV0299 Summary of contents
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... LOCK WIDE RANGE APPLICATIONS LOOP DIGITAL SATELLITE AND SET-TOP BOXES DESCRIPTION The STV0299 Satellite Receiver with FEC is a RATE FROM CMOS single-chip multistandard demodulator for digital satellite broadcasting. It consists of two A/D converters for I-input and Q-input, a multistandard FOR QPSK and BPSK demodulator, and a forward error correction (FEC) unit having both an inner (Viterbi) and outer (Reed-Solomon) decoder ...
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... STV0299 TABLE OF CONTENTS 1 PIN INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 Pinout Description BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 SYSTEM CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 Front End Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 4.1 Interface and Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1.2 Write Operation (Normal Mode 4.1.3 Read Operation (Normal Mode 4.1 Interface in Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1.5 Specific Concerns about SCL Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 ...
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... TABLE OF CONTENTS (continued) 6.2 Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.4 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Characteristics APPLICATION BLOCK DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8 PACKAGE MECHANICAL DATA (CONTINUED STV0299 Page 3/36 ...
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... STV0299 1 PIN INFORMATION 1.1 Pin Connections Figure 1: Pinout for 64-pin TQFP (10x10 mm CLK_IN/XTAL_IN 1 XTAL_OUT 2 V SSA 3 V DDA 4 AUX_CLK AGC SDA 12 V DD_3 SCL 14 RESET 15 F22/DiSEqC 4/ ...
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... V S Ground 3.3 V Supply DD_3 2.5 V Supply DD RESET I Reset, active at low level STDBY I Power consumption reduction control pin DiSEqC modulation (22 kHz Tone), Programmable 2 F22/DiSEqC O Output Port 2 DAC Programmable Digital to Analog Converter Output O STV0299 Description 2 C bus bus 5/36 ...
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... STV0299 2 BLOCK DIAGRAM Nyquist & Interpolation Filter Derotator AGC1 AGC V Offset DDA Comp. V TOP IN/IP ADCs QN/QP V BOT V SSA CLK_IN/XTAL_IN Clock Generator AUX_CLK XTAL_OUT 22 kHz F22/DiSEqC Tone DiSEqC Interface SCL 2 I Interface SDA SDAT 3 SYSTEM CHARACTERISTICS Performances The following given parameters are for indication purposes only ...
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... The second AGC performs power optimization of the digital signal bandwidth (internal to the STV0299). The digital signal then passes through the digital carrier loop fitted with an on-chip derotator and tracking loop, lock detector, and digital timing recovery. ...
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... The Identification Register (at address Hex 00) gives the release number of the circuit. The content of this register at reset (presently Hex A1) will be modified in case of a new STV0299 release. In this case, the register at reset will become Hex A2. There are two possible ways to use this register, either by read only or read/write. ...
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... F22/ burst modulator DiSEqC 1/0 1/0 AUX_CLK 2 C bus register is forced to the status of pins STBY or f M_CLK divided by P: 000 4 001 6 010 8 011 12 100 16 101 24 110 32 111 48 Summary of F M_CLK -------------- TAL DIRCLK_CTRL = 0 = ----------- - DIRCLK_CTRL =1 CLK_IN = 0 STDBY = 1 STV0299 VCO 9/36 ...
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... Tuner Control Bus In low symbol rate applications, signal pollution generated by the SDA/SCL lines of the I may dramatically worsen tuner phase noise. In order to avoid this problem, the STV0299 offers bus repeater so that the SDAT and SCLT are active only when necessary and muted once the tuner frequency has settled ...
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... M_CLK tied to V consumption (PCMCIA size front-end modules) before any 2 command C sequence, the standby mode is entirely controlled via MCR Register (02). STV0299 Next bit Transmission of 1’s Transmission of 0’s: a) PortCtrl2 = 1 b) PortCtrl2 = 0 DiSEqC Output During Inactive Modulation 0 1 high Z 22 kHZ ...
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... STV0299 4 FUNCTIONAL DESCRIPTION (continued) 4.2 Signal Processing 4.2.1 I and Q Inputs I and Q signals from the tuner are fed to the respective I and Q inputs through a capacitor. The biasing of the ADC is done on the circuit at the mid-voltage between V TOP Compensation for the residual offset is performed in the digital domain. ...
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... Register List on page 22. alpha_tmg Mbaud S 0.66 kHz 0.85 0.93 kHz 0.60 1.32 kHz 0.42 1.86 kHz 0.30 2.63 kHz 0.21 3.72 kHz 0.15 5.26 kHz 0.10 Loop Equation – 5 the symbol frequency the AGC2 S is programmed by the timing beta_tmg 2 = alpha_tmg 0.134 ------------------------------------------------------------- - beta_tmg 2 Timing Lock Indicator 2 3 Damping Factor 1.70 3.38 1.20 2.40 0.85 1.70 0.60 1.20 0.42 0.85 0.30 0.60 0.21 0.42 STV0299 4 6.77 4.80 3.38 2.40 1.70 1.20 0.85 13/36 ...
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... STV0299 4 FUNCTIONAL DESCRIPTION (continued) 4.4 Carrier Recovery and Derotator Loop The tracking range of the derotator /2). The initial frequency search may sampling therefore be performed on several MHz ranges without reprogramming the tuner. Three phase detectors are selectable using software: • Phase detector algorithm 0: This algorithm should only be used for BPSK reception. • ...
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... FUNCTIONAL DESCRIPTION (continued) 4.6 Forward Error Correction 4.6.1 FEC Modes Since the STV0299 is a multistandard decoder, several combinations are possible, at different levels: • The demodulator may accept either QPSK or BPSK signals - the only impact is on the carrier algorithm choice (refer to page 14). The algorithm choice also affects the carrier lock detector and the noise evaluation. • ...
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... STV0299 4 FUNCTIONAL DESCRIPTION (continued) 4.6.3 Synchronization In DVB, the packet length after inner decoding is 204. The sync word is the first byte of each packet. Its value is Hex 47, but this value is complemented every 8 packets. In DSS, the packet length is 147 and the sync word is Hex 1D. ...
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... In the FEC Mode Register, bit 1 should be “1” (refer to page 24). 1/f M-CLK RS1 = 1 RS1 = 0 Data First bit of the packet RS0 = 0 Useful Data RS0 = 1 RS0 = 0 RS0 = 1 1 Packet No Error Uncorrectible Packet Data Parity if RS1 = 1. This or 6/f VCO Parity Parity No Error STV0299 clock runs 17/36 ...
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... DIRCLK (Reset value depends on the polarity of DIRCLK-DIS pin). [4:0] M[4:0] 7 STDBY (Reset value depends on the polarity of STDBY pin). VCO ON/OFF OFF [5:4] These bits must be programmed to one. 3 SERCLK 0: Maximum instantaneous SERCL = Master Clock 1: Maximum instantaneous SERCL = [2:0] P[2:0] VC0 to M_CLK divider STV0299 Signal Description F VCO ----------------- 6 18/36 ...
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... repeater 0: Output port [6:3] These bits must be programmed to zero. 2 SCLT Port value 1 This bit must be programmed to zero. 0 SDAT Port value STV0299 Signal Description = 400 MHz. VCO Signal Frequency N/A output port = 0 N/A output port = 1 f /8/ACR[4:0] 1 VCO f /8192/(32+ACR[4:0]) 64 VCO ...
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... STV0299 REGISTER LIST (continued) 5 HEX Reset Name Address Value DAC REGISTERS (refer to Section 4.1.11 on page 10) DACR1 (MSB DACR2 (LSB DISEQC AND LOCK CONTROL REGISTER (refer to Section 4.1.12 on page 10) DiSEqC 08 60 DISEQC FIFO (refer to Section 4.1.12 on page 10) DiSEqC FIFO 09 00 DISEQC STATUS (refer to Section 4.1.12 on page 10) ...
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... This bit must be programmed to zero. [2:0] beta_tmg 7 Iagc 1: Invert 0: Normal If Iagc is set, the output signal is complemented (i.e. a high value for the AGC voltage will cause a high gain in the tuner). 6 This bit must be programmed to zero. [5:0] AGC1 Reference Value (m1). Refer to page 12. [7:5] AGC2 Coefficient [4:0] AGC2_Ref (M2) STV0299 Signal Description 21/36 ...
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... STV0299 REGISTER LIST (continued) 5 HEX Reset Name Address Value TIMING LOCK SETTING REGISTER (refer to Section 4.3.3 on page 13) TLSR 11 88 CARRIER FREQUENCY DETECTOR REGISTER (refer to Chapter 4.4 on page 14) CFD 12 F7 ALPHA CARRIER AND NOISE ESTIMATOR REGISTER (refer to Chapter 4.5 on page 14) ACLC 13 88 BETA CARRIER REGISTER (refer to Chapter 4.4 on page 14) ...
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... LSB byte [7:0] Symb_freq (MSBs) The reset value of Hex 800000 corresponds to f [7:0] Symb_freq (Middle SB S [7:4] Symb_freq (LSB ) S [3:0] These bits must be programmed to zero. [7:0] Derotator Frequency (MSB) (signed value) [7:0] Derotator Frequency (LSB) (signed value) [7:0] Noise Indicator (MSB) [7:0] Noise Indicator (LSB) STV0299 Signal Description /2. M_CLK ) 23/36 ...
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... STV0299 REGISTER LIST (continued) 5 HEX Reset Name Address Value VERROR REGISTER (Read Only) (refer to Section 4.6.2 on page 15) VERROR 26 RO FEC MODE REGISTER (refer to Section 4.6.1 on page 15) FECM 28 01 VITERBI THRESHOLD REGISTERS (refer to Section 4.6.2 on page 15) VTH0 29 1E VTH1 2A 14 VTH2 2B 0F VTH3 2C 09 VTH4 ...
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... Reset Value (64k bit periods) [1:0] H[1:0] This is the hysteresis value. This field is used to program the maxi- mum value of the Sync counter. The unit is the block duration (204 bytes in DVB, 147 in DSS). 00: 16 01: 32 10: 64 11: 128 Reset Value (32 blocks) STV0299 Signal Description 25/36 ...
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... RS6 - Synchro Enable 1: The synchro is processed. 0: The synchro word search is disabled. The bit-to-byte conversion remains in its current phase regardless of whether the synchro word is recognized or not. This allows the use of the STV0299 with inner convolutional coding only. 5 RS5 - Reed-Solomon Enable 1: The input code is corrected. ...
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... The error sources are as follows: 00: QPSK bit errors 01: Viterbi bit errors 10: Viterbi byte errors 11: Packet errors. [3:2] These bits must be programmed to zero. [1:0] NOE The NOE bits represent the Count Period in bytes (NB): 12 00: 2 bytes 14 01: 2 bytes 16 10: 2 bytes 18 11: 2 bytes STV0299 Signal Description 27/36 ...
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... STV0299 6 ELECTRICAL CHARACTERISTICS 6.1 Absolute Maximum Ratings Maximum limits indicate where permanent device damages occur. Continuous operation at these Symbol Parameter V Pad Power Supply Voltage DD_3 Core Level Power Supply Voltage (1) Voltage on Input Pins V O (1) Voltage on Output Pins T Storage Temperature ...
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... Signal to Noise Ratio Z Input Impedance between Effective Number of bits eff = 25°C unless otherwise specified. amb Test Conditions SINK V = 5.5 V AGC I/Q Inputs I/Q Inputs & V TOP BOT STV0299 Min. Typ. Max. Unit TBD TBD V TBD TBD TBD pF TBD TBD ...
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... STV0299 6 ELECTRICAL CHARACTERISTICS (continued) 6.4 Timing Characteristics Symbol Parameter f Internal VCO frequency VCO f CLK_IN or XTAL frequency CLK_IN t Clock signal low level duration (external clock) CLK_INL t Clock signal high level duration (external clock) CLK_INH PARALLEL OUTPUT D[7:0], D/P, CLK_OUT, STR_OUT, ERROR OUTPUT CHARACTERISTICS Bit RS1 = Register (see to “RS CONTROL REGISTER (refer to Section 4.6.6 on page 16)” on page 26 and ...
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... F C Capacitive Load for each Bus Line B 2 Figure 12 bus timing diagram Test Conditions Pull 10% Pull 10 0 Normal Mode Standby Mode nals STV0299 Min. Typ. Max. Unit -0.5 0.8 V 2.0 5.5 V 2.4 V 0 3.5 pF ...
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... STV0299 7 APPLICATION BLOCK DIAGRAMS Figure 13: Application Block Diagram ZIF or Double Conversion LNB Supply 32/36 AGC Control I Dual Repeater 2 to PLL Synthesizer 4 MHz I/O + DiSEqC AGC1 QPSK FEH Serial or Parallel serial or 12 parallel To Transport IC ...
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... LNBP 15SP 2V5D 10k 2 x OLF 10k 2.2 F 10nF SDA SCL RESET Requirements : The slug of the STV0299 must be connected to the digital ground. The digital ground and the analog ground must be connected by only one track. 5V 1k5 1k5 5V 5V 30V 100 nF 100 nF (option) ...
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... STV0299 8 PACKAGE MECHANICAL DATA 64 Pins Thin Plastic Quad Flat Pack (TQFP Slug-down Dimensions Min 0.05 A2 1.35 B 0. 3.80 S1 3.80 K 34/ Millimeters Typ. Max. 1.60 0.15 1.40 1.45 0.22 0.27 0.20 12.00 10.00 7.50 0.50 12.00 10.00 7.50 3.75 0.60 0.75 1.00 0° (Min.), 7° (Max 0,10 mm .004 inch ...
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... Millimeters Typ. Max. 1.60 0.15 1.40 1.45 0.22 0.27 0.20 12.00 10.00 7.50 0.50 12.00 10.00 7.50 0.60 0.75 1.00 0° (Min.), 7° (Max.) STV0299 0,10 mm .004 inch SEATING PLANE 0,25 mm .010 inch GAGE PLANE Inches Min. Typ. 0.002 0.053 0.055 0.007 0.009 0.004 0.472 0.394 0.295 0.0197 0.472 0.394 0.295 0.018 0.024 0.039 Max ...
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... STV0299 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. ...