K7M163625A-QC65 Samsung, K7M163625A-QC65 Datasheet
K7M163625A-QC65
Related parts for K7M163625A-QC65
K7M163625A-QC65 Summary of contents
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... K7M163625A K7M161825A Document Title 512Kx36 & 1Mx18-Bit Flow Through NtRAM Revision History Rev. No. History 0.0 1. Initial document. 0.1 1. Add JTAG Scan Order 0.2 1. Remove bin -90 2. Updated DC characteristics(ICC,ISB,ISB1,ISB2) 0.3 1. Add x32 org and industrial temperature . 2. Add 165FBGA package 1.0 1. Final spec release 2.0 1. Add the speed bin (-60) 2 ...
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... K7M163625A K7M161825A 16Mb NtRAM(Flow Through / Pipelined) Ordering Informa Org. Part Number K7M161825A-QC(I)65/75 1Mx18 K7N161801A-Q(F)C(I)25/20/16/13 K7N161845A-Q(F)C(I)25/20/16/13 K7M163625A-QC(I)65/75 512Kx36 K7N163601A-Q(F)C(I)25/20/16/13 K7N163645A-Q(F)C(I)25/20/16/13 512Kx36 & 1Mx18 Flow-Through NtRAM tion Speed Mode VDD FT ; Access Time(ns) Pipelined ; Cycle Time(MHz) FlowThrough 3.3 6.5/7.5 ns Pipelined 3.3 250/200/167/133MHz Pipelined 2.5 250/200/167/133MHz FlowThrough 3.3 6.5/7.5 ns Pipelined 3.3 250/200/167/133MHz Pipelined 2 ...
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... For read cycles, Flow-Through SRAM allows output data to simply flow freely from the memory array. The K7M163625A and K7M161825A are implemented with SAMSUNG s high performance CMOS technology and is avail- -65 -75 Unit able in 100pin TQFP packages ...
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... Burst Mode Control Notes : 1. A and A are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired 512Kx36 & 1Mx18 Flow-Through NtRAM 100 Pin TQFP (20mm x 14mm) K7M163625A(512Kx36) TQFP PIN NO. SYMBOL 32,33,34,35,36,37,44 V Power Supply(+3.3V) DD 45,46,47,48,49,50,81 V Ground ...
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... K7M163625A K7M161825A PIN CONFIGURATION (TOP VIEW) N.C. 1 N. DDQ V 5 SSQ N.C. 6 N.C. 7 DQb 8 8 DQb SSQ V 11 DDQ DQb 12 6 DQb DQb 18 4 DQb DDQ 21 V SSQ DQb 22 2 DQb ...
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... K7M163625A K7M161825A FUNCTION DESCRIPTION The K7M163625A and K7M161825A are NtRAM there is transition from Read to Write, or vice versa. All inputs (with the exception LBO and ZZ) are synchronized to rising clock edges. All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the burst advance pin (ADV) ...
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... K7M163625A K7M161825A BEGIN READ READ BURST COMMAND DS READ WRITE BURST Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does not change the state of the device. 2. States change on the rising edge of the clock(CLK) 512Kx36 & ...
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... K7M163625A K7M161825A TRUTH TABLES SYNCHRONOUS TRUTH TABLE ADV WE BWx ...
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... K7M163625A K7M161825A ASYNCHRONOUS TRUTH TABLE Operation ZZ Sleep Mode H L Read L Write L Deselected L ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on V Supply Relative Voltage on Any Other Pin Relative to V Power Dissipation Storage Temperature Operating Temperature Storage Temperature Range Under Bias *Notes : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied ...
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... K7M163625A K7M161825A DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Input Leakage Current(except ZZ) Output Leakage Current Operating Current Standby Current Output Low Voltage(3.3V I/O) Output High Voltage(3.3V I/O) Output Low Voltage(2.5V I/O) Output High Voltage(2.5V I/O) Input Low Voltage(3.3V I/O) Input High Voltage(3.3V I/O) Input Low Voltage(2.5V I/O) Input High Voltage(2.5V I/O) Notes : 1. The above parameters are also guaranteed at industrial temperature range. ...
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... K7M163625A K7M161825A Output Load(A) Dout Zo=50 AC TIMING CHARACTERISTICS PARAMETER Cycle Time Clock Access Time Output Enable to Data Valid Clock High to Output Low-Z Output Hold from Clock High Output Enable Low to Output Low-Z Output Enable High to Output High-Z Clock High to Output High-Z Clock High Pulse Width ...
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... K7M163625A K7M161825A SLEEP MODE SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to I SLEEP MODE is dictated by the length of time the High state. After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE ...
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... K7M163625A K7M161825A 512Kx36 & 1Mx18 Flow-Through NtRAM - Nov. 2003 Rev 3.0 ...
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... K7M163625A K7M161825A 512Kx36 & 1Mx18 Flow-Through NtRAM - Nov. 2003 Rev 3.0 ...
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... K7M163625A K7M161825A 512Kx36 & 1Mx18 Flow-Through NtRAM - Nov. 2003 Rev 3.0 ...
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... K7M163625A K7M161825A 512Kx36 & 1Mx18 Flow-Through NtRAM - Nov. 2003 Rev 3.0 ...
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... K7M163625A K7M161825A 512Kx36 & 1Mx18 Flow-Through NtRAM - Nov. 2003 Rev 3.0 ...
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... K7M163625A K7M161825A PACKAGE DIMENSIONS 100-TQFP-1420A #1 0.65 512Kx36 & 1Mx18 Flow-Through NtRAM 22.00 0.30 20.00 0.20 (0.58) 0.30 0.10 0.10 MAX 1.40 0.05 MIN 0.50 0. Units ; millimeters/Inches 0~8 + 0.10 0.127 - 0.05 16.00 0.30 0.10 MAX 14.00 0.20 (0.83) 0.50 0.10 1.60 MAX 0.10 TM Nov. 2003 Rev 3.0 ...