SAF-C517A-LN Infineon Technologies AG, SAF-C517A-LN Datasheet
SAF-C517A-LN
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SAF-C517A-LN Summary of contents
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C517A Data Sheet Revision History : Previous Releases : Page Page (previous (new version) version) All sections All sections ...
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CMOS Microcontroller Advance Information • Full upward compatibility with SAB 80C517A/83C517A-5 • MHz external operating frequency – 500 ns instruction cycle at 24 MHz operation • Superset of the 8051 architecture with 8 datapointers • On-chip ...
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... P-MQFP-100 and P-LCC-84 packages • Temperature Ranges : SAB-C517A SAF-C517A SAH-C517A Ordering Information The ordering code for Siemens microcontrollers provides an exact reference to the required product. This ordering code identifies: • the derivative itself, i.e. its function set • ...
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Port 7 8-bit Analog/ Digital Input Port 8 4-bit Analog/ Digital Input XTAL1 XTAL2 ALE PSEN EA RESET PE/SWD OWE RO HWPD V AREF V AGND Figure 2 Logic Symbol Semiconductor Group Port 0 ...
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CC4/INT2/P1.4 2 N.C. 3 N.C. 4 N.C. 5 N.C. 6 CC3/INT6/P1.3 7 CC2/INT5/P1.2 8 CC1/INT4/P1.1 9 CC0/INT3/P1 XTAL2 13 XTAL1 14 P2.0/A8 15 P2.1/A9 16 P2.2/A10 17 P2.3/A11 18 P2.4/A12 ...
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V 12 AGND P7.7/AIN7 13 P7.6/AIN6 14 P7.5/AIN5 15 P7.4/AIN4 16 P7.3/AIN3 17 P7.2/AIN2 18 P7.1/AIN1 19 P7.0/AIN0 20 P3.0/RxD0 21 P3.1/TxD0 22 P3.2/INT0 23 P3.3/INT1 24 P3.4/T0 25 P3.5/T1 26 P3.6/WR 27 P3.7/RD 28 P1.7/T2 29 P1.6/CLKOUT 30 P1.5/T2EX ...
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Table 1 Pin Definitions and Functions P1 100 - 100 Input Output Semiconductor Group I/O Port 1 is ...
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Table 1 Pin Definitions and Functions XTAL2 12 XTAL1 13 P2 Input O = Output Semiconductor Group (cont’d) 37, 83 – Ground (0V) during ...
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Table 1 Pin Definitions and Functions PSEN 22 ALE P0.0 - P0.7 26, 27 Input O = Output Semiconductor Group (cont’ The Program Store Enable output is a control ...
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Table 1 Pin Definitions and Functions HWPD 36 P5 OWE Input O = Output Semiconductor Group (cont’ Hardware Power Down A low level on this pin for the duration ...
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Table 1 Pin Definitions and Functions P6 P8 Input O = Output Semiconductor Group (cont’ I/O ...
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Table 1 Pin Definitions and Functions P4 PE/SWD Input O = Output Semiconductor Group (cont’ I/O Port 8-bit quasi-bidirectional ...
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Table 1 Pin Definitions and Functions P3 Input O = Output Semiconductor Group (cont’ I/O Port 8-bit quasi-bidirectional ...
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Table 1 Pin Definitions and Functions RESET AREF V 79 AGND P7 25, 28 Input O ...
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Oscillator Watchdog XTAL1 OSC & Timing XTAL2 ALE PSEN 8 Datapointer EA PE/SWD Programmable Watchdog Timer RESET HWPD Timer 0 RO OWE Timer 1 Compare Unit Compare Timer Serial Channel 0 Programmable Baud Rate Generator Serial Channel 1 Programmable Baud ...
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CPU The C517A is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting ...
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Memory Organization The C517A CPU manipulates operands in the following five address spaces: – Kbyte of program memory (32K on-chip program memory for C517A-4R) – Kbyte of external data memory – 256 bytes of ...
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Reset and System Clock The reset input is an active low input at pin RESET. Since the reset is synchronized internally, the RESET pin must be held low for at least two machine cycles (24 oscillator periods) while the oscillator ...
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Figure 8 shows the recommended oscillator circiutries for crystal and external clock operation. Crystal Oscillator Mode C 3 MHz C Crystal Mode: Figure 8 Recommended Oscillator Circuitries Semiconductor Group Driving from External Source N.C. XTAL1 External Oscillator Signal ...
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Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of ...
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Special Function Registers The registers, except the program counter and the four general purpose register banks, reside in the special function register area. The 94 special function registers (SFRs) in the standard and mapped SFR area include pointers and registers ...
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Table 2 Special Function Registers - Functional Blocks Block Symbol Name CPU ACC Accumulator B B-Register DPH Data Pointer, High Byte DPL Data Pointer, Low Byte DPSEL Data Pointer Select Register PSW Program Status Word Register SP Stack Pointer A/D- ...
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Table 2 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Compare/ CCEN Compare/Capture Enable Register Capture CC4EN Compare/Capture 4 Enable Register Unit CCH1 Compare/Capture Register 1, High Byte (CCU) CCH2 Compare/Capture Register 2, High Byte Timer 2 CCH3 ...
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Table 2 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Ports P0 Port 0 P1 Port 1 P2 Port 2 P3 Port 3 P4 Port 4 P5 Port 5 P6 Port 6 P7 Port 7, Analog/Digital Input P8 ...
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Table 3 Contents of the SFRs, SFRs in numeric order of their addresses Addr Register Content Bit 7 after 1) Reset DPL ...
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Table 3 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d) Addr Register Content Bit 7 after 1) Reset COMCLRH A5 H SETMSK CLRMSK ...
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Table 3 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d) Addr Register Content Bit 7 after 1) Reset CA H CRCL CRCH TL2 ...
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Table 3 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d) Addr Register Content Bit 7 after 1) Reset E3 H CMH3 CML4 CMH4 ...
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Digital I/O Ports The C517A allows for digital I lines grouped into 7 bidirectional 8-bit ports. Each port bit consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports ...
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Timer / Counter 0 and 1 Timer/Counter 0 and 1 can be used in four operating modes as listed in table 4 : Table 4 Timer/Counter 0 and 1 Operating Modes Mode Description 0 8-bit timer/counter with a divide-by-32 prescaler ...
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Cpmpare / Capture Unit (CCU) The compare/capture unit is one of the C517A’s most powerful peripheral units for use in all kinds of digital signal generation and event capturing like pulse generation, pulse width modulation, pulse width measuring etc. The ...
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The main functional blocks of the CCU are : – Timer 2 with f /12 input clock, 2-bit prescaler, 16-bit reload, counter/gated timer mode and OSC overflow interrupt request. f – Compare timer with OSC request. – Compare/(reload/)capture register array ...
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Timer 2 Operation Timer Mode : In timer function, the count rate is derived from the oscillator frequency. A prescaler offers the possibility of selecting a count rate of 1/12 or 1/24 of the oscillator frequency. Gated Timer Mode : ...
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Compare Timer Operation The compare timer receives its input clock from a programmable prescaler which provides input frequencies, ranging from f OSC 16-bit timer, which on overflow is automatically reloaded by the contents of a 16-bit reload register. The compare ...
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Compare Modes The compare function of a timer/register combination operates as follows : the 16-bit value stored in a compare or compare/capture register is compared with the contents of the timer register; if the count value in the timer register ...
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Compare Register Circuit Compare Reg. 16 Bit Comparator Compare 16 Bit Match Timer Register Timer Circuit Figure 15 Compare Function in Compare Mode 1 Compare Mode 2 In the compare mode 2 the port 5 pins are under control of ...
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Multiplication / Division Unit (MDU) This on-chip arithmetic unit of the C517A provides fast 32-bit division, 16-bit multiplication as well as shift and normalize features. All operations are unsigned integer operations. Table 6 describes the five general operations the MDU ...
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For starting an operation, registers MD0 to MD5 and ARCON must be written certain sequence according table 7 and 8. The order the registers are accessed determines the type of the operation. A shift operation is started ...
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Serial Interfaces 0 and 1 The C517A has two serial interfaces which are functionally nearly identical concerning the asynchronous modes of operation. The two channels are full-duplex, meaning they can transmit and receive simultaneously. The serial channel 0 is completely ...
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For clarification some terms regarding the difference between "baud rate clock" and "baud rate" should be mentioned. In the asynchronous modes the serial interfaces require a clock rate which is 16 times the baud rate for internal synchronization. Therefore, the ...
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Table 10 below lists the values/formulas for the baud rate calculation of serial interface 0 and 1 with its dependencies of the control bits BD and SMOD. Table 10 Serial Interfaces - Baud Rate Dependencies Serial Interface Active Control Operating ...
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A/D Converter The C517A provides an A/D converter with the following features: – 12 multiplexed input channels (port 7, 8), which can also be used as digital inputs – 10-bit resolution – Single or continuous conversion mode – Internal ...
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IEN1 ( EXEN2 IRCON0 ( EXF2 P7.7 ADCON1 ( ADCL ADCON0 ( Port 7 Port 8 Clock f /2 OSC Prescaler ÷8, ÷4 ...
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Interrupt System The C517A provides 17 interrupt sources with four priority levels. Ten interrupts can be generated by the on-chip peripherals (timer 0, timer 1, timer 2, compare timer, compare match/set/clear, A/D converter, and serial interface 0 and 1) and ...
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P3.2/ INT0 IT0 TCON.0 RI1 S1CON.0 UART 1 TI1 S1CON.1 A/D Converter Timer 0 Overflow P1.4/ INT2/ CC4 I2FR T2CON.5 Bit addressable Request Flag is cleared by hardware Figure 21 Interrupt Structure, Overview (Part 1) Semiconductor Group IE0 0003 EX0 ...
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P3.3/ INT1 IT1 TCON.2 Match in CM0-CM7 P1.0/ INT3/ CC0 I3FR T2CON.5 Timer 1 Overflow Compare Timer Overflow P1.1/ INT4/ CC1 Bit addressable Request Flag is cleared by hardware Figure 22 Interrupt Structure, Overview (Part 2) Semiconductor Group IE1 0013 ...
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RI0 S0CON.0 USART 0 TI0 S0CON.1 Match in COMSET P1.2/ INT5/ CC2 Timer 2 TF2 Overflow IRCON0.6 P1.5/ EXF2 T2EX EXEN2 IRCON0.7 IEN1.7 Match in COMCLR P1.3/ INT6/ CC3 Bit addressable Request Flag is cleared by hardware Figure 23 Interrupt ...
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Table 11 Interrupt Source and Vectors Interrupt Source External Interrupt 0 Timer 0 Overflow External Interrupt 1 Timer 1 Overflow Serial Channel 0 Timer 2 Overflow / Ext. Reload A/D Converter External Interrupt 2 External Interrupt 3 External Interrupt 4 ...
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... Fail Save Mechanisms The C517A offers enhanced fail safe mechanisms, which allow an automatic recovery from software upset or hardware failure : – a programmable watchdog timer (WDT), with variable time-out period from 512 approx. 1 MHz. (256 approx. 0. MHz) – an oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the microcontroller into reset state in case the on-chip oscillator fails ...
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Oscillator Watchdog The oscillator watchdog unit serves for four functions: – Monitoring of the on-chip oscillator’s function The watchdog supervises the on-chip oscillator's frequency lower than the frequency of the auxiliary RC oscillator in the watchdog unit, ...
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Power Saving Modes The C517A provides two basic power saving modes, the idle mode and the power down mode. Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate in normal operating mode and ...
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Table 12 Power Saving Modes Overview Mode Entering 2-Instruction Example Idle mode ORL PCON, #01H ORL PCON, #20H Slow Down Mode In normal mode : ORL PCON,#10H With idle mode : ORL PCON,#01H ORL PCON, #30H Software ORL PCON, #02H ...
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... the values defined by the absolute maximum ratings. Operating Conditions Parameter Supply voltage Ground voltage Ambient temperature SAB-C517A SAF-C517A SAH-C517A Analog reference voltage Analog ground voltage Analog input voltage CPU clock Semiconductor Group Symbol Limit Values min. T – – ...
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DC Characteristics (Operating Conditions apply) Parameter Input low voltage Pins except EA,RESET,HWPD EA pin HWPD and RESET pins Input high voltage pins except RESET, XTAL2 and HWPD XTAL2 pin RESET and HWPD pin Output low voltage Ports ...
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Power Supply Current Parameter Active mode 18 MHz 24 MHz Idle mode 18 MHz 24 MHz Active mode with 18 MHz slow-down enabled 24 MHz Power-down mode Notes: 1) Capacitive loading on ports 0 and 2 may cause spurious noise ...
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3.5 Figure 26 IDD Diagram Table 13 Power Supply Current Calculation Formulas Parameter Symbol I Active mode DD typ I DD max Idle mode I DD typ I DD max ...
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A/D Converter Characteristics (Operating Conditions apply) Parameter Analog input voltage Sample time Conversion cycle time Total unadjusted error Internal resistance of reference voltage source Internal resistance of analog source ADC input capacitance Notes see next page. Clock calculation table : ...
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Notes may exeed AIN AGND these cases will be X000 or X3FF H 2) During the sample time the input capacitance C internal resistance of the analog source must allow the capacitance to reach their ...
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AC Characteristics (18 MHz) (Operating Conditions apply for port 0, ALE and PSEN outputs = 100 pF; L Program Memory Characteristics Parameter ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instruction ...
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AC Characteristics (18 MHz, cont’d) External Data Memory Characteristics Parameter RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to ...
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AC Characteristics (24 MHz) (Operating Conditions apply for port 0, ALE and PSEN outputs = 100 pF; L Program Memory Characteristics Parameter ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instruction ...
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AC Characteristics (24 MHz, cont’d) External Data Memory Characteristics Parameter RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to ...
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ALE PSEN Port 0 Port 2 Figure 27 Program Memory Read Cycle Semiconductor Group t LHLL t t AVLL PLPH t LLPL t LLIV t PLIV t AZPL t LLAX Instr.IN t AVIV A8 - A15 62 ...
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ALE PSEN RD t AVLL from Port DPL Port 2 Figure 28 Data Memory Read Cycle Figure 29 CLKOUT Timing Semiconductor Group t LLDV t t LLWL RLRH t RLDV t LLAX2 t RLAZ ...
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ALE PSEN WR t AVLL from Port DPL t AVWL Port 2 Figure 30 Data Memory Write Cycle 0. 0 0.1 0.2 0.45V Figure 31 External ...
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ROM Verification Characteristics for the C517A-4RM/4RN ROM Verification Mode 1 Parameter Address to valid data P1.0-P1.7 P2.0-P2.6 Port 0 Data: Addresses: Figure 32 ROM Verification Mode 1 Semiconductor Group Symbol min. t – AVQV Address t AVQV Data Out P0.0-P0.7 ...
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ROM Verification Mode 2 Parameter ALE pulse width ALE period Data valid after ALE Data stable after ALE P3.5 setup to ALE low Oscillator frequency ALE Port 0 P3.5 Figure 33 ROM Verification Mode 2 Semiconductor Group Symbol min. t ...
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Inputs during testing are driven at Timing measurements are made at Figure 34 AC Testing: Input, Output Waveforms V Load V Load For timing purposes a port pin is no longer floating when a 100 ...
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Plastic Package, P-MQFP-100-2 (SMD) (Plastic Metric Quad Flat Package) Figure 37 P-LCC-100-2 Package Outlines Semiconductor Group 68 C517A ...
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Plastic Package, P-LCC-84-2 (SMD) (Plastic Leaded Chip-Carrier) 1.27 0.43 ±0.1 0.18 84x M 25 29.31 ±0.076 30.23 ±0.13 1) Does not include plastic or metal protrusions of 0.25 max. per side 2) Dimension from center to center Figure ...
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Semiconductor Group 70 C517A ...