i960 Intel Corporation, i960 Datasheet
i960
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i960 Summary of contents
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... RP/RD I/O PROCESSOR AT 3.3 VOLTS • 33 MHz, 3.3 Volt Version (80960RP 33/3.3) • 66 MHz, 3.3 Volt Version (80960RD 66/3.3) - Clock Doubled 80960JF Core • Complies with PCI Local Bus Specification Revision 2.1 • 5 Volt PCI Signalling Environment High Performance 80960JF Core — Sustained One Instruction/Clock Execution — 4 Kbyte Two-Way Set-Associative Instruction Cache — ...
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... Intel may make changes to specifications and product descriptions at any time, without notice. *Third-party brands and names are the property of their respective owners. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect IL 60056-764 or call 1-800-548-4725 ©INTEL CORPORATION, 1997 ...
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... Address Translation Unit .......................................................................................................... 3 2.1.5 Messaging Unit ........................................................................................................................ 3 2.1.6 Memory Controller ................................................................................................................... 3 2.1.7 I2C Bus Interface Unit .............................................................................................................. 3 2.1.8 I/O APIC Bus Interface Unit ..................................................................................................... 3 2.1.9 Secondary PCI Arbitration Unit ................................................................................................ 4 2.2 i960 Core Features (80960JF) ........................................................................................................... 4 2.2.1 Burst Bus ................................................................................................................................. 5 2.2.2 Timer Unit ................................................................................................................................ 5 2.2.3 Priority Interrupt Controller ....................................................................................................... 5 2.2.4 Faults and Debugging .............................................................................................................. 5 2.2.5 On-Chip Cache and Data RAM ................................................................................................ 5 2.2.6 Local Register Cache ............................................................................................................... 5 2 ...
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... Rx I/O Processor at 3.3 V FIGURES ® Figure 1. i960 Rx I/O Processor at 3.3 V Functional Block Diagram .......................................................... 2 Figure 2. 80960JF Core Block Diagram ........................................................................................................ 4 Figure 3. 352L HL-PBGA Package Diagram (Top and Side View) ............................................................. 21 Figure 4. 352L HL-PBGA Package Diagram (Bottom View) ....................................................................... 22 Figure 5. Thermocouple Attachment - No Heat Sink .................................................................................. 31 Figure 6. Thermocouple Attachment - With Heat Sink ................................................................................ 31 Figure 7 ...
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TABLES Table 1. Related Documentation ................................................................................................................. 1 Table 2. 80960Rx Instruction Set ................................................................................................................ 7 Table 3. Signal Type Definition .................................................................................................................... 8 Table 4. Signal Descriptions ........................................................................................................................ 9 Table 5. Power Requirement, Processor Control and Test Signal Descriptions ....................................... 13 Table ...
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... Rx I/O Processor at 3 ...
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... ABOUT THIS DOCUMENT This is the ADVANCE INFORMATION data sheet for the low-power (3.3 V) versions of Intel’s i960 Processor family, including: • 80960RD 66/3.3 • 80960RP 33/3.3 Throughout this document, these family members are referred to as 80960Rx when the information is common to both. For product-specific information, such as electrical characteristics, the family member names are used ...
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... Physical and programmed via memory-mapped control registers (MMRs), an extension not found on the i960 Kx processors. Physical and logical configuration registers enable the processor to operate with all combinations of bus width and data object align- ment. ...
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... Special Interest Group. It allows certain bus transac- tions on one PCI bus to be forwarded to the other PCI bus. Dedicated data queues support high perfor- mance bandwidth on the PCI buses. The i960 I/O Processor at 3.3 V supports PCI 64-bit Dual Address Cycle (DAC) addressing. The bridge has dedicated PCI configuration space that is accessible through the primary PCI bus ...
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... PCI Request and Grant signal pairs. This arbitra- tion unit can also be disabled to allow for external arbitration. 2.2 i960 Core Features (80960JF) The processing power of the 80960Rx comes from the 80960JF processor core. The 80960JF is a new, scalar implementation of the 80960 Core Architec- ture ...
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... Interrupt vectors and interrupt handler routines can be reserved on-chip ADVANCE INFORMATION ® i960 Rx I/O Processor at 3.3 V • Register frames for high-priority interrupt handlers can be cached on-chip • The interrupt stack can be placed in cacheable memory space 2 ...
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... Rx I/O Processor at 3.3 V One of the boundary scan instructions, HIGHZ, forces the processor to float all its output pins (ONCE mode). ONCE mode can also be initiated at reset without using the boundary scan mechanism. ONCE mode is useful for board-level testing. This feature allows a mounted 80960Rx to electrically “ ...
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... Branch Call/Return Call Call Extended Call System Return Branch and Link Atomic Atomic Add Atomic Modify ® i960 Rx I/O Processor at 3.3 V Bit, Bit Field and Byte Set Bit Clear Bit Not Bit Alter Bit Scan For Bit Span Over Bit Extract Modify ...
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... Rx I/O Processor at 3.3 V 3.0 PACKAGE INFORMATION 3.1 Package Introduction The 80960Rx is offered in a SuperBGA* Ball Grid Array (HL-PBGA) package. This is a perimeter array package with four rows of ball connections in the outer area of the package. See Figure 4, 352L HL- PBGA Package Diagram (Bottom View) (pg. 22). ...
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... Not the Last Data Transfer ADVANCE INFORMATION DESCRIPTION AD0 Bus Transfers 0 1 Transfer 1 2 Transfers 0 3 Transfers 1 4 Transfers cycle and deasserted before the beginning of the ® i960 Rx I/O Processor at 3 cycle, bits 2-31 contain T a cycle, specifies T a cycle. External bus ...
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... The processor asserts byte enables, byte high enable and byte low enable during tions, these signals do not toggle during a burst (32-bit bus only) from the i960 core processor; they do toggle for DMA and ATU cycles. They remain active through the last T DEN# O DATA ENABLE indicates data transfer cycles during a bus access ...
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... ONCE Mode Not Enabled LRDYRCV# O LOCAL READY/RECOVER, generated by the 80960Rx’s memory controller R(1) unit output version of the READY/RECOVER (RDYRCV#) signal. H(Q) Refer to the RDYRCV# signal description. P(Q) ADVANCE INFORMATION ® i960 DESCRIPTION and T a and T /T cycles for a write. DT/R# never changes state I/O Processor at 3 ...
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... Rx I/O Processor at 3.3 V Table 4. Signal Descriptions (Sheet NAME TYPE HOLD I HOLD is a request from an external bus master to acquire the bus. When the S(L) processor receives HOLD and grants bus control to another master, it asserts HOLDA, floats the address/data and control lines and enters the T state ...
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... TEST MODE SELECT is sampled at the rising edge of TCK to select the operation of S(L) the test logic for IEEE 1149.1 Boundary Scan testing. This signal has a weak internal pullup which is active during reset to ensure normal operation when the signal is not connected. ADVANCE INFORMATION ® i960 Rx I/O Processor at 3.3 V DESCRIPTION DESCRIPTION 13 ...
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... Rx I/O Processor at 3.3 V Table 5. Power Requirement, Processor Control and Test Signal Descriptions (Sheet NAME TYPE TRST# I TEST RESET asynchronously resets the Test Access Port (TAP) controller function A(L) of IEEE 1149.1 Boundary Scan testing (JTAG). When using the Boundary Scan feature, connect a pulldown resistor (1 between this signal and V TAP is not used, this signal must be connected to V required ...
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... PRIMARY PCI BUS REQUEST indicates to the arbiter that this agent K(Q) desires use of the bus. This is a point to point signal. R(Z) NOTE: 1. PCI signal functions are summarized in this data sheet; refer to the PCI Local Bus Specification Revision 2.1 for a more complete definition. ADVANCE INFORMATION ® i960 Rx I/O Processor at 3 DESCRIPTION 15 ...
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... Rx I/O Processor at 3.3 V Table 7. PCI Signal Descriptions (Sheet NAME TYPE P_RST# I PRIMARY RESET brings 80960Rx to a consistent state. When P_RST# is A(L) asserted: • PCI output signals are driven to a known consistent state. • PCI bus interface output signals are three-stated. ...
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... P_RST# enables the internal secondary arbiter. A valid low at the deassertion of P_RST# disables the internal secondary arbiter. NOTE: 1. PCI signal functions are summarized in this data sheet; refer to the PCI Local Bus Specification Revision 2.1 for a more complete definition. ADVANCE INFORMATION ® i960 Rx I/O Processor at 3 DESCRIPTION 17 ...
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... Rx I/O Processor at 3.3 V Table 8. Memory Controller Signal Descriptions (Sheet NAME TYPE CAS7:0# O COLUMN ADDRESS STROBE signals are used for DRAM accesses and are R(1) asserted when the MA11:0 signals contain a valid column address. CAS7:0# H(Q) signals are asserted during refresh. P(Q) Non-Interleaved Operation: ...
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... DMA controller. PICCLK I APIC BUS CLOCK provides synchronous operation of the APIC bus. PICD1:0 I/O APIC DATA lines comprise the data portion of the APIC 3-wire bus. OD R(Z) H(Q) P(Q) ADVANCE INFORMATION i960 DESCRIPTION 2 C Units Signal Descriptions (Sheet DESCRIPTION ® Rx I/O Processor at 3 ...
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... Rx I/O Processor at 3.3 V Table 9. DMA, APIC, I NAME TYPE 2 SCL I CLOCK provides synchronous I OD R(Z) H(Q) P(Q) 2 SDA I DATA used for data transfer and arbitration on the I OD R(Z) H(Q) P(Q) WAIT# O WAIT is an output that allows the DMA controller to insert wait states during R(1) DMA accesses to an external memory system. ...
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... Encapsulant size: 22.38 x 22.38 mm (max). Figure 3. 352L HL-PBGA Package Diagram (Top and Side View) ADVANCE INFORMATION Body Size 35 ± 0.10 mm ® i960 GC80960RxZZ FFFFFFFF QQQQ © ‘9x ‘9x M Ball Footprint 31.75 mm Ball spacing is 1.27 mm Ball width is 0.75 ± 0.15 mm ® i960 Rx I/O Processor at 3 ± 0.10 mm Package Height 0.91 ± 0. ...
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... Rx I/O Processor at 3 Figure 4. 352L HL-PBGA Package Diagram (Bottom View ...
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... B10 AD26 C9 AD27 A9 AD28 B9 AD29 C8 AD30 A8 AD31 B8 ADS# B21 ALE C20 BE0# A22 BE1# B22 BE2# C21 BE3# A21 BLAST# C23 ADVANCE INFORMATION i960 Signal Ball # CAS0# F1 CAS1# F2 CAS2# G3 CAS3# G1 CAS4# G2 CAS5# H3 CAS6# H1 CAS7# H2 CE0# L3 CE1# L1 D/C#/RST_MODE# AF4 DACK# AD3 DALE0 ...
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... Rx I/O Processor at 3.3 V Table 12. 352-Lead HL-PBGA Package — Signal Name Order (Sheet Signal Ball # P_AD10 AF20 P_AD11 AD20 P_AD12 AE19 P_AD13 AF19 P_AD14 AD19 P_AD15 AE18 P_AD16 AE14 P_AD17 AF14 P_AD18 AD14 P_AD19 AE13 P_AD20 AF13 P_AD21 AD13 P_AD22 ...
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... AF1 CC V AF2 CC V AF3 CC V AF24 CC V AF25 CC V AF26 NOTES: 1. Ball AD8 must be tied to either ADVANCE INFORMATION i960 Signal Ball # V B25 CC V B26 C26 D11 CC V D13 ...
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... Rx I/O Processor at 3.3 V Table 12. 352-Lead HL-PBGA Package — Signal Name Order (Sheet Signal Ball # WAIT# N3 WIDTH/HLTD0 AF5 WIDTH/HLTD1/RETRY AE5 26 Signal Ball # XINT4# P2 XINT5# R3 XINT6# R1 ADVANCE INFORMATION Signal Ball # XINT7# R2 ...
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... V CC A26 MA11 B4 MA9 B5 MA7 B6 MA4 B7 MA2 B8 AD31 B9 AD28 ADVANCE INFORMATION i960 Ball # Signal B10 AD25 B11 AD22 B12 AD19 B13 AD16 B14 AD13 B15 AD10 B16 AD7 B17 AD4 B18 AD1 B19 RDYRCV# B20 NC B21 ADS# ...
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... Rx I/O Processor at 3.3 V Table 13. 352-Lead HL-PBGA Pinout — Ballpad Number Order (Sheet Ball # Signal E2 RAS2# E3 RAS0 E23 V CC E24 S_REQ4# E25 S_REQ5#/S_ARB_EN E26 S_GNT4# F1 CAS0# F2 CAS1# F3 RAS3 F23 V SS F24 S_REQ3# F25 S_CLK F26 S_GNT3# G1 CAS3# ...
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... CC AC21 V SS AC22 V CC AC23 V SS AC24 S_AD2 AC25 S_AD4 AC26 S_AD3 AD1 V CC AD2 DREQ ® i960 Rx I/O Processor at 3.3 V Ball # Signal AD3 DACK# AD4 LOCK#/ONCE# AD5 FAIL# AD6 LRST# AD7 P_INTC# AD8 AD9 P_AD31 AD10 P_AD28 AD11 ...
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... Rx I/O Processor at 3.3 V Table 13. 352-Lead HL-PBGA Pinout — Ballpad Number Order (Sheet Ball # Signal AE10 P_AD26 AE11 P_C/BE3# AE12 P_AD22 AE13 P_AD19 AE14 P_AD16 AE15 P_IRDY# AE16 P_STOP# AE17 P_SERR# AE18 P_AD15 AE19 P_AD12 AE20 P_AD9 AE21 P_AD7 AE22 ...
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... The center of the die gives a more accurate measurement and less variation as the boundary condition changes. ADVANCE INFORMATION i960 • Attach the thermocouple bead or junction at a 90° angle by an adhesive bond (such as thermal epoxy or heat-tolerant tape) to the package top surface ...
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... Rx I/O Processor at 3.3 V 3.2.2 Thermal Analysis This thermal analysis is based on the following assumptions: • Power dissipation is a constant 5 W. • Maximum case temperature is 95° C. Table 14 lists the case-to-ambient thermal resis- tances of the 80960RP for different air flow rates with and without a heat sink. ...
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... Dimensions (mm) Heatsink: 2338B 12.6 BGA Clip: 20812-2 T705 NA Heatsink: 40 364424B00032 ® i960 Rx I/O Processor at 3.3 V Product Description Thermalloy Heatsink; use with BGA Clip and Parker Chromerics Thermflow tape Thermflow tape; use with Thermalloy BGA Clip AAVID Heatsink; use with pre-applied thermal ...
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... Rx I/O Processor at 3.3 V 4.0 ELECTRICAL SPECIFICATIONS 4.1 Absolute Maximum Ratings Parameter Maximum Rating 125 C Storage Temperature – Case Temperature Under Bias 0 4.6 V Supply Voltage wrt. V – 6.5 V Supply Voltage wrt – SS CC5 0 Voltage on Any Ball wrt. V – ...
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... Memory Controller signals capable of high drive are MA11:0, CAS7:0#, RAS3:0#, DWE1:0#. ADVANCE INFORMATION Table 18. DC Characteristics Min Max -0.5 0.8 2 2 0.45 2 0.55 2.4 0.45 2.4 0.45 2.4 0. ® i960 Rx I/O Processor at 3.3 V Units Notes V (1) V ( -200 ...
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... Rx I/O Processor at 3.3 V Symbol I Input Leakage Current for each signal except LI1 PCI Bus Signals, LOCK#/ONCE#, WIDTH/HLTD0, WIDTH/HLTD1/RETRY, BLAST#, D/C#/RST_MODE#, DEN#,TMS, TRST#, TDI I Input Leakage Current for LOCK#/ONCE#, LI2 WIDTH/HLTD0, WIDTH/HLTD1/RETRY, BLAST#, D/C#/RST_MODE#, DEN#, TMS, TRST#, TDI ...
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... V/ns 4 V/ns Min Table 23, Relative Output Timings (pg. 45). . Float delay is not tested, but is designed 45). ® i960 Rx I/O Processor at 3.3 V Notes (1) Adjacent Clocks (2,3) Measured at 1.5 V (2,3) Measured at 1.5 V (2,3) 0 2.4 V (2,3) 2 0.4 V (2,3) Max Units Notes 15.5 ns (1,2,5) +15 ns (2, (2,5) 12 ...
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... Rx I/O Processor at 3.3 V Table 22. Synchronous Input Timings Sym T Input Setup to S_CLK — NMI#, XINT7:4#, S_INT[A:D]#/XINT3:0#, IS1 DP3:0# T Input Setup to S_CLK — for all accesses except Expansion ROM IS1A Accesses — AD31:0 only T Input Setup to S_CLK during Expansion ROM Accesses — ...
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... Output switching between V maximium and V CC3 ADVANCE INFORMATION Table 23. Relative Output Timings Min Max Units Min 2 2 0.5Tc+2 0.5Tc ® i960 Rx I/O Processor at 3.3 V Notes ns (1,2,4) ns Equal Loading (1,2,4) ns Equal Loading (1,3,4) Max Units Notes 0.5Tc+8 ns 1,2 0.5Tc+ ...
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... Rx I/O Processor at 3.3 V Table 25. Fast Page Mode Interleaved DRAM Output Timings Symbol Description T RAS3:0# Rising and Falling edge Output Valid Delay OV12 T CAS7:0# Rising Edge Output Valid Delay OV13 T CAS7:0# Falling Edge Output Valid Delay OV14 T MA11:0 Output Valid Delay-Row Address ...
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... Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of an S_CLK period. For testing purposes, the signal is specified relative to the rising edge of S_CLK with the 0.5Tc period offset. 2. Output switching between V maximium and V CC3 ADVANCE INFORMATION ® i960 Min 2 0.5Tc 0.5Tc+2 ...
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... Rx I/O Processor at 3.3 V 4.4.3 Boundary Scan Test Signal Timings Table 29. Boundary Scan Test Signal Timings Symbol Parameter T TCK Frequency BSF T TCK High Time BSCH T TCK Low Time BSCL T TCK Rise Time BSCR T TCK Fall Time BSCF T Input Setup to TCK — TDI, ...
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... ADVANCE INFORMATION Parameter 2 C Interface Signal Timings Std. Mode Min Max 0 100 4.7 4 4.7 4 4.7 0 250 1000 300 4 ® i960 Rx I/O Processor at 3.3 V Min Max Units Notes Fast Mode Units Notes Min Max ...
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... Rx I/O Processor at 3.3 V 4.5 AC Test Conditions The AC Specifications in Section 4.4, Targeted AC Specifications (pg. 37) indicated in Figure 8. Output Ball 4.6 AC Timing Waveforms for all signals Figure 8. AC Test Load Figure 9. S_CLK, TCLK Waveform ADVANCE INFORMATION are tested with the 50 pF load 2 ...
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... S_CLK Figure 10. T S_CLK Figure 11. T ADVANCE INFORMATION i960 1.5V 1.5V T Min Max T OVX OVX 1.5V Valid Output Delay Waveform OV 1.5V 1. Output Float Waveform OF ® Rx I/O Processor at 3.3 V 1.5V 45 ...
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... Rx I/O Processor at 3.3 V S_CLK Figure 12. T S_CLK ALE 1.5V AD31:0 1.5V Figure 13 1.5V 1.5V T IHX T ISX Valid 1.5V and T Input Setup and Hold Waveform 1.5V 1.5V T LXL 1.5V Valid T LXA 1.5V Valid and T Relative Timings Waveform LXL LXA ADVANCE INFORMATION 1.5V 1.5V ...
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... T T LOW BUF SCL T HDSTA Stop Start Figure 15. I ADVANCE INFORMATION 1.5V 1.5V T OVX Valid T DXD T OVX HDDAT HIGH SUDAT SUSTA 2 C Interface Signal Timings ® i960 Rx I/O Processor at 3 HDSTA SP T SUSTO Stop Repeated Start 47 ...
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... Rx I/O Processor at 3.3 V 4.7 Memory Controller Output Timing Waveforms S_CLK AD31:0 ADDR MA11:0 ROW ALE ADS# W/R# BLAST# DT/R# DEN# DWE0# RAS0# CAS3:0# LRDYRCV# RDYRCV# Figure 16. Fast Page-Mode Read Access, Non-Interleaved, 2,1,1,1 Wait State, 32-Bit 80960 Local Bus ...
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... LRDYRCV# RDYRCV# Figure 17. Fast Page-Mode Write Access, Non-Interleaved, 2,1,1,1 Wait States, 32-Bit 80960 Local Bus ADVANCE INFORMATION DATA DATA DATA OUT OUT OUT COL COL COL ® i960 Rx I/O Processor at 3 DATA OUT COL 49 ...
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... Rx I/O Processor at 3.3 V S_CLK AD[31:0] RAS[n]# RAS[n+1#] MA[11:0] DALE[0]# CAS[3:0]# LEAF[0]# DALE[1]# CAS[7:4]# LEAF[1]# DWE[1:0]# Figure 18. FPM DRAM System Read Access, Interleaved, 2,0,0,0 Wait States ADDR IN IN COL ROW COL ADVANCE INFORMATION ...
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... T A S_CLK AD[31:0] ADDR RAS[n]# RAS[n+1]# ROW MA[11:0] DALE[0]# CAS[3:0]# LEAF[0]# DALE[1]# CAS[7:4]# LEAF[1]# DWE[1:0]# Figure 19. FPM DRAM System Write Access, Interleaved, 1,0,0,0 Wait States ADVANCE INFORMATION i960 DATA DATA DATA DATA OUT OUT OUT COL COL ® Rx I/O Processor at 3 ...
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... Rx I/O Processor at 3 S_CLK RAS# MA[11:0] CAS# AD[31:0] ADDR S_CLK RAS# MA[11:0] CAS# AD[31:0] ADDR COL COL COL ROW COL Figure 20. EDO DRAM, Read Cycle COL ROW COL COL COL ...
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... WRITE CAS# AD[31:0] ADDR Figure 23. BEDO DRAM, Write Cycle ADVANCE INFORMATION COL COL COL COL COL ROW COL COL COL OUT OUT OUT OUT ® i960 Rx I/O Processor at 3 COL ...
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... Rx I/O Processor at 3.3 V S_CLK CE[1]# MA[11:0] MWE[3:0]# AD[31:0] Figure 24. 32-Bit Bus, SRAM Read Accesses with 0 Wait States S_CLK CE[1]# MA[11:0] MWE[3:0]# AD[31:0] Figure 25. 32-Bit Bus, SRAM Write Accesses with 0 Wait States ADDR ADDR ADDR ADDR ADDR ...
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... ADS# BE3:0# WIDTH1:0 D/C# W/R# BLAST# DT/R# DEN# LRDYRCV# RDYRCV# Figure 26. Non-Burst Read and Write Transactions without Wait States, 32-Bit 80960 Local Bus ADVANCE INFORMATION Invalid ADDR In 10 ® i960 Rx I/O Processor at 3 DATA Out ...
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... Rx I/O Processor at 3 S_CLK AD31:0 ADDR ALE ADS# BE3:0# WIDTH1:0 D/C# W/R# BLAST# DT/R# DEN# LRDYRCV# RDYRCV# Figure 27. Burst Read and Write Transactions without Wait States, 32-Bit 80960 Local Bus DATA ADDR In In Out 1 0 ADVANCE INFORMATION ...
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... BE3:0# WIDTH1:0 D/C# W/R# BLAST# DT/R# DEN# LRDYRCV# RDYRCV# Figure 28. Burst Write Transactions with 2,1,1,1 Wait States, 32-Bit 80960 Local Bus ADVANCE INFORMATION DATA DATA DATA Out Out Out 1 0 ® i960 Rx I/O Processor at 3 DATA Out 57 ...
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... Rx I/O Processor at 3 S_CLK AD31:0 ADDR ALE ADS# BE1/A1 BE0/A0# WIDTH1:0 D/C# W/R# BLAST# DT/R# DEN# LRDYRCV# RDYRCV# Figure 29. Burst Read and Write Transactions without Wait States, 8-Bit 80960 Local Bus DATA ADDR In In Out ...
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... AD31:0 ALE ADS# 0 BE1/A1# BE3# BE0# WIDTH1:0 D/C# W/R# BLAST# DT/R# DEN# LRDYRCV# RDYRCV# Figure 30. Burst Read and Write Transactions with 1, 0 Wait States and Extra Tr State on Read, 16-Bit 80960 Local Bus ADVANCE INFORMATION i960 ADDR ® ...
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... Rx I/O Processor at 3 S_CLK D AD31 ALE ADS# BE3: WIDTH1:0 D/C# W/R# BLAST# DT/R# DEN# LRDYRCV# RDYRCV# Figure 31. Bus Transactions Generated by Double Word Read Bus Request, Misaligned One Byte From Quad Word Boundary, 32-Bit 80960 Local Bus ...
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... The processor asserts HOLDA to grant the bus on the same edge in which it recognizes HOLD if the last state was T or the last T i the same edge in which it recognizes the deassertion of HOLD. Figure 32. HOLD/HOLDA Waveform For Bus Arbitration ADVANCE INFORMATION i960 ...
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... Rx I/O Processor at 3.3 V Figure 33. 80960 Core Cold Reset Waveform 62 ADVANCE INFORMATION ...
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... Figure 34. 80960 Local Bus Warm Reset Waveform ADVANCE INFORMATION ® i960 Rx I/O Processor at 3 ...
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... During the manufacturing process, values characterizing the i960 Rx I/O processor type and stepping are programmed into the memory-mapped registers. The i960 Rx I/O processor contains two read-only device ID MMRs. One holds the Processor Device ID (PDIDR - 0000 1710H) and the other holds the i960 Core Processor Device ID (DEVICEID - FF00 8710H). During initialization, the PDIDR is placed in g0. ...