MAX3748HETE#G16 Maxim Integrated Products, MAX3748HETE#G16 Datasheet - Page 7

• Manufacturer Part Number: MAX3748HETE#G16
• Description: IC AMP LIMITING 16-TQFN-EP
• Manufacturer: Maxim Integrated Products
• Type: Limiting Amplifierr

Specifications of MAX3748HETE#G16

• Applications: Optical Networks
• Mounting Type: Surface Mount
• Package / Case: 16-TQFN Exposed Pad
• Amplifier Type: Limiting
• Supply Voltage Range: 2.97V To 3.63V
• Amplifier Case Style: TQFN
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +85°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The limiting amplifier consists of an input buffer, a multi-
stage amplifier, offset correction circuitry, an output
buffer, power-detection circuitry, and signal-detect cir-
cuitry (see Functional Diagram ).
The input buffer is shown in Figure 3. It provides 50Ω
termination for each input signal IN+ and IN-. The
MAX3748/MAX3748A can be DC- or AC-coupled to a
TIA (TIA output offset degrades receiver performance if
DC-coupled). The MAX3748/MAX3748A CML input
buffers are optimized for the MAX3744 TIA.
The high-bandwidth gain stage provides approximately
53dB of gain.
The MAX3748/MAX3748A are susceptible to DC offsets
in the signal path because they have high gain. In com-
munication systems using NRZ data with a 50% duty
cycle, pulse-width distortion present in the signal or
generated in the transimpedance amplifier appears as
an input offset and is reduced by the offset correction
Figure 1. Power-Supply Current Measurement
_______________________________________________________________________________________________________
V
CC
MAX3748A
MAX3748
I
CC
(SUPPLY CURRENT)
50Ω
Detailed Description
Offset Correction Loop
50Ω
R
TH
Input Buffer
Compact 155Mbps to 4.25Gbps
I
OUTPUT CURRENT)
OUT
Gain Stage
(CML
loop. For Gigabit Ethernet and Fibre Channel applica-
tions, no capacitor is required. For SONET applications,
C
mines the lower 3dB frequency of the data path.
Figure 2. LOS Deassert Threshold Set 1dB Below the Minimum
by Receiver Sensitivity (for Selected R
Figure 3. CML Input Buffer
AZ
IN+
IN-
0.25pF
0.25pF
0V
= 0.1µF is recommended. This capacitor deter-
V
IN
STRUCTURES
1dB
6dB
ESD
Limiting Amplifier
POWER-DETECT WINDOW
MAX DEASSERT LEVEL
MIN DEASSERT LEVEL
SIGNAL ON
50Ω
V
CC
50Ω
TH
)
75kΩ
SIGNAL OFF
TIME
7