DS2172 Dallas Semiconductor, DS2172 Datasheet
DS2172
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DS2172 Summary of contents
Page 1
... Two categories of test pattern generation (Pseudo-random and Repetitive) conform to CCITT/ITU O.151, O.152, O.153, and O.161 standards. The DS2172 operates at clock rates ranging from MHz. This wide range of operating frequency allows the DS2172 to be used in existing and future test equipment, transmission facilities, switching equipment, multiplexers, DACs, Routers, Bridges, CSUs, DSUs, and CPE equipment ...
Page 2
... Injecting errors allows users to stress communication links and to check the functionality of error monitoring equipment along the path. 1.5 POWER-UP SEQUENCE On power-up, the registers in the DS2172 will random state. The user must program all the internal registers to a known state before proper operation can be insured ...
Page 3
... DS2172 FUNCTIONAL BLOCK DIAGRAM Figure 1 DS2172 PATTERN GENERATION BLOCK DIAGRAM Figure 2 NOTES: 1. Tap A always equals length (N-1) of pseudorandom or repetitive pattern. 2. Tab B can be programmed to any feedback tap for pseudorandom pattern generation DS2172 ...
Page 4
... BCR and BECR registers and clears the internal count registers logically OR’ed with control bit PCR.4. Should be tied not used. SS Receive Loss Of Sync. Indicates the real time status of the receive synchronizer. Active high output DS2172 , ADx, TDATA, RLOS). INT (DS), RD ...
Page 5
... R Bit Counter Register 0. NOTE: 1. The Test Register must be set to 00 hex to insure proper operation of the DS2172. Receive Load. A positive-going edge loads the previous 32 bits of data received at RDATA into the Pattern Receive Registers logically OR’ed with control bit PCR.3. Should be tied to V Receive Data ...
Page 6
... Addresses must be valid prior to the falling edge of ALE(AS), at which time the DS2172 latches the address from the AD0 to AD7 pins. Valid write data must be present and held stable during the later portion of the DS or pulses ...
Page 7
... Not Assigned. Should be set to 0 when written to. Not Assigned. Should be set to 0 when written to. Not Assigned. Should be set to 0 when written to. Polynomial Tap Bit 4. Polynomial Tap Bit 3. Polynomial Tap Bit 2. Polynomial Tap Bit 1. Polynomial Tap Bit DS2172 (LSB) LB2 LB1 LB0 (LSB) PT2 PT1 PT0 ...
Page 8
... PATTERN CONTROL REGISTER The Pattern Control Register (PCR) is used to configure the operating parameters of the DS2172 and to control the patterns being generated and received. Also the PCR is used to control the pattern synchronizer and the error and bit counters. PCR: PATTERN CONTROL REGISTER (Address=06 Hex) ...
Page 9
... ERROR INSERT REGISTER The Error Insertion Register (EIR) controls circuitry within the DS2172 that allows the generated pattern to be intentionally corrupted. Bit errors can be inserted automatically at regular intervals by properly programming the EIR0 to EIR2 bits or bit errors can be inserted at random (under microcontroller control) via the EIR ...
Page 10
... DS2172 TINV RINV ...
Page 11
... The Status Register bit BECOF is set when this 32-bit register overflows. Upon an overflow condition, the user must clear the BECR by either toggling the LC bit or pin. The DS2172 latches the bit error count into the BECR registers and clears the internal bit error count when either the PCR.4 bit or the LC input pin toggles from low to high ...
Page 12
... DS2172. Asserting the RL bit (PCR.3) or pin during an out-of -sync condition (SR will latch the previous 32 bits of data received at RDATA into the PRR registers. When the DS2172 is in sync (SR asserting RL will latch the pattern that to which the device has established synchronization. Since the receiver has no knowledge of the start or end of the pattern, the data in the PRR registers will have no particular alignment ...
Page 13
... Bit Error Count Overflow. Set when the 32-bit BECR overflows. Sync. Real time status of the synchronizer (this bit is not latched). Will be set when synchronization is declared. Will be cleared when 6 or more bits out of 64 are received in error (if PCR (LSB) BCOF BECOF SYNC DS2172 ...
Page 14
... Receive Loss Of Sync interrupt masked 1 = interrupt enabled Bit Error Detection interrupt masked 1 = interrupt enabled Bit Counter Overflow interrupt masked 1 = interrupt enabled Bit Error Count Overflow interrupt masked 1 = interrupt enabled Sync interrupt masked 1 = interrupt enabled (LSB) BCOF BECOF SYNC DS2172 ...
Page 15
... TO +85ºC for DS2172TN) SYMBOL MIN TYP 4.50 DD SYMBOL MIN TYP OUT (0ºC TO 70ºC for DS2172T; VDD=5V 10%; -40ºC TO +85ºC for DS2172TN; VDD=5V 10%) SYMBOL MIN TYP - DS2172 MAX UNITS NOTES V +0 ...
Page 16
... Delay Time DS ALE Rise Pulse Width AS or ALE High Delay Time ALE to DS, RD Output Data Delay Time from Data Setup Time (0ºC to 70ºC for DS2172T; V -40ºC to +85ºC for DS2172TN; V SYMBOL MIN t 200 CYC PW 100 High EL ...
Page 17
... INTEL BUS READ AC TIMING (BTS=0) Figure DS2172 ...
Page 18
... INTEL BUS WRITE AC TIMING (BTS=0) Figure 4 MOTOROLA BUS AC TIMING (BTS=1) Figure DS2172 ...
Page 19
... SU1 t 0 HD1 t 4 SU2 t 0 HD2 t 25 WRL (0ºC TO 70ºC for DS2172T; VDD=5V 10%; -40ºC TO +85ºC for DS2172TN; VDD=5V 10%) SYMBOL MIN TYP WTL t 4 ...
Page 20
... TDIS is low about the rising edge of TCLK. TRANSMIT AC TIMING FOR THE TL INPUT Figure 8 NOTE: The rising edge of TL causes the internal pattern generation circuitry to be reloaded; the first bit of the new pattern (the shaded one) will appear after two TCLK periods DS2172 ...
Page 21
... DS2172 32-PIN TQFP DIM MIN MAX A - 1.20 A1 0.05 0.15 A2 0.95 1.05 D 8.80 9.20 D1 7.00 BSC E 8.80 9.20 E1 7.00 BSC L 0.45 0.75 e 0.80 BSC B 0.30 0.45 C 0.09 0. DS2172 ...