AM79C940KC/W Advanced Micro Devices, AM79C940KC/W Datasheet
AM79C940KC/W
Related parts for AM79C940KC/W
AM79C940KC/W Summary of contents
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FINAL Am79C940 Media Access Controller for Ethernet (MACE™) DISTINCTIVE CHARACTERISTICS Integrated Controller with Manchester encoder/decoder and 10BASE-T transceiver and AUI port Supports IEEE 802.3/ANSI 8802-3 and Ethernet standards 84-pin PLCC and 100-pin PQFP Packages 80-pin Thin Quad Flat Pack (TQFP) ...
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The MACE device provides a complete Ethernet node solution with an integrated 10BASE-T transceiver, and supports up to 25-MHz system clocks. The MACE device embodies the Media Access Control (MAC) and Physical Signaling (PLS) sub-layers of the IEEE 802.3 standard, ...
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BLOCK DIAGRAM DBUS 15–0 ADD 4–0 R/W CS FDS DTV Bus EOF Interface RDTREQ Unit TDTREQ BE 1–0 INTR SCLK EDSEL TC SLEEP RESET JTAG PORT CNTRL TDI TDO TCK TMS Notes: 1. Only one of the network ports AUI, ...
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TABLE OF CONTENTS AM79C940 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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TMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Receive Status Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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CONNECTION DIAGRAMS PL 084 PLCC PACKAGE 11 10 SRDCLK 12 EAM/R 13 SRD 14 SF/BD 15 RESET 16 SLEEP INTR DBUS0 DBUS1 23 DBUS2 24 DBUS3 25 DBUS4 26 ...
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CONNECTION DIAGRAMS PQR100 PQFP PACKAGE SRDCLK 5 6 EAM/R 7 SRD 8 SF/BD 9 RESET 10 SLEEP INTR DBUS0 DBUS1 17 ...
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CONNECTION DIAGRAMS PQT080 TQFP PACKAGE SRDCLK 1 EAM/R 2 SF/BD 3 RESET 4 SLEEP INTR 7 ...
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ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM79C940 V C DEVICE NUMBER/DESCRIPTION (include revision letter) Am79C940 Media Access Controller for Ethernet ...
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PIN/PACKAGE SUMMARY (PLCC) PLCC Pin # Pin Name 1 DXCVR 2 EDSEL TXDAT+ 5 TXDAT– STDCLK 8 TXEN/TXEN 9 CLSN 10 RXDAT 11 RXCRS 12 SRDCLK 13 EAM/R 14 SRD 15 SF/BD ...
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PIN/PACKAGE SUMMARY (continued) PLCC Pin # Pin Name 45 BE1 46 SCLK 47 TDTREQ 48 RDTREQ 49 ADD0 50 ADD1 51 ADD2 52 ADD3 53 ADD4 54 R RXPOL 57 LNKST 58 TDO 59 TMS 60 TCK ...
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PIN/PACKAGE SUMMARY (PQFP) (continued) PQFP Pin # Pin Name SHDCLK 6 EAM/R 7 SRD 8 SF/BD 9 RESET 10 SLEEP 11 DVDD 12 INTR DBUS0 ...
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PIN/PACKAGE SUMMARY (continued) PQFP Pin # Pin Name 43 SCLK 44 TDTREQ 45 RDTREQ 46 ADD0 47 ADD1 48 ADD2 49 ADD3 50 ADD4 R RXPOL 58 LNKST ...
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PIN/PACKAGE SUMMARY (continued) PQFP Pin # Pin Name 86 CI– DXCVR 91 EDSEL TXDAT+ 94 TXDAT– STDCLK 97 TXEN/TXEN 98 CLSN 99 RXDAT ...
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PIN/PACKAGE SUMMARY (TQFP) (continued) TQFP # Pin Name Pin Function 1 SRDCLK Serial Receive Data Clock 2 EAM/R External Address Match/Reject 3 SF/BD Start Frame/Byte Delimiter 4 RESET Reset 5 SLEEP Sleep Mode 6 DVDD Digital Power 7 INTR Interrupt ...
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PIN SUMMARY Pin Name Pin Function Attachment Unit Interface (AUI) DO+/DO– Data Out DI+/DI– Data In CI+/CI– Control In RXCRS Receive Carrier Sense TXEN Transmit Enable CLSN Collision DXCVR Disable Transceiver STDCLK Serial Transmit Data Clock SRDCLK Serial Receive Data ...
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PIN SUMMARY (continued) Pin Name Pin Function External Address Detection Interface (EADI) SF/BD Start Frame/Byte Delimiter SRD Serial Receive Data EAM/R External Address Match/Reject SRDCLK Serial Receive Data Clock Host System Interface DBUS 15–0 Data Bus ADD4–0 Address R/W Read/Write ...
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PIN DESCRIPTION Network Interfaces The MACE device has five potential network inter- faces. Only one of the interfaces that provides physical network attachment can be used (active) at any time. Selection between the AUI, 10BASE-T, DAI or GPSI ports is ...
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TXEN/TXEN Transmit Enable (Output) When the AUI port is selected (PORTSEL [1-0] = 00), an output indicating that the AUI DO differential output has valid Manchester encoded data is presented. When the 10BASE-T port is selected (PORTSEL [1-0] = 01), ...
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PORTSEL SLEEP [1–0] ENPLSIO Notes: 1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14). 2. This pin should be externally terminated, ...
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DXCVR Configuration—SLEEP Operation Sleep RWAKE AWAKE ASEL Pin Bit Bit Bit ...
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INTERFACE TXD+, TXD– Transmit Data (Output) 10BASE–T port differential drivers. TXP+, TXP– Transmit Pre-Distortion (Output) Transmit wave form differential driver for pre-distortion. RXD+, RXD– Receive Data (Input) 10BASE–T port differential receiver. These pins should be externally terminated to reduce ...
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CLSN Collision (Input/Output) An external indication that a collision condition has been detected by the (internal or external) Medium Attachment Unit (MAU), and that signals from two or more nodes are present on the network. When the AUI port is ...
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PORTSEL SLEEP [1- Note: 1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14). PORTSEL SLEEP [1- ...
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HOST SYSTEM INTERFACE DBUS15-0 Data Bus (Input/Output/3-state) DBUS contains read and write data to and from internal registers and the Transmit and Receive FIFOs. ADD4-0 Address Bus (Input) ADD is used to access the internal registers and FIFOs to be ...
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CS Chip Select (Input) Used to access the MACE device FIFOs and internal registers locations using the ADD address bus. The FIFOs may alternatively be directly accessed without supplying the FIFO address, by using the FDS and R/W pins. INTR ...
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MAC configuration Control Register of the internal analog circuits allow for stabilization. If the AWAKE bit is set prior to the activation of SLEEP, the 10BASE–T receiver and the LNKST output ...
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FIFO. In general, there are ways to ensure that a transfer is always valid; so this pin is not required in many designs. For instance, the TDTREQ and RDTREQ pins can be used to monitor the state of the FIFOs ...
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FUNCTIONAL DESCRIPTION The Media Access Controller for Ethernet (MACE) chip embodies the Media Access Control (MAC) and Phys- ical Signaling (PLS) sub-layers of the 802.3 Standard. The MACE device provides the IEEE defined Attach- ment Unit Interface (AUI) for coupling ...
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Transmit FIFO will not return DTV if ENXMT is dis- abled, and no data will be written. The MACE device will commence the preamble sequence once the Transmit Start Point (XMTSP bits in BIU Configuration Control register) threshold is reached ...
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For BSWP = 0, data can be presented on DBUS7-0 using BE0 or DBUS15-8 using BE1. For BSWP = 1, data can be presented ...
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TDTREQ would remain de-asserted. Hence for byte wide data transfers, the XMTFW should be pro- grammed to the write cycle limit, or the host should ensure that sufficient data will be written to the XMTFIFO after TDTREQ ...
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Receive FIFO provides to the host system. The description and table below outline the point at which RDTREQ will be asserted when the first duration of the packet has been received and when ...
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RCVFIFO before the RCVFS bytes are available. Media Access Control (MAC) The Media Access Control engine is the heart of the MACE device, incorporating the essential protocol requirements for ...
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In addition, multiple physical addresses can be constructed (perfect address filtering) using external logic in conjunction with the EADI interface. Error Detection (Physical Medium Transmission Errors) The MACE device provides several facilities which report and recover from ...
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Upon completing a transmission, start timing the interpacket gap, as soon as transmitting and carrier Sense are both false. (2) When timing an interFrame gap following r ece pti on the i nte ...
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MORE will be clear), and the transmit mes- sage will be flushed from the XMTFIFO, either by reset- ting the XMTFIFO (if no End-of-Frame tag exists moving the XMTFIFO read pointer to the next free lo- ...
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Parameter 1. Parallel Resonant Frequency 2. Resonant Frequency Error ( pF) 3. Change in Resonant Frequency With Respect To Temperature ( pF)* 4. Crystal Capacitance 5. Motional Crystal Capacitance (C1) 6. Series Resistance 7. Shunt Capacitance ...
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DI Input Signal Conditioning Transient noise pulses at the input data stream are rejected by the Noise Rejection Filter. Pulse width rejection is proportional to transmit data rate. DC inputs more negative than minus 100 also suppressed. ...
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SRDCLK strobes the data receiver output at 1/4 bit time to determine the value of the Manchester bit and clocks the data out on SRD on the following SRDCLK. The data receiver also gener- ates ...
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Frame Status (bit 7) after the packet has been transmitted. Digital Attachment Interface (DAI) The Digital Attachment Interface is a simplified electri- cal attachment specification which allows MAUs which do not require the DC isolation between the MAU and ...
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Filter and transformer loss are not specified. The 10BASE-T MAU receiver squelch levels are defined to ac- count for a 1dB insertion loss at 10 MHz, which is typical for the type of receive filters/transformers recommended (see the Appendix ...
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Positive Link Test pulses are defined as received signal with a positive amplitude greater than 520 mV (LRT = LOW) with a pulse width of 60 ns-200 ns. This positive excursion may be followed by a negative excursion. This definition ...
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CLSN pin after each transmission. In DAI mode, SEQ Test has no relevance. Jabber Function The Jabber function inhibits the twisted pair transmit function of the MACE device if the TXD /TXP circuits ...
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EAR must have a pulse width of at least 200 ns. Note that setting the PROM bit (MAC Configuration Control) will cause all receive packets to be received, Internal/External Address Recognition Capabilities PROM M/R EAM ...
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After hardware or software reset, the IDCODE instruc- tion is always invoked. The decoding logic provides signals to control the data flow in the DATA registers according to the current instruction. Each Boundary Scan Register (BSR) cell also has two ...
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Either the FIFO Direct or Register Address modes can be interleaved at any time to read the Receive Frame Status, although this is considered ...
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Reinitialization The SWRST bit in the BIU Configuration Control (BIUCC) register can be set to reset the MACE device into a defined state for reinitialization. The same sequence described in the initialization section can be used. The 1 ms delay ...
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FIFO is controlled by the XMTFW bits in the FIFO Con- figuration Control register. TDTREQ will be asserted when one of the following conditions is true: The number of bytes free in the Transmit FIFO rel- ative to the current ...
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Minimum frame size (excluding preamble, including FCS) 64 bytes Preamble/SFD size 8 bytes FCS size 4 bytes To be classed as a minimum size frame at the receiver, the transmitted frame must contain: Preamble + (Min Frame Size + FCS) ...
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FIFO will not be overwritten until at least 64 bytes (512 bits) of data have been successfully transmitted onto the network. This criteria will be met, regardless of whether the transmit frame was the first (or only) frame in ...
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FIFO and does not get transmitted as a whole frame recommended that the host clear the ...
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Transmit FIFO. RECEIVE OPERATION The receive operation and features of the MACE de- vice are controlled by programmable options. These options are programmed through the BIU, FIFO and MAC Configuration ...
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Bits Bits Preamble SYNCH 1010....1010 10101011 Start of Packet at Time= 0 Increasing Time 802.3 Packet and Length Field Transmission Order subsequent packets that would have normally been passed to the host, and are now ignored due to ...
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The Receive Frame Status is a single location which must be read four times to allow the four bytes of status information associated with each frame to be read. Further data read operations from the Receive FIFO using the ...
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Failure to read packet data from the Receive FIFO will eventually cause an overflow condition. The FIFO will maintain any previously completed packet(s), which can be read by the host at its convenience. However, packet data on the network ...
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XMTFIFO, by asserting the EOF signal. Transmit Frame Control (XMTFC) The Transmit Frame Control register is latched inter- nally on the last write to the Transmit FIFO for each ...
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XMTFS has been read. The MACE device does not retry after a late collision. Bit 4 MORE More. Indicates that more than one retry was needed to transmit the frame. ONE, MORE and RTRY are mutually exclusive. ...
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RCVFIFO to underflow, and will be indicated by DTV being invalid. The MACE device will no longer be able to reject runts in this mode, this responsibility is ...
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Receive FIFO it- self. OFLO is indicated on the re- ceive frame ...
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Missed Packet Count (MPC) register will be incremented for frames which match the internal address(es) of the MACE device. Bit 3–0 XMTFC Transmit Frame Count. The [3–0] (read only) count of ...
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RCVCC (REG ADDR 27) is free running. RCVCCO is READ/CLEAR only set by the MACE device and reset when read. Writing has no effect also cleared by asserting the RESET pin or SWRST bit. Bit 3 ...
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MACE device regardless of the state of the RCVCCO bit, if RCVCCOM is set cleared by activation of the RESET pin or SWRST bit. Bit 3 RNTPCOM Runt Packet Count Overflow Mask. RNTPCOM is the mask for ...
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Transmit Start Point XMTSP [1- Bit 3-1 RES Reserved. Read as zeroes. Al- ways write as zeroes. Bit 0 SWRST Software Reset. When set, pro- vides an equivalent of the hard- ware RESET pin function. All ...
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Transmit FIFO Watermark bits. The XMTFW can be written at any point, and will be read back as written. However, the new value in the XMTFW bits will be ignored until XMTFWU is set (or the transmit path is reset ...
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EMBA is cleared by activation of the RESET pin or SWRST bit. Bit 4 RES Reserved. Read as zeroes. Always write as zeroes. Bit 3 DRCVPA Disable Receive Address. When set, the physical address detection (Station or node ...
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PORTSEL Interface Definitio PORTSEL Active [1–0] Interface 00 AUI 01 10BASE–T 10 DAI Port 11 GPSI Bit 0 ENPLSIO Enable PLS I/O. ENPLSIO is used to enable the optional I/O functions from the PLS function. The following pins are affected ...
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SLEEP. Incoming packet activity will be passed to the EADI port pins permitting detection of spe- cific frame contents used to ini- tiate a wake-up RWAKE must be programmed prior to SLEEP being asserted for ...
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After a hardware or software reset and before the ENRCV bit in the MAC Configuration Con- trol register has been set, the Logical Address can be accessed by setting the LOG ADDR bit in the Internal Address Configuration ...
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Physical Address (PADR [47-00]) (REG ADDR 21 PADR [47–00] This 48-bit value represents the unique node value assigned by the IEEE and used for internal address comparison. After a hardware or software reset and before the ENRCV bit in the ...
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Bit Name Description Bit 7 RTRE Reserved Test Register Enable. Access to the Reserved Test Registers should not be attempt the user. Note that access to the Reserved Test Register may cause damage to the MACE device if ...
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One Internal loopback function in- cludes the MENDEC in the loop. Bit 0 FD_TEST Full Duplex Test. When set, will allow the MACE device to transmit ...
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Register Table Summary Address Mnemonic 0 RCVFIFO 1 XMTFIFO 2 XMTFC 3 XMTFS 4 XMTRC 5 RCVFC 6 RCVFS 7 FIFOFC IMR BIUCC 12 FIFOCC 13 MACCC 14 PLSCC 15 PHYCC 16 CHIPID 17 ...
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Register Bit Summary 16-Bit Registers 0 1 8-Bit Registers Address 2 DRTRY RES 3 XMTSV UFLO 4 EXDEF RES 5 RES RES 6 7 RCVFC [3–0] 8 JAB BABL 9 JABM BABLM 10 XMTSV TDTREQ 11 RES BSWP 12 XMTFW ...
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Programmer’s Register Model Addr Mnemonic 0 RCVFIFO Receive FIFO–16 bits 1 XMTFIFO Transmit FIFO–16 bits 2 XMTFC Transmit Frame Control 80 DRTRY 08 DXMTFC 01 APADXMT 3 XMTFS Transmit Frame Status 80 XMTSV 40 UFLO 20 LCOL 10 MORE 08 ...
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Addr Mnemonic 8 IR Interrupt Register 80 JAB 40 BABL 20 CERR 10 RCVCCO 08 RNTPCO 04 MPCO 02 RCVINT 01 XMTINT 9 IMR Interrupt Mask Register 80 JABM 40 BABLM 20 CERRM 10 RCVCCOM 08 RNTPCOM 04 MPCOM 02 ...
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Programmer’s Register Model (continued) Addr Mnemonic FIFO Configuration Control 12 FIFOCC C0 XMTFW RCVFW XMTFWU 04 RCVFWU 02 XMBRST 01 RCVBRST 13 MACCC Media Access Control (MAC) Configuration Control 80 ...
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Programmer’s Register Model (continued) Addr Mnemonic 15 PHYCC Physical Layer (PHY) Configuration Control 80 LNKFL 40 DLNKTST 20 REVPOL 10 DAPC 08 LRT 04 ASEL 02 RWAKE 01 AWAKE 16 CHIPID Chip Identification Register LSB–CHIPID [7:0] 17 CHIPID Chip Identification ...
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Missing Table Title? Addr Mnemonic 29 UTR User Test Register 80 RTRE 40 RTRD 20 RPA 10 FCOLL 08 RCVFCSE 06 LOOP – Reserved 31 – Reserved SYSTEM APPLICATIONS Host System Examples Motherboard DMA ...
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CLK SCLK DREQ0 DREQ1 EOP DACK0 DACK1 8237 ADSTB DB[7:0] A[7:0] IOW CSMACE D[7:0] Q[7:0] ’373 CC D[7:0] D[7:0] Q[7:0] ’373 CC LATCHHIGHADR D[15:0] A[23:0] System Interface - Motherboard DMA Example SCLK RDTREQ TDTREQ EOF FDS ...
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PC/AT Ethernet Adapter Card SA19-SA0 Remote Boot PROM I S SD7-SD0 SD15-SD8 S CAM System Interface - Simple PC/AT Ethernet Adapter Card Example 82 IEEE Address PROM D7-D0 Am79C940 D15-D8 AUI DB15 RJ45 TP GPSI/DAI Header 16235D-12 ...
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NETWORK INTERFACES External Address Detection Interface (EADI) The External Address Detection Interface can be used to implement alternative address recognition schemes outside the MACE device, to complement the physical, logical and promiscuous detection supported internally. EADI Pins SRD SRDCLK SF/BD ...
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Attachment Unit Interface (AUI) The AUI can drive standard drop cable to allow the transceiver to be remotely located typi- cally the case in IEEE 803.3 10BASE5 or thick Ether- net® installations. For ...
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Ethernet Other Slave System I/O Device(s) CPU i.e. SCSI I/O Slave Peripheral Bus Processor 10BASE-T/Unshielded Twisted-Pair Interface RJ45 Am79C9416 Am79C940 MACE Unshielded Twisted-Pair 16235D-16 85 ...
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ANLG +5 V 0.1 F AVDD AVSS TXD+ TXP+ TXD- TXP- RXD+ RXD- LNKST RXPOL Am79C940 DXCVR Optional Notes: 1. Compatible filter modules, with a brief description of package type and features are included in the following section. 2. The ...
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ANLG +5 V 0.1 F AVDD AVSS TXD+ TXP+ TXD- TXP- RXD+ RXD- LNKST RXPOL Am79C940 DO+ DO– DI+ DI- CI+ CI- 40.2 0.1 F Optional : Notes 1. Compatible filter modules, with a brief description of package type and ...
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MACE Compatible 10BASE-T Filters and Transformers The table below provides a sample list of MACE com- patible 10BASE-T filter and transformer modules available from various vendors. Contact the respective manufacturer for a complete and updated listing of components. Manufacturer Part ...
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MACE Compatible DC/DC Converters The table below provides a sample list of MACE com- patible DC/DC converters available from various ven- dors. Contact the respective manufacturer for a complete and updated listing of components. Manufacturer Part # Halo Electronics DCU0-0509D ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . - +150 C Ambient Temperature . . . . . . . . . . . . . . . . ...
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DC CHARACTERISTICS (Continued) Parameter Symbol Parameter Description Transmit Differential I AODOFF Output Idle Current DO Common Mode V AOCM Output Voltage DO Differential Output Voltage Imbalance Receive Data Differential V ATH Input Threshold DI and CI Differential ...
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DC CHARACTERISTICS (Continued) Parameter Symbol Parameter Description RXD Post-Squelch V LTHS– Negative Threshold (Peak) V RXD Switching Threshold RXDTH TXD and TXD Output V TXH HIGH Voltage TXD and TXD Output V TXL LOW Voltage TXD and TXD Differential V ...
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AC CHARACTERISTICS (Unless otherwise noted, parametric values are the same between Commercial devices and Industrial devices.) Parameter No. Symbol Parameter Description Clock and Reset Timing 1 t SCLK period SCLK 2 t SCLK LOW pulse width SCLKL 3 t SCLK ...
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AC CHARACTERISTICS (continued) Parameter No. Symbol Parameter Description AUI Timing 53 t XTAL1 (externally driven DOTD rise time (10% to 90%) DOTR fall time (10% to 90%) DOTF rise ...
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AC CHARACTERISTICS (continued) Parameter No. Symbol GPSI Clock Timing 17 t STDCLK period STDC 18 t STDCLK low pulse width STDCL 19 t STDCLK high pulse width STDCH 20 t STDCLK rise time STDCR 21 t STDCLK fall time STDCF ...
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AC CHARACTERISTICS (continued) Parameter No. Parameter Description Symbol IEEE 1149.1 Timing 109 t TCK Period, 50% duty cycle (+5%) TCLK 110 t TMS setup to TCK su1 111 t TDI setup to TCK su2 112 t TMS hold time from ...
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BIU Output Valid Delay vs. Load Chart nom+4 nom BIU Output Valid Delay from SCLK (ns) nom-4 nom-8 KEY TO SWITCHING WAVEFORMS WAVEFORM 50 75 100 C L (pF) INPUTS OUTPUTS Must be Will be Steady Steady May Will be ...
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SWITCHING TEST CIRCUITS Sense Point DO+ DO- TXD+ TXD- Includes Test Jig Capacitance Normal and Three-State Outputs AV DD 52.3 Test Point 154 100 AUI DO Switching Test Circuit DV ...
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TXP+ TXP- Includes Test Jig Capacitance AC WAVEFORMS 3 SCLK 4 RESET 11 XTAL1 715 Test Point 715 100 TXP Outputs Test Circuit Clock and Reset Timing ...
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AC WAVEFORMS SCLK TL TH (EDSEL = 0) SCLK TL TH (EDSEL = 1) 31 ADD[4:0] R FDS DBUS[15:0] 50 Word N DTV EOF BE0 Host System Interface—2-Cycle Receive FIFO/Register Read Timing 100 S0 ...
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AC WAVEFORMS SCLK (EDSEL = 0) SCLK (EDSEL = 1) 31 ADD[4:0] R FDS 35 DBUS[15:0] 50 DTV EOF BE0 Host System Interface—3-Cycle Receive FIFO/Register Read Timing S1 ...
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AC WAVEFORMS SCLK (EDSEL = 0) SCLK (EDSEL = 1) 31 ADD4–0 R FDS DBUS15–0 DTV 37 EOF BE0 Host System Interface—2-Cycle Transmit FIFO/Register Write Timing 102 S1 ...
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AC WAVEFORMS SCLK (EDSEL = 0) SCLK (EDSEL = 1) 31 ADD[4:0] R DBUS[15:0] DTV EOF BE0 Host System Interface—3-Cycle Transmit FIFO/Register Write Timing SCLK ...
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AC WAVEFORMS SCLK (EDSEL = 0) SCLK (EDSEL = 1) EOF TDTREQ Notes: 1. TDTREQ will be asserted for two write cycles (4 SCLK cycles) minimum. 2. TDTREQ will deassert 1 SCLK ...
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XTAL1 STDCLK TXEN 1 1 TXDAT+ (Note 1) DO+ DO– DO± 1 bit (n–2) Note: TXDAT+ is the internal version of the signal, and is shown for clarification only. AUI Transmit Timing–End of Packet (Last Bit = 0) XTAL1 SRDCLK ...
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DO± AUI Transmit Timing—End Transmit Delimiter (ETD) Bit Cell 1 1 (Note 1) 59 DI± V ASQ BCC RXCRS IVCO_ENABLE IVCO SRDCLK SRD : Notes 1. Minimum pulse width>45 ns with amplitude >–160 mV. 2. SRD first decoded bit might ...
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Bit Cell (n– DI± V ASQ BCC RXCRS IVCO SRDCLK SRD Notes: 1. RXCRS deasserts in less than 3 bit times after last DI rising edge. 2. Start of next packet reception (2 bit times). 3. IVCO is ...
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DO± TXEN CI+ CI- CLSN DO± CI+ CI- CLSN = 0 108 80 79 AUI Collision Timing 66 67 AUI SQE Test Timing 16235D-38 16235D-39 ...
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STDCLK BCB BCB 72 TXDAT± TXDAT+ 95 TXDAT- 72 TXEN RXDAT 100 RXCRS DAI Port Receive Timing BCB BCB BCB BCB BCB 97 96 DAI Port Transmit Timing 101 BCB 99 16235D-40 16235D-41 109 ...
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TXDAT+ TXDAT- TXEN RXDAT RXCRS 102 CLSN SRDCLK SRD SF/BD EAM/R Note: First assertion of EAM/R must occur after bit 2/3 boundary of preamble. 110 79 DAI Port Collision Timing Destination Address Byte 1 BIT BIT BIT BIT BIT SFD ...
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Last Byte of Message SRDCLK SRD 86 SF/BD 85 EADI Feature–End of Packet Timing Destination Address Byte 6 SRDCLK SRD BIT BIT BIT SF/BD EAM 90 Source Address Byte 1 BIT BIT BIT BIT BIT BIT BIT ...
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Byte 64 (Data Byte 51) RDCLK BIT BIT SRD 4 5 SF/BD 91 EAR STDCLK 72 TXDAT+ 70 TXEN RXCRS Note: During transmit, the RXCRS input must be asserted (high) and remain active-high after TXEN goes active (high). If RXCRS ...
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SRDCLK RXDAT RXCRS GPSI Receive Timing STDCLK 72 73 TXDAT+ 70 TXEN CLSN GPSI Collision Timing 16235D-48 16235D-49 113 ...
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TCK TMS TDI TDO System Output Note: 1. Parameter is internal to the device. 114 tsu1 thd1 tsu2 thd2 IEEE 1149.1 TAP Timing t TF 10BASE-T Transmit Timing td1 td2 16235D- TETD t XMTOFF 16235D-51 ...
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RXD t RCVON RXCRS TXD RXD t COLON CLSN 10BASE-T Receive Timing 10BASE-T Collision Timing V TSQ+ V TSQ- t RCVOFF 16235D-52 t COLOFF 16235D-53 115 ...
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PWPLP TXD+ TXP+ TXD- TXP- t PWLP RXD 10BASE-T Receive Thresholds (LRT = 0) RXD 10BASE-T Receive Thresholds (LRT = 1) 116 t PERLP 10BASE-T Idle Link Test Pulse 16235D-54 V TSQ+ V THS+ V THS- V TSQ- 16235D-55 ...
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PHYSICAL DIMENSIONS* PL 084 84-Pin Plastic Leaded Chip Carrier (measured in inches) 1.185 1.195 Pin 1 I.D. 1.185 1.195 1.150 1.156 .026 .032 TOP VIEW .042 1.150 .056 1.156 .007 .013 .050 REF .062 .083 1.090 1.130 1.000 REF .013 ...
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PHYSICAL DIMENSIONS* PQR100 100-Pin Plastic Quad Flat Pack; Trimmed and Formed (measured in millimeters) 50 0.22 0.38 0.65 BASIC 80 2.70 2.90 0.25 MIN 118 17.10 17.30 13.90 14.10 12.35 REF 30 Pin 1 I.D. 100 TOP VIEW SIDE VIEW ...
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PHYSICAL DIMENSIONS PQR100 100-Pin Plastic Quad Flat Pack with Molded Carrier Ring (measured in millimeters) 35.50 27.87 22.15 35.90 28.13 22.25 35.87 31.37 25.15 19.80 36.13 31.63 25.25 20.10 .45 Typ .65 Pitch .65 Typ 35.87 36.13 35.50 31.37 35.90 ...
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PHYSICAL DIMENSIONS* PQT080 80-Pin Thin Quad Flat Package (measured in millimeters) .95 1.05 1.00 REF. 120 80 1 11.80 12.20 13.80 14.20 11 – 13 0.50 BSC 11 – 13 13.80 14.20 11.80 12.20 1.20 MAX ...
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APPENDIX A Logical Address Filtering For Ethernet The purpose of logical (or group or multicast) ad dresses is to allow a group of nodes in a network to receive the same message. Each node can maintain a list of multicast ...
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MAPPING OF LOGICAL ADDRESS TO FILTER MASK LADRF Byte # Bit # Bit Address Accepted ...
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APPENDIX B BSDL DESCRIPTION OF Am79C940 MACE JTAG STRUCTURE -- -------- 04 November 1996 ----------- -- JWB 13-AUG-1996 changed "TQFP_PACKAGE" to "TQFP" -- 31-OCT-1996 corrected reversed bit subscripts for ADD, DBUS ! -- and bumped chip rev version from 2 ...
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AVSS1: linkage bit; AVSS2: linkage bit; BE0_L: in bit; BE1_L: in bit; CI0: linkage bit; CI1: in bit; CLSN: inout bit; CS_L: in bit; DBUS: inout bit_vector (15 downto 0); DI0: linkage bit; DI1: in bit; DO0: linkage bit; DO1: ...
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SLEEP_L: in bit; SRDCLK: inout bit; STDCLK: inout bit; TCK: in bit; TC_L: in bit; TDI: in bit; TDO: out bit; TDTREQ_L: out bit; TMS: in bit; TXD0: linkage bit; TXD1: out bit; TXDAT1: inout bit; TXEN_L: inout bit; TXP0: ...
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"DI0:65," & "DI1:66," & "DO0:62," & "DO1:63," & "DVDD1:49," & "DVDD2:70," & "DVDDN:25," & "DVDDP:6," & "DVSS1:47," & "DVSS2:73," & "DVSSN1:10," & "DVSSN2:15," & "DVSSN3:28," & "DVSSP:75," & "DXRCV_L:71," & "EAM_R_L:2," & "EDSEL:72," & "EOF_L:29," & "FDS_L:30," & "INTR_L:7," & ...
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TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute ...
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BYPASS, SETBYP, TRIBYP)," & "BOUNDARY ( EXTEST, SAMPLE, SELFTST)," & "IDCODE ( IDCODE)"; attribute BOUNDARY_CELLS of AM79C940 : entity is " BC_1, BC_4"; attribute BOUNDARY_LENGTH of AM79C940 : entity is 99; attribute BOUNDARY_REGISTER of AM79C940 : entity is ...
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DBUS(12), output3, X, 22, 0, Z)," & " 30 (BC_1, DBUS(12), input, 0)," & " 31 (BC_1, DBUS(11), output3, X, 22, 0, Z)," & " 32 (BC_1, DBUS(11), input, 0)," & " 33 (BC_1, DBUS(10), output3, X, ...
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RXCRS, output3, X, 68, 0, Z)," & " 70 (BC_1, RXCRS, input, 0)," & " 71 (BC_1, *, control, 0)," & " 72 (BC_1, RXDAT, output3, X, 71, 0, Z)," ...
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BSDL File created/edited by AT&T BSD Editor -- -- BSDE:Revision: Silicon Rev. C0; File REV A3 -- BSDE:Description: BSDL File for the AM79C940 MACE Product; -- 84-Pin PLCC and 100-Pin PQFP packages. -- Separate file for 80-Pin TQFP ...
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DVSS1: linkage bit; DVSS2: linkage bit; DVSSN1: linkage bit; DVSSN2: linkage bit; DVSSN3: linkage bit; DVSSP: linkage bit; DXRCV_L: out bit; EAM_R_L: in bit; EDSEL: in bit; EOF_L: inout bit; FDS_L: in bit; INTR_L: out bit; LNKST_L: out bit; RDTREQ_L: ...
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TXP1: out bit; XTAL1: in bit; XTAL2: linkage bit ); use STD_1149_1_1990.all; attribute PIN_MAP of AM79C940 : entity is PHYSICAL_PIN_MAP; constant PLCC_PACKAGE: PIN_MAP_STRING:= "ADD:(49,50,51,52,53)," & "AVDD1:66," & "AVDD2:71," & "AVDD3:78," & "AVDD4:83," & "AVSS1:73," & "AVSS2:75," & "BE0_L:44," & "BE1_L:45," ...
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"DVSSP:6," & "DXRCV_L:1," & "EAM_R_L:13," & "EDSEL:2," & "EOF_L:41," & "FDS_L:43," & "INTR_L:19," & "LNKST_L:57," & "RDTREQ_L:48," & "RESET_L:16," & "RXCRS:11," & "RXD0:64," & "RXD1:65," & "RXDAT:10," & "RXPOL_L:56," & "R_W_L:54," & "SCLK:46," & "SF_BD:15," & "SLEEP_L:17," & "SRD:14," & ...
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"ADD:(46,47,48,49,50)," & "AVDD1:67," & "AVDD2:72," & "AVDD3:83," & "AVDD4:88," & "AVSS1:74," & "AVSS2:79," & "BE0_L:41," & "BE1_L:42," & "CI0:86," & "CI1:87," & "CLSN:98," & "CS_L:56," & "DBUS:(14,16,17,18,19,21,22,23,24,25," & "29,31,32,33,35,36)," & "DI0:84," & "DI1:85," & "DO0:81," & "DO1:82," & "DTV_L:39," & ...
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"RXCRS:100," & "RXD0:65," & "RXD1:66," & "RXDAT:99," & "RXPOL_L:57," & "R_W_L:55," & "SCLK:43," & "SF_BD:8," & "SLEEP_L:10," & "SRD:7," & "SRDCLK:5," & "STDCLK:96," & "TCK:61," & "TC_L:13," & "TDI:63," & "TDO:59," & "TDTREQ_L:44," & "TMS:60," & "TXD0:69," & "TXD1:71," & ...
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INSTRUCTION_CAPTURE of AM79C940 : entity is "0001"; attribute INSTRUCTION_DISABLE of AM79C940 : entity is "TRIBYP"; attribute INSTRUCTION_PRIVATE of AM79C940 : entity is " ...
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RDTREQ_L, output3, X, 10, 0, Z)," & " 12 (BC_1, TDTREQ_L, output3, X, 10, 0, Z)," & " 13 (BC_4, SCLK, clock, 1)," & " 14 (BC_1, BE1_L, input, 1)," ...
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DBUS(3), input, 0)," & " 50 (BC_1, DBUS(2), output3, X, 35, 0, Z)," & " 51 (BC_1, DBUS(2), input, 0)," & " 52 (BC_1, DBUS(1), output3, X, 35, 0, Z)," & " 53 (BC_1, DBUS(1), input, 0)," ...
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DXRCV_L, output3, X, 88, 0, Z)," & " 90 (BC_4, XTAL1, clock, 0)," & " 91 (BC_1, RXD1, input, 1)," & " 92 (BC_1, *, control, 0)," & " 93 ...
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APPENDIX C Am79C940 MACE Rev C0 Silicon Errata The items below are the known errata for Rev C0 silicon. Rev C0 is the production silicon. The enclosed is a list of known errata’s encountered with the MACE Rev C0 device. ...
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Status: No current plan to fix this item. 3) Flashing LED for Link Status: Description: When TMAU receiver is receiving negative polarity link pulse, and the automatic polarity correc- tion algorithm (DAPC bit in PHY Configuration Control Register) is disabled, ...
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If (ISR_LATENCY < 9.6 us) True_bable_err = BABL * ( TINT + XMT_LED) { i.e. False_bable_err = ~ (BABL * ( TINT + XMT_LED))} else Cannot tell if the BABL error is true or false just by reading BABL, TINT, ...
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Am79C940 ...