AD8304ARU-REEL Analog Devices Inc, AD8304ARU-REEL Datasheet - Page 9

• Manufacturer Part Number: AD8304ARU-REEL
• Description: IC LOGARITHMIC CONV 14-TSSOP T/R
• Manufacturer: Analog Devices Inc
• Type: Logarithmic Converterr

Specifications of AD8304ARU-REEL

• Rohs Status: RoHS non-compliant
• Design Resources: Interfacing ADL5315 to Translinear Logarithmic Amplifier (CN0056) Interfacing ADL5317 High Side Current Mirror to a Translinear Logarithmic Amplifier in an Avalanche Photodiode Power Detector
• Applications: Fiber Optics
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP

To repeat the previous example: for a reference power level of
1 mW, a P
4.77 dBm, while the equivalent intercept power of 110 pW will
correspond to a D
which is in agreement with the result from Equation 7.
GENERAL STRUCTURE
The AD8304 addresses a wide variety of interfacing conditions
to meet the needs of fiber optic supervisory systems, and will also
be useful in many nonoptical applications. These notes explain
the structure of this unique translinear log amp. Figure 1 is a
simplified schematic showing the key elements.
The photodiode current I
summing voltage at this node is essentially equal to that on the
two adjacent guard pins, VSUM, due to the low offset voltage of
the ultralow bias J-FET op amp used to support the operation of
the transistor Q1, which converts the current to a logarithmic
voltage, as delineated in Equation 1. VSUM is needed to provide
the collector-emitter bias for Q1, and is internally set to 0.5 V,
using a quarter of the reference voltage of 2 V appearing on
Pin VREF.
In conventional translinear log amps, the summing node is gener-
ally held at ground potential, but that condition is not readily
realized in a single-supply part. To address this, the AD8304 also
supports the use of an optional negative supply voltage, V
Pin VNEG. For a V
be connected to ground potential. Larger negative voltages may
be used, with essentially no effect on scaling, up to a maximum
supply of 8 V between VPOS and VNEG. Note that the resistance
at the VSUM pins is approximately 10 kΩ to ground; this voltage
is not intended as a general bias source.
The input-dependent V
a second transistor, Q2, which operates at an accurate internally
generated current, I
to be 100,000 times smaller than I
The difference between these two V
Thus, the uncertain and temperature-dependent saturation current,
I
eliminate the temperature variation of kT/q, this difference
REV. A
S
V
that appears in Equation 1, has been eliminated. Next, to
INPUT CURRENT
R1
C1
LOG
PHOTODIODE
INPT
V
I
PD
BE
=
1
OPT
0.5V
VNEG (NORMALLY GROUNDED)
–
20
Q1
V
~10k
VSUM
BE
mV
of 3 mW would correspond to a D
Figure 1. Simplified Schematic
2
0.5V
=
{
Z
4 77
REF
kT q
of –69.6 dBm; now using Equation 8:
.
N
of at least –0.5 V the summing node can
/ log (
= 10 µA. The overall intercept is arranged
BE
– (–
QM
200
of Q1 is compared with the fixed V
PD
69 9
10
is received at input Pin INPT. The
V
BE1
V
. )
PDB
REF
I
0.6V
PD
VPDB
}
, in later parts of the signal chain.
BE
=
/
I
REF
1 487
values can be written as
.
0.5V
)
(INTERNAL)
I
REF
Q2
296mVP
V
V
V
BE2–
BE1
OPT
of 10 log
INTERCEPT AND
(SUBTRACT AND
VLOG
COMPENSATION
V
ACOM
TEMPERATURE
DIVIDE BY T K)
BE2
40 A/dec
5k
10
N
(3) =
, at
BE
V
(10)
LOG
(9)
of
–9–
voltage is applied to a processing block—essentially an analog divider
that effectively puts a variable proportional to temperature
underneath the T in Equation 10. In this same block, I
formed to the much smaller current I
defined value for V
Recall that V
this is generated first as an output current of 40 µA/decade
(2 µA/dB) applied to an internal load resistor from VLOG to
ACOM that is laser-trimmed to 5 kΩ ± 1%. The slope may be
altered at this point by adding an external shunt resistor. This is
required when using the minimum supply voltage of 3.0 V,
because the span of V
range of I
internal headroom at this node. Using a shunt of 5 kΩ, this is
reduced to 800 mV, that is, the slope becomes 5 mV/dB. In
those applications needing a higher slope, the buffer can provide
voltage gain. For example, to raise the output swing to 2.4 V,
which can be accommodated by the rail-to-rail buffer when
using a 3.0 V supply, a gain of 3 can be used which raises the
slope to 15 mV/dB. Slope variations implemented in these ways
do not affect the intercept. Keep in mind these measures to
address the limitations of a small positive supply voltage will not
be needed when I
can also be avoided by using a negative supply that allows V
to run below ground, which will be discussed later.
Figure 1 shows how a sample of the input current is derived using
a very small monitoring transistor, Q
Q1. This is used to generate the photodiode bias, V
which varies from 0.6 V when I
the diode by 0.1 V (after subtracting the fixed 0.5 V at INPT)
and rises to 2.6 V at I
The driver for this output is current-limited to about 20 mA.
The system is completed by the final buffer amplifier, which is
essentially an uncommitted op amp with a rail-to-rail output
capability, a 10 MHz bandwidth, and good load-driving capabili-
ties, and may be used to implement multipole low-pass filters,
and a voltage reference for internal use in controlling the scaling,
but that is also made available at the 2.0 V level at Pin VREF.
Figure 2 shows the ideal output V
Bandwidth and Noise Considerations
The response time and wide-band noise of translinear log amps
are fundamentally a function of the signal current I
bandwidth becomes progressively lower as I
largely due to the effects of junction capacitances in Q1. This is
easily understood by noting that the transconductance (g
bipolar transistor is a linear function of collector current, I
(hence, translinear), which in this case is just I
sponding incremental emitter resistance is:
Basically, this resistance and the capacitance C
generate a time constant of r
corner frequency of:
showing the proportionality of bandwidth to current.
V
r
f
e
3
LOG
dB
=
g
=
1
=
m
PD
V
2
=
Y
π
qI
amounts to 8
Y
log (
qI
kTC
kT
PD
is 200 mV/decade and I
PD
10
PD
j
LOG
I
is limited to about 1 mA maximum. They
PD
PD
, that is,
LOG
/
I
Z
= 10 mA, for a net diode bias of 2 V.
)
for the full 160 dB (eight-decade)
e
C
0.2 V = 1.6 V, which exceeds the
J
PD
and thus a corresponding low-pass
LOG
= 100 pA, and reverse-biases
M
Z
versus I
, connected in parallel with
, to provide the previously
Z
is 100 pA. Internally,
PD
PD
J
.
AD8304
PDB
of the transistor
PD
is reduced,
. The corre-
, at Pin V
REF
PD
. The
is trans-
m
) of a
(11)
(12)
(13)
LOG
PDB
C
,
,