GAL16V8D-15LD/883 National Semiconductor, GAL16V8D-15LD/883 Datasheet
GAL16V8D-15LD/883
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GAL16V8D-15LD/883 Summary of contents
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... PCI REQ/GNT Bus Pairs National Semiconductor and Virtual System Architecture are registered trademarks of National Semiconductor Corporation. Geode, WebPAD, and VSA are trademarks of National Semiconductor Corporation. For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks. © 2002 National Semiconductor Corporation The Geode GX1 processor series is divided into three main categories as defined by the core operating voltage ...
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... VGA and 16-bit audio functions that are transparent at the operating system level. Together the National Semiconductor I/O companion and GX1 processor Geode devices provide a scalable, flexible, low-power, system-level solution well suited for a wide ...
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Flexible Power Management Supports a wide variety of standards: — APM (Advanced Power Management) for Legacy power management — ACPI (Advanced Configuration and Power Interface) for Windows power management – Direct support for all standard processor (C0-C4) states — ...
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Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents (Continued) 3.5 OFFSET, SEGMENT, AND PAGING MECHANISMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 ...
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Table of Contents (Continued) 4.0 Integrated Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents (Continued) 4.5 DISPLAY CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents (Continued) 5.0 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents (Continued) 7.0 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Architecture Overview The Geode GX1 processor series represents the sixth gen- eration of x86-compatible 32-bit processors with sixth-gen- eration features. The decoupled load/store unit allows reordering of load/store traffic to achieve higher perfor- mance. Other features include single-cycle execution, ...
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Architecture Overview (Continued) 1.1 INTEGER UNIT The integer unit consists of: • Instruction Buffer • Instruction Fetch • Instruction Decoder and Execution The pipelined integer unit fetches, decodes, and executes x86 instructions through the use of a five-stage integer pipeline. ...
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Architecture Overview (Continued) 1.6 INTEGRATED FUNCTIONS The GX1 processor integrates the following functions tradi- tionally implemented using external devices: • High-performance 2D graphics accelerator • Separate CRT and TFT control from the display controller • SDRAM memory controller • PCI ...
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Architecture Overview (Continued) 1.7 GEODE GX1/CS5530A SYSTEM DESIGNS A GX1 processor and Geode CS5530A I/O companion based design provides high performance using 32-bit x86 processing. The two chips integrate video, audio and mem- ory interface functions normally performed by external ...
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Architecture Overview (Continued) 18 Pixel Data Geode™ Geode™ GX Series CS5530A Processor I/O Companion 8 Video Port (YUV) Figure 1-3. Geode™ CS9211 Interface System Diagram Exclusive Interconnect Signals (Do not connect to any other device) Geode™ GX1 Processor Nonexclusive Interconnect ...
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Architecture Overview (Continued) Geode™ GX1 R Processor G B Revision 4.1 PIXEL17 PIXEL23 PIXEL16 PIXEL22 PIXEL15 PIXEL21 PIXEL14 PIXEL20 PIXEL13 PIXEL19 PIXEL12 PIXEL18 PIXEL17 PIXEL16 PIXEL11 PIXEL15 PIXEL10 PIXEL14 PIXEL9 PIXEL13 PIXEL8 PIXEL12 PIXEL7 PIXEL11 PIXEL6 PIXEL10 PIXEL9 PIXEL8 PIXEL5 ...
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... Figure 1-6. Example WebPAD™ System Diagram www.national.com main segments of the information appliance market: Per- sonal Internet Access, Thin Client, and Set-top Box. Con- tact your local National Semiconductor sales or field support representative for further information on reference designs for the information appliance market. Control Geode™ ...
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Architecture Overview (Continued) SDRAM SO-DIMM Geode™ Video GX1 3.3V PCI Bus Processor NSC DP83815 Ethernet Controller Reset CPU Core PWR CTL Power Figure 1-7. Example Thin Client System Diagram Revision 4.1 Geode™ CS5530A I/O Companion ISA Bus Termination Clock Generator ...
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Architecture Overview (Continued) CPU Temp. Sensor LM75 MIC MIC AC3 1 2 Anlg IN IN Headphone Output LM4548 Audio Line Codec Output Tuner Companion 2.5” UDMA33 Hard Drive Notebook Notebook DVD Floppy Drive Drive Internal Assembly ...
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Signal Definitions This section describes the external interface of the Geode GX1 processor. Figure 2-1 shows the signals organized by their functional interface groups (internal test and electrical pins are not shown). SYSCLK CLKMODE[2:0] RESET System INTR IRQ13 Interface ...
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Signal Definitions (Continued) 2.1 PIN ASSIGNMENTS The tables in this section use several common abbrevia- tions. Table 2-1 lists the mnemonics and their meanings. Figure 2-2 shows the pin assignment for the 352 BGA with Table 2-2 and Table 2-3 ...
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Signal Definitions (Continued) Index Corner AD27 AD24 AD21 AD16 V FRAM#DEVS CC2 AD28 AD25 AD22 AD18 V CBE2# TRDY CC2 ...
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Signal Definitions (Continued) Table 2-2. 352 BGA Pin Assignments - Sorted by Pin Number Pin Pin No. Signal Name No. Signal Name A1 V B23 MD1 B24 MD33 SS A3 AD27 B25 AD24 B26 ...
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Signal Definitions (Continued) Table 2-2. 352 BGA Pin Assignments - Sorted by Pin Number (Continued) Pin Pin No. Signal Name No. Signal Name AB1 DCLK AC16 V SS AB2 PIXEL17 AC17 V CC2 AB3 VID_DATA6 AC18 V SS AB4 VID_DATA7 ...
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Signal Definitions (Continued) Table 2-3. 352 BGA Pin Assignments - Sorted Alphabetically by Signal Name 1 Signal Name Type Pin No. Signal Name AD0 I/O A21 DQM0 AD1 I/O A22 DQM1 AD2 I/O A19 DQM2 AD3 I/O B19 DQM3 AD4 ...
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Signal Definitions (Continued) Table 2-3. 352 BGA Pin Assignments - Sorted Alphabetically by Signal Name (Continued) 1 Signal Name Type Pin No. Signal Name V PWR K1 V CC2 CC3 V PWR K2 V CC2 CC3 V PWR K3 V ...
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Signal Definitions (Continued) Index Corner AD25 V V AD16 CC3 SS CC2 ...
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Signal Definitions (Continued) Table 2-4. 320 SPGA Pin Assignments - Sorted by Pin Number Pin Pin No. Signal Name No. Signal Name A3 V C25 AD4 CC3 A5 AD25 C27 AD0 A7 V C29 V SS CC2 A9 V C31 ...
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Signal Definitions (Continued) Table 2-4. 320 SPGA Pin Assignments - Sorted by Pin Number (Continued) Pin Pin No. Signal Name No. Signal Name AJ27 V AK24 MD20 CC2 AJ29 V AK26 MD50 CC2 AJ31 V AK28 MD16 SS AJ33 BA1 ...
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Signal Definitions (Continued) Table 2-5. 320 SPGA Pin Assignments - Sorted Alphabetically by Signal Name 1 Signal Name Type Pin. No. Signal Name AD0 I/O C27 DQM0 AD1 I/O B30 DQM1 AD2 I/O A27 DQM2 AD3 I/O B26 DQM3 AD4 ...
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Signal Definitions (Continued) Table 2-5. 320 SPGA Pin Assignments - Sorted Alphabetically by Signal Name (Continued) 1 Signal Name Type Pin. No. Signal Name V PWR A29 V CC2 CC2 V PWR C9 V CC2 CC2 V PWR C29 V ...
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Signal Definitions (Continued) 2.2 SIGNAL DESCRIPTIONS 2.2.1 System Interface Signals BGA Signal Name Pin No. SYSCLK P26 CLKMODE[2:0] M1, L1, M3 RESET J3 INTR B18 IRQ13 C22 Revision 4.1 SPGA Pin No. Type Description V34 I System Clock PCI clock ...
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Signal Definitions (Continued) 2.2.1 System Interface Signals (Continued) BGA Signal Name Pin No. SMI# C19 SUSP# H2 (PU) SUSPA# E2 SERIALP L3 www.national.com SPGA Pin No. Type Description B28 I System Management Interrupt SMI level-sensitive interrupt. SMI# puts ...
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Signal Definitions (Continued) 2.2.2 PCI Interface Signals BGA Signal Name Pin No. FRAME# A8 (PU) IRDY# C9 (PU) TRDY# B9 (PU) STOP# C11 (PU) Revision 4.1 SPGA Pin No Type Description C13 s/t/s Frame (PU) FRAME# is driven by the ...
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Signal Definitions (Continued) 2.2.2 PCI Interface Signals (Continued) BGA Signal Name Pin No. AD[31:0] Refer to Table 2-3 C/BE[3:0]# D5, B8, C13, A15 PAR B12 www.national.com SPGA Pin No Type Description Refer to I/O Multiplexed Address and Data Table 2-5 ...
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Signal Definitions (Continued) 2.2.2 PCI Interface Signals (Continued) BGA Signal Name Pin No. LOCK# B11 (PU) DEVSEL# A9 (PU) PERR# A11 (PU) SERR# C12 (PU) REQ[2:0]# D3, H3, E3 (PU) Revision 4.1 SPGA Pin No Type Description B16 s/t/s Lock ...
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Signal Definitions (Continued) 2.2.2 PCI Interface Signals (Continued) BGA Signal Name Pin No. GNT[2:0]# E1, F2, D1 2.2.3 Memory Controller Interface Signals BGA Signal Name Pin No. MD[63:0] Refer to Table 2-3 MA[12:0] Refer to Table 2-3 BA[1:0] AD26, AD25 ...
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Signal Definitions (Continued) 2.2.3 Memory Controller Interface Signals (Continued) BGA Signal Name Pin No. DQM[7:0] Refer to Table 2-3 SDCLK[3:0] AE4, AF5, AE5, AF4 SDCLK_IN AE8 SDCLK_OUT AF8 2.2.4 Video Interface Signals BGA Signal Name Pin No PCLK AC1 VID_CLK ...
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Signal Definitions (Continued) 2.2.4 Video Interface Signals (Continued) BGA Signal Name Pin No FP_HSYNC L2 FP_VSYNC J1 ENA_DISP AD5 VID_RDY AD1 VID_VAL M2 VID_DATA[7:0] Refer to Table 2-3 PIXEL[17:0] Refer to Table 2-3 www.national.com SPGA Pin No Type Description R4 ...
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Signal Definitions (Continued) 2.2.5 Power, Ground, and No Connect Signals BGA Signal Name Pin No. V Refer to SS Table 2-3 (Total of 71) V Refer to CC2 Table 2-3 (Total of 32) V Refer to CC3 Table 2-3 (Total ...
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Signal Definitions (Continued) 2.2.6 Internal Test and Measurement Signals (Continued) BGA Signal Name Pin No. TEST F3 (PD) TDP D26 TDN E24 www.national.com SPGA Pin No. Type Description J5 I Test (PD) Test-mode input. This pin is internally connected to ...
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Processor Programming This section describes the internal operations of the Geode GX1 processor from a programmer’s point of view. It includes a description of the traditional “core” processing and FPU operations. The integrated functions are described in Section 4.0 ...
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Processor Programming Table 3-1. Initialized Core Register Controls (Continued) Register Register Name LDTR Local Descriptor Table Register TR Task Register CR0 Control Register 0 CR2 Control Register 2 CR3 Control Register 3 CR4 Control Register 4 CCR1 Configuration Control 1 ...
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Processor Programming 3.2 INSTRUCTION SET OVERVIEW The GX1 processor instruction set can be divided into nine types of operations: • Arithmetic • Bit Manipulation • Shift/Rotate • String Manipulation • Control Transfer • Data Transfer • Floating Point • High-Level ...
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Processor Programming 3.3.1 Application Register Set The Application Register Set consists of the registers most often used by the applications programmer. These regis- ters are generally accessible, although some bits in the EFLAGS registers are protected. The General Purpose Register ...
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Processor Programming General Purpose Registers Segment (Selector) Registers Instruction Pointer and EFLAGS Registers Revision 4.1 (Continued) Table 3-2. ...
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Processor Programming 3.3.1.2 Segment Registers The 16-bit segment registers, part of the main memory addressing mechanism, are described in Section 3.5 "Off- set, Segment, and Paging Mechanisms" on page 66. The six segment registers are: CS- Code Segment DS- Data ...
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Processor Programming 3.3.1.4 EFLAGS Register The EFLAGS register contains status information and con- trols certain operations on the GX1 processor. The lower Bit Name Flag Type 31:22 RSVD -- 21 ID System 20:19 RSVD -- 18 AC System 17 VM ...
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Processor Programming 3.3.2 System Register Set The System Register Set, shown in Table 3-5, consists of registers not generally used by application programmers. These registers are typically employed by system level pro- grammers who generate operating systems and memory management ...
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Processor Programming 3.3.2.1 Control Registers A map of the Control Registers (CR0, CR1, CR2, CR3, and CR4) is shown in Table 3-6 and the bit definitions are given in Table 3-7. (These registers should not be confused with the CRRn ...
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Processor Programming Table 3-7. CR4-CR0 Bit Definitions (Continued) Bit Name Description 11:0 RSVD Reserved: Set to 0. CR2 Register 31:0 PFLA Page Fault Linear Address: With paging enabled and after a page fault, PFLA contains the linear address of the ...
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Processor Programming 3.3.2.2 Configuration Registers The Configuration Registers listed in Table 3-9 are CPU registers and are selected by register index numbers. The registers are accessed through I/O memory locations 22h and 23h. Registers are selected for access by writing ...
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Processor Programming Register (Index) Bit 7 Bit 6 Control Registers CCR1 (C1h) CCR2 (C2h) USE_SUSP CCR3 (C3h) LSS_34 LSS_23 CCR4 (E8h) CPUID SMI_NEST CCR7 (EBh) PCR0 (20h) LSSER RSVD PCR1 (F0h) SMM Base Header Address Registers SMHR0 (B0h ...
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Processor Programming Bit Name Description Index C1h 7:3 RSVD Reserved: Set to 0. 2:1 SMAC System Management Memory Access 00: SMM is disabled 01: SMI# pin is active to enter SMM. SMINT instruction is inactive. If ...
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Processor Programming Table 3-11. Configuration Registers (Continued) Bit Name Description Index E8h 7 CPUID Enable CPUID Instruction The ID bit in the EFLAGS register can be modified and execution of the CPUID instruction occurs as documented in ...
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Processor Programming Table 3-11. Configuration Registers (Continued) Bit Name Description Index 20h 7 LSSER Load/Store Serialize Enable (Reorder Disable): LSSER should be set to ensure that memory mapped I/O devices operating outside of the address range 640 ...
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Processor Programming Table 3-11. Configuration Registers (Continued) Bit Name Description Index FEh 7:4 DID[3:0] Device ID (Read Only): Identifies device as GXyy processor, where yy is defined by the DIR1 register. 3:0 MULT[3:0] Core Multiplier (Read Only): Identifies the core ...
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Processor Programming 3.3.2.3 Debug Registers Six debug registers (DR0-DR3, DR6 and DR7) support debugging on the GX1 processor. Memory addresses loaded in the debug registers, referred to as “breakpoints,” generate a debug exception when a memory access of the specified ...
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Processor Programming The Debug Status Register (DR6) reflects conditions that were in effect at the time the debug exception occurred. The contents of the DR6 register are not automatically cleared by the processor after a debug exception occurs, and therefore ...
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Processor Programming 3.3.2.4 TLB Test Registers Two test registers are used in testing the processor’s Trans- lation Lookaside Buffer (TLB), TR6 and TR7. Table 3- register map for the TLB Test Registers with their bit defini- tions given ...
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Processor Programming Bit Name Description TR7 Register 31:12 Physical Physical Address: Address TLB lookup: Data field from the TLB. TLB write: Data field written into the TLB. 11:10 RSVD Reserved: Set to 0. 9:7 TLB LRU LRU Bits: TLB lookup: ...
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Processor Programming 3.3.2.5 Cache Test Registers Three test registers are used in testing the processor’s on- chip cache, TR3-TR5. Table 3- register map for the Cache Test Registers with their bit definitions given in Table 3-17 on page ...
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Processor Programming Bit Name Description TR5 Register (R/W) 31:12 RSVD Reserved 11:4 Line Selection Line Selection: Physical address bits [11:4] used to select one of 256 lines. 3:2 Set/DWord Set/DWORD Selection: Selection Cache read: Selects which of the four sets ...
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Processor Programming There are five types of test operations that can be exe- cuted: • Flush buffer read • Fill buffer write • Cache write • Cache read • Cache flush Test Operation Code Sequence Flush Buffer Read MOV TR5, ...
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Processor Programming 3.3.3 Model Specific Register Set The Model Specific Register (MSR) Set is used to monitor the performance of the processor or a specific component within the processor. A MSR can be read using the RDMSR instruction, opcode 0F32h. ...
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Processor Programming 3.4 ADDRESS SPACES The GX1 processor can directly address either memory or I/O space. Figure 3-2 illustrates the range of addresses available for memory address space and I/O address space. For the CPU, the addresses for physical memory ...
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Processor Programming 3.5 OFFSET, SEGMENT, AND PAGING MECHANISMS The mapping of address space into a sequence of memory locations (often cached) is performed by the offset, seg- ment, and paging mechanisms. In general, the offset, segment and paging mechanisms work ...
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Processor Programming 3.5.2 Segment Mechanisms Memory is divided into contiguous regions called “seg- ments.” The segments allow the partitioning of individual elements of a program. Each segment provides a zero address-based private memory for such elements as code, data, and ...
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Processor Programming 3.5.2.4 Segment Selectors The segment registers are used to store segment selec- tors. In protected mode, the segment selectors are divided in to three fields: the RPL, TI and INDEX fields as shown in Figure 3-6 on page ...
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Processor Programming Selector Load Instruction 15 Selector INDEX TI RPL In Segment Register Revision 4.1 (Continued) 0 Segment Descriptor Global Descriptor Table Segment Descriptor Local Descriptor Table Figure 3-7. Selector Mechanism Caching 69 Segment ...
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Processor Programming 3.5.3 Descriptors 3.5.3.1 Global and Local Descriptor Table Registers The GDT and LDT descriptor tables are defined by the Glo- bal Descriptor Table Register (GDTR) and the Local Descriptor Table Register (LDTR), respectively. Some texts refer to these ...
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Processor Programming 3.5.3.3 Task, Gate, Interrupt, and Application and System Descriptors Besides segment descriptors there are descriptors used in task switching, switching between tasks with different prior- ity and those used to control interrupt functions: • Interrupt Descriptors • Application ...
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Processor Programming Memory Bit Offset Name Description 31:24 +4 BASE Segment Base Address: Three fields which collectively define the base location for the segment physical address space. 7:0 +4 31:16 +0 19:16 +4 LIMIT Segment Limit: Two ...
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Processor Programming Table 3-23. Application and System Segment Descriptors TYPE Bit Definitions TYPE System Segment and Gate Types Bits [11:8] Num SEWA 0 0000 1 0001 Available 16-Bit TSS 2 0010 3 0011 4 0100 5 0101 6 0110 16-Bit ...
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Processor Programming Gate Descriptors Four kinds of gate descriptors are used to provide protec- tion during control transfers: • Call gates • Trap gates • Interrupt gates • Task gates (For more information on protection refer to Section 3.9 "Protection" ...
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Processor Programming Task State Segments Descriptors The CPU enables rapid task switching using JMP and CALL instructions that refer to Task State Segment (TSS) descriptors. During a switch, the complete task state of the current task is stored in its ...
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Processor Programming Table 3-27. 16-Bit Task State Segment (TSS) Table 15 www.national.com (Continued) Selector for Task’s LDT FLAGS IP SS for Privilege Level 0 SP for Privilege Level ...
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Processor Programming 3.5.4 Paging Mechanism The paging mechanism translates a linear address to its corresponding physical address. If the required page is not currently present in RAM, an exception is generated. When the operating system services the exception, the required ...
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Processor Programming Along with the base address of the page table or the page frame, each DTE or PTE contains attribute bits and a present bit as illustrated in Table 3-28. If the present bit (P) is set in the ...
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Processor Programming 3.6 INTERRUPTS AND EXCEPTIONS The processing of either an interrupt or an exception changes the normal sequential flow of a program by trans- ferring program control to a selected service routine. Except for SMM interrupts, the location of ...
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Processor Programming 3.6.3 Interrupt Vectors When the CPU services an interrupt or exception, the cur- rent program’s instruction pointer and flags are pushed onto the stack to allow resumption of execution of the inter- rupted program. In protected mode, the ...
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Processor Programming 3.6.4 Interrupt and Exception Priorities As the CPU executes instructions, it follows a consistent policy for prioritizing exceptions and hardware interrupts. The priorities for competing interrupts and exceptions are listed in Table 3-30. SMM interrupts always take prece- ...
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Processor Programming 3.6.5 Exceptions in Real Mode Many of the exceptions described in Table 3-29 "Interrupt Vector Assignments" on page 80 are not applicable in real mode. Exceptions 10, 11, and 14 do not occur in real mode. Other exceptions ...
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Processor Programming 3.7 SYSTEM MANAGEMENT MODE System Management Mode (SMM enhancement of the standard x86 architecture. SMM is usually employed for system power management or software-transparent emula- tion of I/O peripherals. SMM is entered through a hardware signal ...
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Processor Programming 3.7.1 SMM Operation SMM execution flow is summarized in Figure 3-10. Entering SMM requires the assertion of the SMI# pin for at least two SYSCLK periods or execution of the SMINT instruction. For the SMI# signal or SMINT ...
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Processor Programming 3.7.3 SMM Configuration Registers The SMAR register specifies the base location of SMM code region and its size limit. The SMHR register specifies the 32-bit physical address of the SMM header. The SMHR address must be 32-bit aligned ...
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Processor Programming Table 3-35. SMM Memory Space Header Description Name DR7 Debug Register 7: The contents of Debug Register 7. EFLAGS Extended Flags Register: The contents of Extended Flags Register. CR0 Control Register 0: The contents of Control Register 0. ...
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Processor Programming 3.7.5 SMM Instructions The GX1 processor core automatically saves a minimal amount of CPU state information when entering SMM which allows fast SMM service routine entry and exit. After enter- ing the SMM service routine, the MOV, SVDC, ...
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Processor Programming 3.7.6 SMM Memory Space SMM memory space is defined by specifying the base address and size of the SMM memory space in the SMAR register. The base address must be a multiple of the SMM memory space size. ...
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Processor Programming When SMI nesting is disabled, the processor holds off external SMI interrupts until the currently executing SMM code exits. When SMI nesting is enabled, the processor can proceed with the SMI. The SMM service routine will guarantee that ...
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Processor Programming 3.7.9.1 CPU States Related to SMM and Suspend Mode The state diagram shown in Figure 3-12 illustrates the vari- ous CPU states associated with SMM and Suspend mode. While in the SMM service routine, the GX1 processor core ...
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Processor Programming 3.8 HALT AND SHUTDOWN The halt instruction (HLT) stops program execution and generates the Halt bus cycle on the PCI bus. The GX1 pro- cessor core then drives out a Stop Grant bus cycle and enters a low-power ...
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Processor Programming 3.9.3 Privilege Level Transfers A task’s CPL can be changed only through intersegment control transfers using gates or task switches to a code seg- ment with a different privilege level. Control transfers result from exception and interrupt servicing ...
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Processor Programming 3.10 VIRTUAL 8086 MODE Both real mode and virtual 8086 (V86) modes are sup- ported by the GX1 processor, allowing execution of 8086 application programs and 8086 operating systems. V86 mode allows the execution of 8086-type applications, yet ...
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Processor Programming 3.11 FLOATING POINT UNIT OPERATIONS The GX1 processor contains an FPU that is x87 and MMX instruction-set compatible and adheres to the IEEE-754 standard. Because most applications that contain FPU instructions intermix with integer instructions, the GX1 pro- ...
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Processor Programming Bit Name Description 1 FPU Tag Word Register (R/W) 15:14 TAG7 TAG7 Valid Zero Special Empty. 13:12 TAG6 TAG6 Valid Zero Special ...
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... Performance degrada- tion in traditional UMA systems is reduced through the use of National Semiconductor’s Display Compression Technol- ogy (DCT) architecture. Figure 4-1 shows the major functional blocks of the GX1 processor and how the internal bus interface unit operates as the interface between the processor’ ...
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Integrated Functions (Continued) 4.1 INTEGRATED FUNCTIONS PROGRAMMING INTERFACE The GX1 processor’s integrated functions programming interface is a memory mapped space. The control registers for the graphics pipeline, display controller, and memory controller are located in this space, as well as ...
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Integrated Functions (Continued) DRAM Map FFFF FFFFh MAX Graphics Memory (Frame Buffer, etc.) *GBADD or Top of DRAM Extended Memory 100000h (1 MB) Shadowed System BIOS E8000h Shadowed Video BIOS E0000h UMBs and Expansion ROMs C0000h SMM System Code A0000h ...
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Integrated Functions (Continued) 4.1.2 Control Registers The control registers for the GX1 processor use the memory map, starting at GX_BASE+8000h (see Figure 4-2 on page 98). The space from GX_BASE+9000h to GX_BASE+4000000h is also mapped to the ...
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... Section 4.1.6 on page 102. If the graphics pipeline or National software is used, and it is desirable to use scratchpad RAM by software other than that supplied by National, please contact your local National Semiconductor technical support representative. 4.1.4.3 BLT Buffer Address registers, BitBLT, have been added to the front ...
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Integrated Functions (Continued) Table 4-4. L1 Cache BitBLT Register Summary 1 Mnemonic Name L1_BB0_BASE L1 Cache BitBLT 0 Base Address L1_BB0_POINTER L1 Cache BitBLT 0 Pointer L1_BB1_BASE L1 Cache BitBLT 1 Base Address L1_BB1_POINTER L1 Cache BitBLT 1 Pointer 1. ...
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Integrated Functions (Continued) 4.1.5 Display Driver Instructions While the majority of the GX1’s integrated function inter- face is memory mapped, a few integrated function regis- ters are accessed via four GX1 specific instructions. Table 4-6 shows these instructions. Adding CPU ...
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Integrated Functions (Continued) 4.2 INTERNAL BUS INTERFACE UNIT The GX1 processor’s internal bus interface unit provides control and interface functions to the C-Bus and X-Bus. The functions on C-Bus include: processor core, FPU, graphics pipeline, and L1 cache. The functions ...
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Integrated Functions (Continued) 4.2.5 Internal Bus Interface Unit Registers The internal bus interface unit maps 100h bytes starting at GX_BASE+8000h. However, only 16 bytes (four 32-bit reg- isters) are defined and some of these registers will alias across the 100h ...
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Integrated Functions (Continued) Table 4-9. Internal Bus Interface Unit Registers Bit Name Description GX_BASE+8000h-8003h 31:29 RSVD Reserved: Set to 0. 28:17 TOP OF Top of DRAM: DRAM 000h = Minimum top or 0001FFFFh (128 KB) FFFh = Maximum top or ...
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Integrated Functions (Continued) Table 4-9. Internal Bus Interface Unit Registers Bit Name Description GX_BASE+8008h-800Bh 31: Region: Region control field for address range DC000h to DFFFFh. 27: Region: Region control field for address range D8000h to DBFFFh. ...
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... SDRAM clock. SDRAM frequencies over 79 MHz are only supported for certain types of closed systems, and strict design rules must be adhered to. For further details, contact your local National Semiconductor technical support representative. A basic block diagram of the memory controller is shown in Figure 4-3 ...
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Integrated Functions (Continued) 4.3.1 Memory Array Configuration The memory controller supports up to four 64-bit SDRAM banks, with maximum of eight physical devices per bank. Banks 0: 1 and 2: 3 must be identical configurations. Two 168-pin unbuffered SDRAM modules ...
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Integrated Functions (Continued) 4.3.2 Memory Organizations The memory controller supports JEDEC standard synchro- nous DRAMs in 16, 64, 128, and 256-Mbit configurations. Supported configurations are shown in Table 4-11. Note Table 4-11. Synchronous DRAM Configurations Depth Organization 1 1Mx16 2 ...
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Integrated Functions (Continued) 4.3.3 SDRAM Commands This subsection discusses the SDRAM commands sup- ported by the memory controller. Table 4-12 summarizes these commands followed by detailed operational informa- tion regarding each command. Refer to the SDRAM manu- facturer’s specification for ...
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Integrated Functions (Continued) ACT — The activate command is used to open a row in a particular bank for a subsequent access. The value on the BA lines selects the bank, and the address on the MA lines selects the ...
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Integrated Functions (Continued) 4.3.4 Memory Controller Register Description The Memory Controller maps 100h locations starting at GX_BASE+8400h. However, only 28 bytes are defined and some of these registers will alias across the 100h space. Table 4-14. Memory Controller Register Summary ...
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Integrated Functions (Continued) Bit Name Description GX_BASE+ 8400h-8403h 31:29 RSVD Reserved 28:26 RSVD Reserved 25:23 RSVD Reserved 22 RSVD Reserved: Set RSVD Reserved: Must be set to 0. Wait state on the X-Bus x_data during read cycles ...
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Integrated Functions (Continued) Table 4-15. Memory Controller Registers (Continued) Bit Name Description GX_BASE+8404h-8407h 31:14 RSVD Reserved: Set to 0. 13:11 RSVD Reserved 10 SDCLKOMSK# Enable SDCLK_OUT: Turn on the output Enabled Disabled. 9 SDCLK3MSK# Enable SDCLK3: ...
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Integrated Functions (Continued) Table 4-15. Memory Controller Registers (Continued) Bit Name Description 12 DIMM0_ DIMM0 Component Banks (Banks 0 and 1): Selects the number of component banks per module COMP_BNK bank for DIMM0 Component banks 1 = ...
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Integrated Functions (Continued) Table 4-15. Memory Controller Registers (Continued) Bit Name Description 7 RSVD Reserved: Set to 0. 6:4 DPL Data-in to PRE command period (tDPL): Minimum number of SDRAM clocks from the time the last write datum is sampled ...
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Integrated Functions (Continued) 4.3.5 Address Translation The memory controller supports two address translations depending on the method used to interleave pages. The hardware automatically enables high order interleaving. Low order interleaving is automatically enabled only under specific memory configurations. 4.3.5.1 ...
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Integrated Functions (Continued) Table 4-16. Auto LOI -- 2 DIMMs, Same Size, 1 DIMM Bank 1 KB Page Size 2 KB Page Size Row Col Row Address 2 Component Banks MA12 A24 -- A25 MA11 A23 -- A24 MA10 A22 ...
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Integrated Functions (Continued) Table 4-18. Non-Auto LOI -- DIMMs, Different Sizes, 1 DIMM Bank 1 KB Page Size 2 KB Page Size Row Col Row Address 2 Component Banks MA12 A23 -- A24 MA11 A22 -- A23 ...
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Integrated Functions (Continued) 4.3.6 Memory Cycles Figures 4-5 through 4-8 illustrate various memory cycles that the memory controller supports. The following subsec- tions describe some of the supported cycles. SDCLK CS# RAS# CAS# WE# MA DQM MD Figure 4-5. Basic ...
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Integrated Functions (Continued) SDRAM Write Cycle Figure 4-6 shows a SDRAM write cycle. The burst length for the WRT command is two. SDCLK CS# RAS# CAS# WE DQM Revision 4.1 COL n n n+1 n n+1 Figure 4-6. ...
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Integrated Functions (Continued) SDRAM Refresh Cycle Figure 4-7 shows a SDRAM auto refresh cycle. The mem- ory controller always precedes the refresh cycle with a PRE command to all banks. SDCLK CS# RAS# CAS# WE# MA[10] SDCLK COMMAND PRE NOP ...
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Integrated Functions (Continued) 4.3.7 SDRAM Interface Clocking The GX1 processor drives the SDCLK to the SDRAMs; one for each DIMM bank. All the control, data, and address signals driven by the memory controller are sampled by the SDRAM at the ...
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Integrated Functions (Continued) The SDRAM interface timings are programmable. The SHFTSDCLK bits in the MC_MEM_CNTRL2 register can be used to change the relationship between SDCLK and the control/address/data signals to meet setup and hold time requirements for SDRAM across different ...
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Integrated Functions (Continued) 4.4 GRAPHICS PIPELINE The graphics pipeline of the GX1 processor contains a 2D graphics accelerator. This hardware accelerator has a Bit- BLT/vector engine which dramatically improves graphics performance when rendering and moving graphical objects. Overall operating system ...
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Integrated Functions (Continued) 4.4.2 Master/Slave Registers When starting a BitBLT or vector operation, the graphics pipeline registers are latched from the master registers to the slave registers. A second BitBLT or vector operation can then be loaded into the master ...
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Integrated Functions (Continued) 4.4.3.1 Monochrome Patterns Setting the pattern mode to 01b (GX_BASE+8200h[9:8] = 01b) in the GP_RASTER_MODE register selects the monochrome patterns (see bit details on page 132). Those pixels corresponding to a clear bit (0) in the pattern ...
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Integrated Functions (Continued) 4.4.3.3 Color Patterns Setting the pattern mode to 11b (GX_BASE+8200h[9:8] = 11b), in the GP_RASTER_MODE register selects the color patterns. Bits [63:0] are used to hold a row of pattern data for an 8-bpp pattern, with bits ...
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Integrated Functions (Continued) 4.4.6 Graphics Pipeline Register Descriptions The graphics pipeline maps 200h locations starting at GX_BASE+8100h. However, only 72 bytes are defined and some of these registers will alias across the 200h space. Table 4-23. Graphics Pipeline Configuration Register ...
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Integrated Functions (Continued) Table 4-23. Graphics Pipeline Configuration Register Summary (Continued) GX_BASE+ Memory Offset Type Name / Function 8208h-820Bh R/W GP_BLT_MODE Graphics Pipeline BLT Mode Register: Writing to this initiates a BLT operation. 820Ch-820Fh R/W GP_BLT_STATUS Graphics Pipeline BLT Status ...
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Integrated Functions (Continued) Table 4-24. Graphics Pipeline Configuration Registers (Continued) Bit Name Description GX_BASE+810Ch-810Dh 15:0 8-bpp Mode: 8-bpp color: The color index must be duplicated in the upper byte. 16-bpp Mode: 16-bpp color (RGB) GX_BASE+810Eh-810Fh 15:0 8-bpp Mode: 8-bpp color: ...
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Integrated Functions (Continued) Table 4-24. Graphics Pipeline Configuration Registers (Continued) Bit Name Description GX_BASE+8200h-8203h 31:13 RSVD Reserved: Set Transparent BLT: When set, this bit enables transparent BLT. The source color data will be compared to a ...
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Integrated Functions (Continued) Table 4-24. Graphics Pipeline Configuration Registers (Continued) Bit Name Description GX_BASE+820Ch-820Fh 31:11 RSVD Reserved: Set to 0. 10:9 W Screen Width: Selects a frame-buffer width. This register must be programmed correctly in order for com- pression to ...
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Integrated Functions (Continued) 4.5 DISPLAY CONTROLLER The GX1 processor incorporates a display controller that retrieves display data from the memory controller and for- mats it for output on a variety of display devices. The GX1 processor connects directly to the ...
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Integrated Functions (Continued) 4.5.1 Display FIFO The display controller contains a large (64x64 bit) FIFO for queuing up display data from the memory controller as required for output to the screen. The memory controller must arbitrate between display controller requests ...
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Integrated Functions (Continued) 4.5.3 Hardware Cursor The display controller contains hardware cursor logic to allow overlay of the cursor image onto the pixel data stream. Overhead for updating this image on the screen is kept to a minimum by requiring ...
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Integrated Functions (Continued) Simultaneous Resolution Colors 8-bpp 5 640x480 256 colors out of a palette of 256 16-bpp 64 KB colors 5-6-5 5 8-bpp 800x600 256 colors out of a palette of 256 16-bpp 64 KB Colors 5-6-5 1024x768 8-bpp ...
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Integrated Functions (Continued) Table 4-26. CRT and TFT Panel Data Bus Formats Panel Data CRT & Bus Bit 18-Bit TFT ...
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Integrated Functions (Continued) Resolution 640x480 8-bpp 256 colors out of a palette of 256 16-bpp 64 KB colors RGB 5-6-5 800x600 8-bpp 256 colors out of a palette of 256 16-bpp 64 KB colors RGB 5-6-5 1024x768 8-bpp 256 colors ...
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Integrated Functions (Continued) 4.5.7 Graphics Memory Map The GX1 processor supports a maximum graph- ics memory and will map address space (see Fig- ure 4-2 on page 98) higher than the maximum amount ...
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Integrated Functions (Continued) 4.5.7.3 VGA Display Support The graphics pipeline contains full hardware support for the VGA front end. The VGA data is stored in a 256 KB buffer located in graphics memory. The main task for Virtual VGA (see ...
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Integrated Functions (Continued) Table 4-28. Display Controller Register Summary (Continued) GX_BASE+ Memory Offset Type Name/Function 8320h-8323h R/W DC_VID_ST_OFFSET Display Controller Video Start Address: Specifies offset at which the video buffer starts. 8324h-8327h R/W DC_LINE_DELTA Display Controller Line Delta: Stores line ...
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Integrated Functions (Continued) Table 4-28. Display Controller Register Summary (Continued) GX_BASE+ Memory Offset Type Name/Function Cursor and Line Compare Registers 8350h-8353h R/W DC_CURSOR_X Display Controller Cursor X Position: X position information of the hard- ware cursor. 8354h-8357h RO DC_V_LINE_CNT Display ...
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Integrated Functions (Continued) 4.5.8.1 Configuration and Status Registers The Configuration and Status registers group consists of four 32-bit registers located at GX_BASE+8300h-830Ch. Table 4-29. Display Controller Configuration and Status Registers Bit Name Description GX_BASE+8300h-8303h 31:16 RSVD Reserved: Set to 0. ...
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Integrated Functions (Continued) Table 4-29. Display Controller Configuration and Status Registers (Continued) Bit Name Description 11:8 DFIFO Display FIFO High Priority Start Level: This field specifies the depth of the display FIFO (in 64-bit HI-PRI entries which ...
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Integrated Functions (Continued) Table 4-29. Display Controller Configuration and Status Registers (Continued) Bit Name Description 16 BKRT Blink Rate Cursor blinks on every 16 frames for a duration of 8 frames (approximately 4 times per second) and VGA ...
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Integrated Functions (Continued) Table 4-29. Display Controller Configuration and Status Registers (Continued) Bit Name Description 3 BLKE Blank Enable: Allow generation of the composite blank signal to the display device Disable Enable. When disabled, the ENA_DISP ...
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Integrated Functions (Continued) 4.5.9 Memory Organization Registers The GX1 processor utilizes a graphics memory aperture that size. The base address of the graphics memory aperture is stored in the DRAM controller Graph- ics Base ...
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Integrated Functions (Continued) Table 4-30. Display Controller Memory Organization Registers (Continued) Bit Name Description GX_BASE+8324h-8327h 31:23 RSVD Reserved: Set to 0. 22:12 CB_LINE_ Compressed Display Buffer Line Delta: This value represents number of DWORDs that, when added to DELTA the ...
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Integrated Functions (Continued) 4.5.10 Timing Registers The Display Controller’s timing registers control the gener- ation of sync, blanking, and active display regions. They provide complete flexibility in interfacing to both CRT and flat panel displays. These registers will generally be ...
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Integrated Functions (Continued) Table 4-31. Display Controller Timing Registers (Continued) Name Bit Description GX_BASE+8338h-833Bh 31:27 RSVD Reserved: Set to 0. 26:19 H_SYNC Horizontal Sync End: The character clock count at which the CRT horizontal sync signal becomes inac- _END tive ...
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Integrated Functions (Continued) Table 4-31. Display Controller Timing Registers (Continued) Name Bit Description GX_BASE+8348h-834Bh 31:27 RSVD Reserved: Set to 0. 26:16 V_SYNC_E Vertical Sync End: The line at which the CRT vertical sync signal becomes inactive minus 1. ND 15:11 ...
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Integrated Functions (Continued) 4.5.11 Cursor Position and Miscellaneous Registers The Cursor Position registers contain pixel coordinate information for the cursor. These values are not latched by the timing generator until the start of the frame to avoid tearing artifacts when ...
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Integrated Functions (Continued) 4.5.12 Palette Access Registers These registers are used for accessing the internal palette RAM and extensions. In addition to the standard 256 entries for 8-bpp color translation, the GX1 processor pal- ette has extensions for cursor colors ...
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Integrated Functions (Continued) 4.5.13 FIFO Diagnostic Registers The FIFO Diagnostic register group consists of two 32-bit registers located at GX_BASE+8378h Bit Name Description GX_BASE+8378h-837Bh DC_DFIFO_DIAG Register (R/W) Default Value = xxxxxxxxh 31:0 DISPLAY FIFO Display FIFO Diagnostic Read or Write ...
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Integrated Functions (Continued) 4.5.14 CS5530A Display Controller Interface As previously stated in Section 1.7 "Geode GX1/CS5530A System Designs" on page 13, the GX1 processor inter- faces with the Geode CS5530A I/O companion chip. This section will discuss the specifics on ...
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Integrated Functions (Continued) 4.5.14.1 CS5530A Video Port Data Transfer VID_VAL indicates that the GX1 processor has placed valid data on VID_DATA[7:0]. VID_RDY indicates that the CS5530A is ready to accept the next byte of video data. VID_CLK VID_VAL VID_RDY VID_DATA ...
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Integrated Functions (Continued) 4.6 VIRTUAL VGA SUBSYSTEM This section describes the Virtual System Architecture as implemented with the Geode GX1 processor(s) and VSA enhanced Geode I/O companion device(s). VSA provides a framework to enable software implementation of tradi- tionally hardware-only ...
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Integrated Functions (Continued) Category Mode Software 0,1 2,3 4 Hardware 0Dh 0Eh 0Fh 10h 11h 12h 13h A VGA is made up of several functional units. • The frame buffer is 256 KB of memory that provides data ...
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Integrated Functions (Continued) 4.6.1.2 VGA Front End The VGA front end consists of address and data transla- tions between the CPU and the frame buffer. This function- ality is contained within the graphics controller and sequencer components. Most of the ...
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Integrated Functions (Continued) ette with 6 bits per entry. Except for 8-bpp modes, all VGA configurations drive four bits of pixel data into the palette, which produces a 6-bit result. Based on various control registers, this value is then combined ...
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Integrated Functions (Continued) An application that wishes to perform ROPs on the source and destination must first byte read the address (to load the latch) and then immediately write a byte to the same address. The ALU has no effect ...
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Integrated Functions (Continued) 4.6.2.8 VGA Memory The VGA memory requires 256 KB of memory organized bits. The VGA memory is implemented as part of system memory. The GX1 processor partitions sys- tem memory into two ...
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Integrated Functions (Continued) Bit Description Index B9h 7:3 Reserved: Set SMI generation for VGA memory range B8000h to BFFFFh Disable Enable. 1 SMI generation for VGA memory range B0000h to B7FFFh ...
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Integrated Functions (Continued) 4.6.4 Virtual VGA Register Descriptions This section describes the registers contained in the graph- ics pipeline used for VGA emulation. The graphics pipeline maps 200h locations starting at GX_BASE+8100h. Refer GX_BASE+ Memory Offset Type Name/Function 8140h-8143h R/W ...
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Integrated Functions (Continued) Bit Name Description GX_BASE+8140h-8143h 31:28 RSVD Reserved: Set to 0. 27:24 MAP_MASK Map Mask: Enables planes 3 through 0 for writing. Combined with chain control to determine the final enables. 23:21 RSVD Reserved: Set ...
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Integrated Functions (Continued) 4.7 PCI CONTROLLER The GX1 processor includes an integrated PCI controller with the following features. 4.7.1 X-Bus PCI Slave • 16-byte PCI write buffer • 16-byte PCI read buffer from X-bus • Supports cache line bursting • ...
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Integrated Functions (Continued) 4.7.6 PCI Configuration Space Control Registers There are two registers CONFIG_ADDRESS and CONFIG_DATA. The CONFIG_ADDRESS register contains the address information for the next configuration space access to CONFIG_DATA. Only DWORD accesses are permitted to Bit Name Description ...
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Integrated Functions (Continued) 4.7.7 PCI Configuration Space Registers To access the internal PCI configuration registers of the GX1 processor, the Configuration Address register (CONFIG_ADDRESS) must be written as a DWORD using the format shown in Table 4-42. Any other size ...
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... Description Index 00h-01h 31:0 VID (RO) Vendor Identification register (Read Only): The combination of this value and the device ID uniquely identifies any PCI device. The Vendor ID is the ID given to National Semiconductor Corporation by the PCI SIG. Index 02h-03h 31:0 DIR (RO) Device Identification register (Read Only): This value along with the vendor ID uniquely identifies any PCI device ...
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Integrated Functions (Continued) Table 4-44. PCI Configuration Registers (Continued) Bit Name Description 10:9 DT Device Timing: The GX1 processor performs medium DEVSEL# active for addresses that hit into the GX1 processor address space. These two bits are always set to ...
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Integrated Functions (Continued) Table 4-44. PCI Configuration Registers (Continued) Bit Name Description 3 SWBE PCI Slave Write Buffer Enable: GX1 PCI slave write buffers Disable Enable. 2 CLRE PCI Cache Line Read Enable: Read operations from ...
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Integrated Functions (Continued) Table 4-44. PCI Configuration Registers (Continued) Bit Name Description Index 44h 7 PP Ping-Pong Arbiter grants the processor bus per the setting of bits [2:0 Arbiter grants the processor bus ownership of the ...
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Integrated Functions (Continued) 4.7.8 PCI Cycles The following sections and diagrams provide the functional relationships for PCI cycles. 4.7.8.1 PCI Read Transaction A PCI read transaction consists of an address phase and one or more data phases. Data phases may ...
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Integrated Functions (Continued) 4.7.8.2 PCI Write Transaction A PCI write transaction is similar to a PCI read transaction, consisting of an address phase and one or more data phases. Since the master provides both address and data, no turnaround cycle ...
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Integrated Functions (Continued) 4.7.8.3 PCI Arbitration An agent requests the bus by asserting its REQ#. Based on the arbitration scheme set in the PCI Arbitration Control 2 register (Index 44h), the GX1 processor’s PCI arbiter will grant the request by ...
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Power Management Power consumption in a GX1 processor based system is managed with the use of both hardware and software. The complete hardware solution is provided for only when the GX1 processor is combined with a Geode I/O companion ...
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Power Management (Continued) 5.1.3.1 Suspend Modulation for Thermal Management The best use of Suspend Modulation is for thermal man- agement. The Geode I/O companion monitors the temper- ature of the system and/or CPU and asserts the SMI# pin, if the ...
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Power Management (Continued) 5.2 SUSPEND MODES AND BUS CYCLES The following subsections describe the bus cycles of the various Suspend states. 5.2.1 Timing Diagram for Suspend-on-Halt The CPU enters Suspend-on-Halt as a result of executing a halt (HLT) instruction if ...
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Power Management (Continued) 5.2.2 Initiating Suspend with SUSP# The GX1 processor enters the Suspend mode in response to SUSP# input assertion only when certain conditions are met. First, the USE_SUSP bit must be set in CCR2 (Index C2h[7]). In addition, ...
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Power Management (Continued) 5.2.3 Stopping the Input Clock The GX1 processor is a static device, allowing the input clock (SYSCLK stopped and restarted without any loss of internal CPU data. The SYSCLK input can be stopped at either ...
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Power Management (Continued) 5.3 POWER MANAGEMENT REGISTERS The GX1 processor contains the power management reg- isters for the serial packet transmission control, the user- defined power management address space, Suspend Refresh, and SMI status for Suspend/Resume. The power management registers ...
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Power Management (Continued) Table 5-2. Power Management Control and Status Registers Bit Name Description GX_BASE+8500h-8503h 31:8 RSVD Reserved: These bits are not used. Do not write to these bits. 7:3 RSVD Reserved: Set SMI_MEM SMI VGA Emulation ...
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Power Management (Continued) Table 5-2. Power Management Control and Status Registers (Continued) Bit Name Description GX_BASE+850Ch-850Fh 31:8 RSVD Reserved: These bits are not used. Do not write to these bits. 7 VID_IRQ Video IRQ: This bit indicates the occurrence of ...
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Electrical Specifications 6.1 PART NUMBERS/PERFORMANCE CHARACTERISTICS The GX1 series of processors is designated by three core voltage specifications: 2.2V, 2.0V, and 1.8V. Each core volt- age is offered in frequencies that are enabled by specific system clock and internal ...
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Electrical Specifications (Continued) 6.2 ELECTRICAL CONNECTIONS 6.2.1 Power/Ground Connections and Decoupling Testing and operating the GX1 processor requires the use of standard high frequency techniques to reduce parasitic effects. These effects can be minimized by filtering the DC power leads ...
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Electrical Specifications (Continued 3.3V Plane (V ) CC3 2.9V Regulator Legend = High frequency capacitor = 220 µF, low ESR capacitor = 3.3V connection = 1.8V, 2.0V, or 2.2V connection Figure 6-2. SPGA Recommended Split ...
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Electrical Specifications (Continued) 6.2.2 NC-Designated Pins Pins designated NC (No Connection) should be left discon- nected. Connecting an NC pin to a pull-up/-down resistor active signal could cause unexpected results and possible circuit malfunctions. 6.2.3 Pull-Up and Pull-Down ...
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Electrical Specifications (Continued) 6.4 OPERATING CONDITIONS Table 6-4 lists the operating conditions for the GX1 processor. Symbol Parameter T Operating Case Temperature Core Supply Voltage CC2 1.8V (Nominal 200, 233, or 266 MHz CLK ...
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Electrical Specifications (Continued) 6.5 DC CHARACTERISTICS All DC parameters and current measurements in this sec- tion were measured under the operating conditions listed in Table 6-4 "Operating Conditions" on page 189. 6.5.1 Input/Output DC Characteristics Table 6-5 shows the input/output ...
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Electrical Specifications (Continued) 6.5.2.2 Definition and Measurement Techniques of CPU Current Parameters The following two parameters indicate processor current while in the “On” state: • Typical Average: Indicates the average current used by the processor while in the “On” state. ...
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Electrical Specifications (Continued) 6.5.2.4 DC Current Measurements The following tables show the DC current measurements for the 1.8V (Tables 6-7 and 6-8), 2.0V (Tables 6-9 and 6-10) and 2.2V (Tables 6-11 and 6-12) devices of the GX1 processor series. Table ...
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Electrical Specifications (Continued) Table 6-9. 2.0V DC Characteristics for CPU Mode = “On” 1 Symbol Parameter I I/O Current @ V = 3.3V (Nominal); CC3ON CC3 CPU mode = “On”; f CLK I Core Current @ V CC2ON CC2 CPU ...
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Electrical Specifications (Continued) Table 6-11. 2.2V DC Characteristics for CPU Mode = “On” 1 Symbol Parameter I I/O Current @ V = 3.3V (Nominal); CC3ON CC3 CPU mode = “On”; f CLK I Core Current @ V CC2ON CC2 CPU ...
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... SDRAM frequencies between 79 and 111 MHz are only supported for certain types of closed systems and strict design rules must be adhered to. For further details, please contact your local National Semiconductor technical sup- port representative. 6.6.3 I/O Current De-Rating Curve The I/O current de-rating curve, shown in Figure 6-3, is the same for all devices in the GX1 series of processors ...
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Electrical Specifications (Continued) 6.7 AC CHARACTERISTICS The following tables list the AC characteristics including output delays, input setup requirements, input hold require- ments, and output float delays. The rising-clock-edge refer- ence level V , and other reference levels are shown ...
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Electrical Specifications (Continued) Parameter 1 Setup Time for RESET, INTR 1 Hold Time for RESET, INTR Setup Time for SMI#, SUSP#, FLT# Hold Time for SMI#, SUSP#, FLT# Valid Delay for IRQ13 Valid Delay for SUSPA# Valid Delay for SERIALP ...
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Electrical Specifications (Continued) Symbol Parameter t SYSCLK Period 1 t SYSCLK Period Stability 2 t SYSCLK High Time 3 t SYSCLK Low Time SYSCLK Fall Time SYSCLK Rise Time 6 t SDCLK_OUT, SDCLK[3:0] Period ...
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Electrical Specifications (Continued IH(Min) 1.5V V IL(Max) SYSCLK t 6 Figure 6-6. SYSCLK Timing and Measurement Points (Min) 1. (Max) SDCLK_OUT, SDCLK[3: Figure 6-7. SDCLK[3:0] Timing and Measurement Points ...
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Electrical Specifications (Continued) Symbol Parameter t Delay Time, SYSCLK to Signal Valid for Bused Signals VAL1 t Delay Time, SYSCLK to Signal Valid for GNT# VAL2 t Delay Time, Float to Active ON t Delay Time, Active to Float OFF ...