IDT77V1053L25PF Integrated Device Technology, Inc., IDT77V1053L25PF Datasheet

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IDT77V1053L25PF

Manufacturer Part Number
IDT77V1053L25PF
Description
Triple PORT ATM PHY for 25.6 and 51.2 Mbps Applications with 8-bit UTOPIA Level 2
Manufacturer
Integrated Device Technology, Inc.
Datasheet
©1999 Integrated Device Technology, Inc.
Physical Media Dependent (PMD) Sublayer functions for
three 25.6 Mbps ATM channels
specifications for 25.6 Mbps physical interface
Performs the PHY-Transmission Convergence (TC) and
Compliant to ATM Forum (af-phy-040.000) and ITU-T I.432.5
Also operates at 51.2Mbps
8-bit UTOPIA Level 2 Interface
3-Cell Transmit & Receive FIFOs
LED Interface for status signalling
Supports UTP Category 3 physical media
Interfaces to standard magnetics
Low-Power CMOS
3.3V supply with 5V tolerant inputs
128-pin TQFP Package (14 x 20 mm)
RxDATA[7:0]
RxADDR[4:0]
TxADDR[4:0]
TxDATA[7:0]
RxPARITY
TxPARITY
RxCLAV
TxCLAV
RxSOC
TxSOC
RxCLK
AD[7:0]
TxCLK
RxEN
TxEN
OSC
RST
ALE
INT
WR
RD
CS
(UTOPIA or DPI)
Microprocessor
(Utility Bus)
PHY-ATM
Interface
Interface
RxREF
Triple Port ATM PHY
for 25.6 and 51.2 Mbps
with 8-bit Utopia 2
TxREF
Tx/Rx ATM
Tx/Rx ATM
Tx/Rx ATM
Cell FIFO
Cell FIFO
Cell FIFO
RxLED[2:0]
1
Descrambler
Descrambler
Descrambler
Scrambler/
Scrambler/
Scrambler/
ing Asynchronous Transfer Mode (ATM) data communications and
networking. The IDT77V1053 implements the physical layer for 25.6
Mbps ATM, connecting three serial copper links (UTP Category 3) to
one ATM layer device such as a SAR or a switch ASIC. The
IDT77V1053 also operates at 51.2 Mbps, and is well suited to
backplane driving applications. The 77V1053 utilizes an 8-bit UTOPIA
Level 2 interface on the cell side.
CMOS technology, providing the highest levels of integration, perfor-
mance and reliability, with the low-power consumption characteristics
of CMOS.
3
The IDT77V1053 is a member of IDT's family of products support-
The IDT77V1053 is fabricated using IDT's state-of-the-art
TxLED[2:0]
3
Encoding/
Encoding/
Encoding/
Decoding
Decoding
Decoding
5B/4B
5B/4B
5B/4B
P/S and S/P
P/S and S/P
P/S and S/P
NRZI
NRZI
NRZI
Clock/Data
Clock/Data
Clock/Data
Recovery
Recovery
Recovery
Driver
Driver
Driver
PRELIMINARY
IDT77V1053
77v1053 drw 01
DSC-5359/1
+
-
+
-
+
-
+
-
+
-
+
-
Tx 0
Rx 0
Tx 1
Rx 1
Tx 2
Rx 2

Related parts for IDT77V1053L25PF

IDT77V1053L25PF Summary of contents

Page 1

... WR Interface CS AD[7:0] ALE OSC ©1999 Integrated Device Technology, Inc. Triple Port ATM PHY for 25.6 and 51.2 Mbps with 8-bit Utopia 2 The IDT77V1053 is a member of IDT's family of products support- ing Asynchronous Transfer Mode (ATM) data communications and networking. The IDT77V1053 implements the physical layer for 25.6 Mbps ATM, connecting three serial copper links (UTP Category 3) to one ATM layer device such as a SAR or a switch ASIC ...

Page 2

IDT77V1053 Triple Port ATM PHY for 25.6 and 51.2 Mbps with 8-bit Utopia 2 DNC 1 GND 2 VDD 3 TX2- 4 TX2+ 5 GND 6 AGND 7 AVDD AVDD 11 AGND 12 13 AGND ...

Page 3

IDT77V1053 Triple Port ATM PHY for 25.6 and 51.2 Mbps with 8-bit Utopia 2 SIGNAL NAME PIN NUMBER RX0+,- 34, 33 RX1+,- 28, 27 RX2+,- 16, 15 TX0+,- 43, 42 TX1+,- 39, 38 TX2+,- 5, 4 SIGNAL NAME PIN NUMBER ...

Page 4

IDT77V1053 Triple Port ATM PHY for 25.6 and 51.2 Mbps with 8-bit Utopia 2 SIGNAL NAME PIN NUMBER SE 125 TXLED[2:0] 52, 53 SIGNAL NAME PIN NUMBER AGND 7, 12, 13, 18, 19, 22, 24, 25, 30, 31, ...

Page 5

IDT77V1053 Triple Port ATM PHY for 25.6 and 51.2 Mbps with 8-bit Utopia 2 SIGNAL NAME PIN NUMBER TXDATA[7:0] 63, 62, 61, 60, 59, 58, 57 TXPARITY 64 TXSOC 66 The 77V1053 is a three-port implementation of the ...

Page 6

IDT77V1053 Triple Port ATM PHY for 25.6 and 51.2 Mbps with 8-bit Utopia 2 TRANSMISSION CONVERGENCE (TC) SUB LAYER Introduction The TC sub layer defines the line coding, scrambling, data framing and synchronization. Under control of a switch interface or ...

Page 7

IDT77V1053 Triple Port ATM PHY for 25.6 and 51.2 Mbps with 8-bit Utopia 2 Transmission Description Refer to the TC Transmit Block Diagram on the previous page. Cell transmission begins with the PHY-ATM Interface. An ATM layer device transfers a ...

Page 8

IDT77V1053 Triple Port ATM PHY for 25.6 and 51.2 Mbps with 8-bit Utopia 2 Receiver Description The receiver side of the TC sublayer operates like the transmitter, but in reverse. The data is NRZI decoded before each symbol is reassembled. ...

Page 9

IDT77V1053 Triple Port ATM PHY for 25.6 and 51.2 Mbps with 8-bit Utopia 2 To declare 'Bad Signal' (from "Good" to "Bad"): The same up-down counter counts from (being provide a "Good" status). When ...

Page 10

IDT77V1053 Triple Port ATM PHY for 25.6 and 51.2 Mbps with 8-bit Utopia 2 UTOPIA is a Physical Layer to ATM Layer interface standardized by the ATM Forum. It transfers ATM cells and has separate transmit and receive channels and ...

Page 11

IDT77V1053 Triple Port ATM PHY for 25.6 and 51.2 Mbps with 8-bit Utopia 2 polling polling: TxCLK TxADDR[4:0] 1F N+3 High-Z TxCLAV N+1 TxEN TxData[7:0], P44 P45 TxPARITY TxSOC PHY N cell transmission to: Figure 5. Utopia 2 Transmit Handshake ...

Page 12

IDT77V1053 Triple Port ATM PHY for 25.6 and 51.2 Mbps with 8-bit Utopia 2 polling polling: TxCLK TxADDR[4:0] 1F N+3 High-Z TxCLAV N+1 TxEN TxData[7:0], P28 P29 TxPARITY TxSOC PHY M cell transmission to: Figure 7. Utopia 2 Transmit Handshake ...

Page 13

IDT77V1053 Triple Port ATM PHY for 25.6 and 51.2 Mbps with 8-bit Utopia 2 polling polling: RxCLK RxADDR[4:0] N+3 1F RxCLAV N+3 RxEN RxData[7:0], P47 P48 RxPARITY RxSOC PHY N+3 cell transmission to: Figure 9. Utopia 2 Receive Handshake - ...

Page 14

IDT77V1053 Triple Port ATM PHY for 25.6 and 51.2 Mbps with 8-bit Utopia 2 UTILITY BUS The Utility Bus is a byte-wide interface that provides access to the registers within the IDT77V1053. These registers are used to select desired operating ...

Page 15

IDT77V1053 Triple Port ATM PHY for 25.6 and 51.2 Mbps with 8-bit Utopia 2 DIAGNOSTIC FUNCTIONS 1. LOOPBACK There are two loopback modes supported by the 77V1053. The loopback mode is controlled via bits 1 and 0 of the Diagnostic ...

Page 16

IDT77V1053 Triple Port ATM PHY for 25.6 and 51.2 Mbps with 8-bit Utopia 2 Utopia ATM Layer Interface Device 2. COUNTERS Several condition counters are provided to assist external systems (e.g. software drivers) in evaluating communications conditions anticipated ...

Page 17

IDT77V1053 Triple Port ATM PHY for 25.6 and 51.2 Mbps with 8-bit Utopia 2 Each of the threeports has two pins for differential serial transmis- sion, and two pins for differential serial receiving. PHY TO MAGNETICS INTERFACE A standard connection ...

Page 18

IDT77V1053 Triple Port ATM PHY for 25.6 and 51.2 Mbps with 8-bit Utopia 2 The 77V1053 has 28 registers that are accessible through the utility bus. Each of the threeports has 9 registers dedicated to that port. There is only ...

Page 19

IDT77V1053 Triple Port ATM PHY for 25.6 and 51.2 Mbps with 8-bit Utopia 2 Addresses: 0x01, 0x11, 0x21 Bit Type Initial State 7 Reserved Bad Signal Good Signal Bit 1 - Good Signal 0 - Bad ...

Page 20

IDT77V1053 Triple Port ATM PHY for 25.6 and 51.2 Mbps with 8-bit Utopia 2 Addresses: 0x03, 0x13, 0x23 Bit Type Initial State 7 0 Reserved 6 R enable Disable Receive HEC Checking (HEC Enable) checking When not set, ...

Page 21

IDT77V1053 Triple Port ATM PHY for 25.6 and 51.2 Mbps with 8-bit Utopia 2 Addresses: 0x07, 0x17, 0x27 Bit Type Initial State R interrupt enabled HEC Error Cell interrupt ...

Page 22

IDT77V1053 Triple Port ATM PHY for 25.6 and 51.2 Mbps with 8-bit Utopia 2 Symbol Rating V Terminal Voltage TERM with Respect to GND T Temperature BIAS Under Bias T Storage STG Temperature I DC Output Current OUT NOTE: 1. ...

Page 23

IDT77V1053 Triple Port ATM PHY for 25.6 and 51.2 Mbps with 8-bit Utopia 2 Symbol t1 TxCLK Frequency t2 TxCLK Duty Cycle (% of t1) t3 TxDATA[7:0], TxPARITY Setup Time to TxCLK t4 TxDATA[7:0], TxPARITY Hold Time to TxCLK t5 ...

Page 24

IDT77V1053 Triple Port ATM PHY for 25.6 and 51.2 Mbps with 8-bit Utopia 2 RxCLK RxEN RxADDR[4:0] High-Z RxCLAV t 21 High-Z RxSOC t 23 High-Z RxDATA[7:0], RxPARITY ...

Page 25

IDT77V1053 Triple Port ATM PHY for 25.6 and 51.2 Mbps with 8-bit Utopia 2 Name Min Max Unit Tas 10 ____ ns Address setup to ALE Tcsrd 0 ____ ns Chip select to read enable Tah 5 ____ ns Address ...

Page 26

IDT77V1053 Triple Port ATM PHY for 25.6 and 51.2 Mbps with 8-bit Utopia 2 RXREF TXREF Sym bol Tcyc OSC cycle period (25.6 Mbps) (51.2 Mbps) Tch OSC high time Tcl OSC low time Tcc OSC cycle to cycle period ...

Page 27

IDT77V1053 Triple Port ATM PHY for 25.6 and 51.2 Mbps with 8-bit Utopia 2 A note about Figures 22 and 23: The ATM Forum and ITU-T standards for 25 Mbps ATM define "Network" and "User" interfaces. They are identical except ...

Page 28

IDT77V1053 Triple Port ATM PHY for 25.6 and 51.2 Mbps with 8-bit Utopia 2 103 128 1 128-Lead TQFP PK128 3.4306 ' E 4.5139 ' SYMBOL Dimensions are in millimeters 102 4.3514 ' ...

Page 29

... Timing data are based on simulation or initial characterization and are subject to change upon full characterization. 9/13/99 PRELIMINARY. Initial Release. CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 The IDT logo is a registered trademark of Integrated Device Technology, Inc. NNN A A Process/ Package Temp ...

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