TE28F800F3T120 Intel Corporation, TE28F800F3T120 Datasheet

no-image

TE28F800F3T120

Manufacturer Part Number
TE28F800F3T120
Description
3 Volt Fast Boot Block Flash Memory
Manufacturer
Intel Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TE28F800F3T120
Manufacturer:
INT
Quantity:
5 960
Part Number:
TE28F800F3T120
Manufacturer:
INT
Quantity:
5 960
3 Volt Fast Boot Block Flash Memory
28F800F3 and 28F160F3
Product Features
Intel
reads—making it an ideal memory solution for burst CPUs. The Intel 3 Volt Fast Boot Block
Flash memory also supports asynchronous page mode operation for non-clocked memory
subsystems. Combining high read performance with the intrinsic nonvolatility of flash memory
eliminates the traditional redundant memory paradigm of shadowing code from a slower
nonvolatile storage source to a faster execution memory device, (e.g., SRAM SDRAM), for
improved system performance. By adding 3 Volt Fast Boot Block Flash memory to your system
you could reduce the total memory requirement, which helps increase reliability and reduce
overall system power consumption—all while reducing system cost.
This family of products is manufactured on Intel
are available in a wide variety of industry-standard packaging technologies.
Notice: This document contains information on products in full production. The specifications
are subject to change without notice. Verify with your local Intel sales office that you have the lat-
est datasheet before finalizing a design.
High Performance
SmartVoltage Technology
Flexible I/O Voltage
5 V-Safe I/O Enables Interfacing to
5 V Devices
Enhanced Data Protection
Density Upgrade Path
Manufactured on ETOX™ V Flash
Technology
— Up to 60 MHz Effective Zero Wait-State
— Synchronous Burst-Mode Reads
— Asynchronous Page-Mode Reads
— 2.7 V 3.6 V Read and Write Operations
— 12 V V
— 1.65 V I/O Reduces Overall System
— Absolute Write Protection with
— Block Locking
— Block Erase/Program Lockout during
— 8 and 16 Mbit
®
Performance
for Low Power Designs
Power Consumption
V
Power Transitions
3 Volt Fast Boot Block Flash memory offers the highest performance synchronous burst
PP
= GND
PP
Fast Factory Programming
®
0.4 m ETOX™ V process technology. They
Supports Code Plus Data Storage
Flexible Blocking Architecture
Extended Cycling Capability
Low Power Consumption
Automated Program and Block Erase
Algorithms
Industry-Standard Packaging
— Optimized for Intel
— Fast Program Suspend Capability
— Fast Erase Suspend Capability
— Eight 4-Kword Blocks for Data
— 32-Kword Main Blocks for Code
— Top or Bottom Boot Configurations
— Minimum 100,000 Block Erase Cycles
— Automatic Power Savings Mode
— Command User Interface for
— Status Register for System Feedback
— 56-Lead SSOP
— 56-Lead TSOP
— BGA* CSP
— Intel
Integrator (IFDI) and other Intel
Software
Decreases Power Consumption
Automation
®
Easy BGA
Order Number: 290644-005
®
Flash Data
January 2000
®

Related parts for TE28F800F3T120

TE28F800F3T120 Summary of contents

Page 1

Volt Fast Boot Block Flash Memory 28F800F3 and 28F160F3 Product Features High Performance — MHz Effective Zero Wait-State Performance — Synchronous Burst-Mode Reads — Asynchronous Page-Mode Reads SmartVoltage Technology — 2.7 V 3.6 V Read and ...

Page 2

... Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation 1998–2000 *Other brands and names are the property of their respective owners. ...

Page 3

Contents 1.0 Introduction .................................................................................................................. 1 1.1 Product Overview .................................................................................................. 1 2.0 Product Description 2.1 Pinouts .................................................................................................................. 2 2.2 Pin Description ...................................................................................................... 2 2.3 Memory Blocking Organization ............................................................................. 7 2.3.1 Parameter Blocks ..................................................................................... 7 2.3.2 Main Blocks .............................................................................................. 7 3.0 Principles ...

Page 4

V Voltages ............................................................................................................... 28 PP 7.0 Power Consumption 7.1 Active Power ....................................................................................................... 28 7.2 Automatic Power Savings ................................................................................... 28 7.3 Standby Power.................................................................................................... 28 7.4 Power-Up/Down Operation ................................................................................. 29 7.4.1 RST# Connection................................................................................... 29 7.4.2 V 7.5 Power ...

Page 5

Revision History Date of Version Revision 05/12/98 -001 11/15/98 -002 03/22/99 -003 09/17/99 -004 01/12/2000 -005 Description Original version Minor text modifications Revised Page mode read waveform Revised Single synchronous read waveform Improved automotive specifications Changed name from Fast Boot ...

Page 6

...

Page 7

Introduction This datasheet contains 8- and 16-Mbit 3 Volt Intel Section 1.0 provides a flash memory overview. Sections 2.0 through 8.0 describe the memory functionality and electrical specifications for extended temperature product offerings. 1.1 Product Overview The 3 Volt ...

Page 8

The device’s Command User Interface (CUI) serves as the interface between the system processor and internal flash memory operation. A valid command sequence written to the CUI initiates device automation. This automation is controlled by an internal ...

Page 9

Figure Easy BGA Package Ballout RST# CLK WP# WE# ADV ...

Page 10

Figure 2. 56-Ball µBGA* Package Ballout Pin #1 Indicator NOTES: 1. Shaded connections on the Top View indicate upgrade address connections. Lower density devices will not have upper address solder balls. ...

Page 11

Figure 3. SSOP Pinout 16-Mbit 8-Mbit CLK CLK 2 ADV# ADV# 3 GND GND 4 -- ...

Page 12

Table 1. Pin Descriptions Sym Type ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are internally latched during read and write cycles INPUT 0 – 19 8-Mbit 16-Mbit: A 0–18 ...

Page 13

Memory Blocking Organization The 3 Volt Fast Boot Block Flash memory family is an asymmetrically-blocked architecture that enables system integration of code and data within a single flash device. For the address locations of each block, see the memory ...

Page 14

Figure 5. 8- and 16-Mbit Top Boot Memory Map 8-Mbit 4-Kword Parameter Block 22 4-Kword Parameter Block 21 4-Kword Parameter Block 20 4-Kword Parameter Block 19 4-Kword Parameter Block 18 4-Kword Parameter Block 17 4-Kword Parameter Block ...

Page 15

Figure 6. 8- and 16-Mbit Bottom Boot Memory Map 8-Mbit 32-Kword Main Block 22 32-Kword Main Block 21 32-Kword Main Block 20 32-Kword Main Block 19 32-Kword Main Block 18 32-Kword Main Block 17 32-Kword Main Block 16 32-Kword Main ...

Page 16

Principles of Operation The 3 Volt Fast Boot Block Flash memory components include an on-chip Write State Machine (WSM) to manage block erase and program. It allows for CMOS-level control inputs, fixed power supplies, and minimal ...

Page 17

Standby Deselecting the device by bringing CE logic-high level (V mode, which substantially reduces device power consumption. In standby, outputs are placed in a high-impedance state independent of OE#. If deselected during program or erase operation, the ...

Page 18

Command Definitions Device operations are selected by writing specific commands into the CUI. commands. Table 2. Bus Operations Mode Notes RST# Reset Standby Output Disable Read 1,2 Read Identifier Codes Write 3,4 NOTES: 1. Refer to ...

Page 19

SRD = Data read from status register. See of the status register bits Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first ...

Page 20

Read Status Register Command The status register can be read at any time by writing the Read Status Register command to the CUI. After writing this command, all subsequent read operations output status register data until ...

Page 21

Table 5. Status Register Definition WSMS ESS SR.7 = WRITE STATE MACHINE STATUS (WSMS Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS (ESS Block Erase Suspended 0 = Block Erase in ...

Page 22

Block Erase Suspend/Resume Command The Block Erase Suspend command allows block erase interruption to read or program data in another block. Once the block erase process starts, writing the Block Erase Suspend command requests that the ...

Page 23

... These bits are reserved for future use. Set these bits to “0.” Undocumented combinations of bits RCR.10–9 are reserved by Intel Corporation for future implementations and should not be used. In the asynchronous page mode, the burst length always equals four words. Undocumented combinations of bits RCR.2– ...

Page 24

Read Configuration – (RCR.15) The device supports two high performance read configurations: Synchronous burst mode and asynchronous page mode. Bit RCR.15 in the read configuration register sets the read configuration to either synchronous burst or asynchronous ...

Page 25

Figure 7. Data Output with FCC Setting at Code 3 CLK (C) CE# ADV# A 15-0 DQ (D/Q) 15-0 NOTE: 1. Figure 7 shows the data output available and valid after 4 latencies from ADV# going low in the 1st ...

Page 26

Table 7. Frequency Configuration Settings Frequency Configuration Code NOTE: Table derived by using formulas (1), (2) and (3) in assumed and 4 ns respectively; value of t ...

Page 27

Figure 9. Output Configuration 4.9.4 Wait # Configuration – (RCR.8) The WAIT# configuration bit controls the behavior of the WAIT# output signal. This output signal can be set to be asserted during or one CLK cycle before an output delay ...

Page 28

Clock Configuration – (RCR.6) The clock configuration configures the device to start a burst cycle, output data, and assert WAIT# on the rising or falling edge of the clock. CLK flexibility helps ease 3 Volt Fast ...

Page 29

Figure 10. Automated Block Erase Flowchart Start Write 20H, Block Address Write D0H, Block Address Read Status Register 0 SR Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) ...

Page 30

Figure 11. Automated Program Flowchart Start Write 40H, Address Write Data and Address Read Status Register SR Full Status Check if Desired Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 ...

Page 31

Figure 12. Block Erase Suspend/Resume Flowchart Start Write B0H Read Status Register SR SR Read Read or Byte Write? Read Array No Data Done Yes Write D0H Block Erase Resumed Bus Operation Write Read Standby Standby ...

Page 32

Figure 13. Program Suspend/Resume Flowchart Start Write B0H Read Status Register SR SR Write FFH Read Array Data Done Reading Yes Write D0H Program Resumed 26 Bus Operation Write Read Standby 0 Standby ...

Page 33

Data Protection The 3 Volt Fast Boot Block Flash memory architecture features two hardware-lockable parameter blocks, so critical code can be kept secure while six other parameter blocks can be programmed or erased as necessary to facilitate EEPROM emulation. ...

Page 34

V Voltages PP Intel 3 Volt Fast Boot Block Flash memory provides in-system programming and erase at 2.7 V– 3.6 V (3.0 V–3.6 V for automotive temperature) V their manufacturing environment, this family of products includes ...

Page 35

System engineers should analyze the breakdown of standby time versus active time and quantify the respective power consumption in each mode for their specific application. This will provide a more accurate measure of application-specific power and energy requirements. 7.4 Power-Up/Down ...

Page 36

Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two- line control and proper de-coupling capacitor selection will suppress these transient voltage peaks. Each flash device should have a 0.1 µF ceramic capacitor connected ...

Page 37

Extended Temperature Operating Conditions Symbol T Operating Temperature Supply Voltage CC1 Supply Voltage CC2 Supply Voltage CC3 CC V I/O Voltage CCQ1 V I/O Voltage CCQ2 V I/O Voltage CCQ3 ...

Page 38

DC Characteristics—Extended Temperature V CC Sym Parameter V CCQ Note I Input Load Current 2 LI Output Leakage 2 Current I LO Output Leakage Current for WAIT Standby Current 3 ccs ...

Page 39

DC Characteristics, Continued V CC Sym Parameter V CCQ Note V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage Lock-Out Voltage 4 PPLK PP1 ...

Page 40

Figure 14. AC Input/Output Reference Waveform for V V CCQ 0V NOTE: AC test inputs are driven at V output timing ends conditions are when V Figure 15. AC Equivalent Testing Load Circuit NOTE: See ...

Page 41

AC Characteristics—Read-Only Operations Temperature # Symbol Parameter R1 t CLK Period CLK CLK High (Low) Time CLK Fall (Rise) Time CHCL R4 t Address Valid Setup to CLK AVCH R5 t ...

Page 42

Figure 16. AC Waveform for CLK Input Figure 17. AC Waveform for Single Asynchronous Read Operations from Parameter Blocks, Status Register, Identifier Codes (A) 19 ADV# ( ...

Page 43

Figure 18. AC Waveform for Asynchronous Page Mode Read Operations from Main Blocks (A) 19 (A) 1 R17 V IH ADV# ( CE# ( ...

Page 44

Figure 19. AC Waveform for Single Synchronous Read Operations from Parameter Blocks, Status Register, Identifier Codes V IH CLK [ [A] 19 R17 V IH ADV# [ ...

Page 45

Figure 20. AC Waveform for Synchronous Burst Read Operations, Four-Word Burst Length, from Main Blocks V IH CLK ( Valid A (A) 19-0 Address V IL R11 R17 V IH ADV# ( ...

Page 46

Figure 21. AC Waveform for Continuous Burst Read, Showing an Output Delay with Data Output Configuration Set to One Clock CLK (C) A 19-0 ADV# (V) CE# (E) OE# (G) WE# (W) WAIT# (T) DQ (D/Q) 15-0 ...

Page 47

AC Characteristics—Write Operations Temperature # Sym RST# High Recovery to WE# (CE#) Going Low PHWL PHEL CE# (WE#) Setup to WE# (CE#) Going Low ELWL WLEL Write ...

Page 48

Figure 23. AC Waveform for Write Operations Note (A) 20 ADV# ( CE# (WE#) [E(W OE# [ ...

Page 49

AC Characteristics—Reset Operation—Extended Temperature Figure 24. AC Waveform for Reset Operation V IH RST# ( RST# ( RST# ( Table 10. Reset Specifications Number Symbol RST# Low to Reset ...

Page 50

Extended Temperature Block Erase and Program Performance # Sym Program Time Block Program Time (Parameter) WHRH1 EHRH1 Block Program Time (Main) W19 Block Erase Time (Parameter WHRH2 EHRH2 Block Erase ...

Page 51

... DT28F160F3T120 TE28F160F3T120 DT28F160F3B120 TE28F160F3B120 DT28F160F3T95 TE28F160F3T95 DT28F160F3B95 TE28F800F3B95 DT28F800F3T120 TE28F800F3T120 DT28F800F3B120 TE28F800F3B120 DT28F800F3T95 TE28F800F3T95 DT28F800F3B95 TE28F800F3B95 NOTE: 1. The 56-ball µBGA package topside mark reads F160F3. All product shipping boxes or trays provide the correct information regarding bus architecture ...

Page 52

Additional Information Order Number 297939 210830 292213 298161 Contact your Intel Representative 297874 NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or ...

Related keywords