CY7C1327-133AC Cypress Semiconductor Corporation., CY7C1327-133AC Datasheet
CY7C1327-133AC
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CY7C1327-133AC Summary of contents
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... PowerPC is a trademark of IBM Corporation. Cypress Semiconductor Corporation PRELIMINARY Functional Description The CY7C1327 is a 3.3V 256K by 18 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock ...
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... DDQ Selection Guide Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA) PRELIMINARY 100-Lead TQFP CY7C1327 pinout 7C1327-166 3.5 420 2.0 2 CY7C1327 DDQ ...
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... Selects burst order. When tied to GND selects linear burst sequence. When tied left floating selects interleaved burst sequence. This is a strap pin and DDQ should remain static during device operation. No Connects. 3 CY7C1327 Description , CE , and and A are also loaded into ...
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... If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1327 is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ –DQ ...
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... CY7C1327 , ADSP, and ADSC must remain inactive for the 3 after the ZZ input returns LOW. ADSC ADV Hi-Z ...
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... Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 +150 C Operating Range +125 C 0.5V to +4.6V Range Com’l 0. 0.5V DDQ 0. 0.5V DDQ 6 CY7C1327 BWE ...
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... MHz 10-ns cycle, 100 MHz Max Device Deselected Test Conditions Min ZZ > > > < 0.2V 2t CYC 7 CY7C1327 Min. Max. Unit 3.135 3.6 V 3.135 3.6 V 2.4 V 0.4 V 2.0 V 0.3V V DDQ –0.3 0 – –5 ...
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... Tested initially and after any design or process changes that may affect these parameters. 7. Input waveform should have a slew rate of 1V/ns. PRELIMINARY Test Conditions MHz 3.3V 3.3V DDQ R=317 3.3V OUTPUT 5 pF R=351 GND INCLUDING JIG AND SCOPE (b) 8 CY7C1327 Max. Unit [7] ALL INPUT PULSES 3.0V ...
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... At any given voltage and temperature, t EOHZ PRELIMINARY [8,9,10] -166 -133 Min. Max. Min. 6 7.5 1.7 1.9 1.7 1.9 2.0 2.5 0.5 0.5 3.5 1.5 2.0 2.0 2.5 0.5 0.5 2.0 2.5 0.5 0.5 2.0 2.5 0.5 0.5 2.0 2.5 0.5 0.5 2.0 2.5 0.5 0.5 3 [9, 10] 3.5 [9,10 3.5 is less than t and t is less than t . EOLZ CHZ CLZ 9 CY7C1327 -117 -100 Max. Min. Max. Min. Max. 8.5 10 2.5 3.5 2.5 3.5 2.5 2.5 0.5 0.5 4 4.5 5.5 2.0 2.0 2.5 2.5 0.5 0.5 2.5 2.5 0.5 0.5 2.5 2.5 0.5 0.5 2.5 2.5 0.5 0.5 2.5 2.5 0.5 0.5 3.5 3.5 3 3.5 3.5 3 3.5 3.5 3.5 200 mV from Unit ns ...
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... WE is the combination of BWE & write cycle (see Write Cycle Descriptions table). = UNDEFINED PRELIMINARY Burst Write ADSP ignored with CE inactive masks ADSP define x = DON’T CARE 10 CY7C1327 Pipelined Write Unselected WD3 Unselected with CE 2 High ...
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... PRELIMINARY Burst Read ADSP ignored with Suspend Burst ADH masks ADSP EOHZ t DOH CLZ to define x = DON’T CARE = UNDEFINED 11 CY7C1327 Unselected Pipelined Read inactive 1 ADSC initiated read RD3 Unselected with CHZ ...
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... Single Write Burst Read CH t ADSP ignored with ADH RD3 masks ADSP 1 t EOHZ t DS See Note Out Out In to define x = DON’T CARE = UNDEFINED 12 CY7C1327 Unselected Pipelined Read inactive DOH Out Out Out t CHZ ...
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... ADH t WES ADSP ignored with CE HIGH 1 Q(D) , and GW to define a write cycle (see Write Cycle Description table). [1:0] and CE . All chip selects need to be active in order to select DON’T CARE = UNDEFINED 13 CY7C1327 CEH t WEH D (E) D (F) D (H) D (G) D(C) t DOH ...
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... ADSP HIGH ADSC CE 1 LOW CE 2 HIGH I/Os Notes: 11. Device must be deselected when entering ZZ mode. See Cycle Description for all possible signal conditions to deselect the device. 12. I/Os are in three-state when exiting ZZ sleep mode. PRELIMINARY t ZZS I (active CCZZ Three-state 14 CY7C1327 t ZZREC ...
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... CY7C1327L–133AC 117 CY7C1327–117AC 117 CY7C1327L–117AC 100 CY7C1327–100AC 100 CY7C1327L–100AC Document #: 38-00721 Package Diagram 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 © Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product ...