KM44C1003DJ-6 Samsung, KM44C1003DJ-6 Datasheet

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KM44C1003DJ-6

Manufacturer Part Number
KM44C1003DJ-6
Description
1M x 4-Bit CMOS Quad CAS DRAM with Fast Page Mode
Manufacturer
Samsung
Datasheet

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KM44C1003D
• Performance Range
This is a family of 1,048,576 x 4bit Fast Page Mode Quad CAS CMOS DRAMs. Fast Page Mode offers high speed random access of
memory cells within the same row. Access time (-5, -6 or -7), power consumption(Normal), and package type (SOJ or TSOP-II) are
optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. All
inputs and outputs are fully TTL compatible and four seperate CAS pins provide for seperate I/O operation allowing this device to oper-
ate in parity mode. This 1Mx4 Fast Page Mode DRAM family is fabricated using Samsung s advanced CMOS process to realize high
band-width, low power consumption and high reliability.
FEATURES
• Part Identification
• Active Power Dissipation
• Refresh Cycles
KM44C1003D
Speed
- KM44C1003D(5V)
-5
-6
-7
Speed
Part
NO.
-5
-6
-7
50ns
60ns
70ns
t
RAC
Refresh
cycle
Active power dissipation
1K
15ns
15ns
20ns
t
1M x 4bit CMOS Quad CAS DRAM with Fast Page Mode
CAC
470
415
360
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
Refresh Period
110ns
130ns
90ns
t
RC
Normal
16ms
Unit : mW
35ns
40ns
45ns
t
PC
DESCRIPTION
CAS0~3
A0~A9
RAS
W
FUNCTIONAL BLOCK DIAGRAM
• Fast Page Mode operation
• Four seperate CAS pins provide for seperate I/O
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Fast parallel test mode capability
• TTL compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in 26(24)-pin SOJ 300mil and TSOP(II)
• Single +5V 10% power supply
operation
300mil packages
Control
Row Address Buffer
Clocks
Col. Address Buffer
Refresh Counter
Refresh Control
Refresh Timer
VBB Generator
Column Decoder
Memory Array
Row Decoder
1,048,576 x 4
Cells
CMOS DRAM
Vcc
Vss
Data out
Data in
Buffer
Buffer
OE
DQ0
DQ3
to

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KM44C1003DJ-6 Summary of contents

Page 1

... TTL compatible and four seperate CAS pins provide for seperate I/O operation allowing this device to oper- ate in parity mode. This 1Mx4 Fast Page Mode DRAM family is fabricated using Samsung s advanced CMOS process to realize high band-width, low power consumption and high reliability. ...

Page 2

... KM44C1003D •KM44C1003DJ DQ0 1 DQ1 RAS 4 CAS0 5 CAS1 SOJ ) PIN CONFIGURATION (Top Views DQ3 22 DQ2 21 CAS3 20 OE CAS0 19 CAS2 CAS1 18 N Pin Name Pin function Address Inputs ...

Page 3

KM44C1003D ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative Voltage on V supply relative Storage Temperature Power Dissipation Short Circuit Output Current * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are ...

Page 4

KM44C1003D DC AND OPERATING CHARACTERISTICS Symbol Power I Don t Care CC1 I Don t Care CC2 I Don t Care CC3 I Don t Care CC4 Normal I CC5 L I Don t Care CC6 Operating ...

Page 5

KM44C1003D CAPACITANCE (T = Parameter Input capacitance [A0 ~ A9] Input capacitance [RAS, CAS0-3, W, OE] Output capacitance [DQ0 - DQ3] AC CHARACTERISTICS ( Test condition : V =5.0V 10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V CC Parameter Random ...

Page 6

KM44C1003D AC CHARACTERISTICS (Continued) Parameter Refresh period (4K, Normal) Refresh period (L-ver) Write command set-up time CAS to W delay time RAS to W delay time Column address to W delay time CAS precharge to W delay time CAS set-up ...

Page 7

KM44C1003D TEST MODE CYCLE Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address RAS pulse width CAS pulse width RAS hold time CAS hold time Column ...

Page 8

KM44C1003D NOTES An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles 1. before proper device operation is achieved (min) and V (max) are reference levels for measuring timing ...

Page 9

KM44C1003D READ CYCLE NOTE : D = OPEN OUT RAS CAS0 CAS1 CAS2 ...

Page 10

KM44C1003D WRITE CYCLE ( EARLY WRITE ) RAS CAS0 CAS1 CAS2 CAS3 V ...

Page 11

KM44C1003D WRITE CYCLE ( OE CONTROLLED WRITE ) RAS CAS0 CAS1 CAS2 CAS3 ...

Page 12

KM44C1003D READ - MODIFY - WRTIE CYCLE RAS CAS0 CAS1 CAS2 CAS3 V ...

Page 13

KM44C1003D FAST PAGE READ CYCLE NOTE : D = OPEN OUT RAS CRP CAS0 CAS1 CAS2 V - ...

Page 14

KM44C1003D FAST PAGE WRITE CYCLE ( EARLY WRITE ) RAS CRP CAS0 CAS1 CAS2 ...

Page 15

KM44C1003D FAST PAGE READ - MODIFY - WRITE CYCLE RAS CAS0 CAS1 CAS2 ...

Page 16

KM44C1003D RAS - ONLY REFRESH CYCLE NOTE : W, OE Don t care OPEN OUT RAS CRP CASX ASR V - ...

Page 17

KM44C1003D HIDDEN REFRESH CYCLE ( READ ) RAS CASX ...

Page 18

KM44C1003D HIDDEN REFRESH CYCLE ( WRITE ) NOTE : D = OPEN OUT RAS CASX ...

Page 19

KM44C1003D CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE RAS CSR CASX READ CYCLE t WRP ...

Page 20

KM44C1003D CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE Don t care RAS CASX DQ0 ~ DQ3 ...

Page 21

KM44C1003D PACKAGE DIMENSION 26(24) SOJ 300mil #26(24) 0.0375 (0.95) 26(24) TSOP(II) 300mil 0.037 (0.95) 0.691 (17.55) MAX 0.670 (17.03) 0.680 (17.28) 0.050 (1.27) 0.026 (0.66) 0.032 (0.81) 0.015 (0.38) 0.021 (0.53) 0.691 (17.54) MAX 0.671 (17.04) 0.047 (1.20) 0.679 (17.24) ...

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