W986416CH-7 Winbond, W986416CH-7 Datasheet
W986416CH-7
Related parts for W986416CH-7
W986416CH-7 Summary of contents
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... Using pipelined architecture and 0.20um process technology, W986416CH delivers a data bandwidth 332M bytes per second (-6). For different application, W986416CH is sorted into four speed grades: -6, -7, -75 and -8H. The -6 parts can run up to 166Mhz/CL3. The -7 parts can run up to 143Mhz/CL3 specification. The -75 parts can run up to PC133/CL3 specification ...
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BLOCK DIAGRAM CLK CLOCK BUFFER CKE CS CONTROL SIGNAL GENERATOR RAS COMMAND CAS DECODER WE A10 MODE REGISTER A0 ADDRESS BUFFER A9 A11 BS0 BS1 REFRESH COLUMN COUNTER COUNTER Revision 1 bit x 4 Banks SDRAM COLUMN ...
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... Power for input buffers and logic circuit inside DRAM. Ground for input buffers and logic circuit inside DRAM. Separated power from V , used for output buffers to improve CC noise. Separated ground from V , used for output buffers to improve SS noise. No connection - 3 - W986416CH Publication Release Date: June, 1999 ...
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Pin Assignment (Top View) Revision 1 bit x 4 Banks SDRAM DQ0 DQ1 4 DQ2 DQ3 7 DQ4 DQ5 ...
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... Input/Output capacitance O Note: These parameters are periodically sampled and not 100% tested. Revision 1 bit x 4 Banks SDRAM ITEM RATING -0.3~V +0.3 CC -0.3~4.6 0~70 -55~150 260 1 50 MIN TYP 3.0 3.3 3.0 3.3 2.0 - -0.3 - PARAMETER - 5 - W986416CH UNIT NOTES °C 1 °C 1 ° °C MAX UNIT NOTES 3 3 ...
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... CL*=3 6 1000 7 1000 2.5 2.5 2.5 2.5 CL*= CL*=3 5 5 0.3 10 0.3 10 1.5 1.5 0.8 0.8 1.5 1.5 0.8 0.8 1.5 1.5 0.8 0.8 1.5 1.5 0.8 0 W986416CH -75(PC133) -8H(PC100) MIN MAX MIN MAX 10000 48 10000 7 1000 10 1000 7.5 1000 8 1000 2 5.4 6 2.7 3 2 0.3 10 ...
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... I IH CC2S (Power Down mode CC2PS I IH CC3 (Power Down mode CC3P I CC4 I CC5 I CC6 SYMBOL I I( W986416CH -6 -7/-75(PC133) -8H(PC100) MAX. MAX. MAX 130 115 110 155 ...
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... These parameters depend on the output loading conditions. Specified values are obtained with output open. The W986416CH-6/-7/-75/-8H is tested with 50pF output load. 5. Power up sequence is further described in the "Functional Description" section TESTING CONDITIONS Output Reference Level Output Load Input Signal Levels ...
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... W986416CH A11, A10 CS RAS CAS A9 ...
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... V CC RCD (max). RAS delay. WE pin voltage level defines whether the access cycle is a read operation RCD - 10 - W986416CH supplies. After power up, CC has elapsed. Please refer to the next page for RSC ). Once a bank has been activated it must be ). The minimum RC ...
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Burst Read Command The Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for ...
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Table 2 Address Sequence of Sequential Mode DATA Access Address Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 . Addressing Sequence of Sequential Mode A column access is performed by increasing the ...
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... The bank undergoing auto-precharge can not be reactivated until t DPL = DAL DPL ). RP cycle time plus the Self Refresh exit time the device. REF - 13 - W986416CH ) has been satisfied. Issue of Auto-Precharge RP ). When using the Auto-precharge Command, the RP RAS Publication Release Date: June, 1999 and t are DPL RP (min). (min) + ...
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No Operation Command The No Operation Command should be used in cases when the SDRAM idle or a wait state to prevent the SDRAM from registering any unwanted commands between operations Operation Command is registered ...
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... CKS CKH CKE Revision 1 bit x 4 Banks SDRAM t t CMS CMH t t CMS CMH t t CMS CMH t t CMS CMH CKH CKS - 15 - W986416CH CMH t t CKS CKH Publication Release Date: June, 1999 t CMS ...
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... Read Timing CLK CS RAS CAS WE A0-A11 BS0 Read Command Revision 1 bit x 4 Banks SDRAM Read CAS Latency Data-Out - 16 - W986416CH Valid Valid Data-Out Burst Length Publication Release Date: June, 1999 ...
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... CMS CMH CMS Valid Valid Data-Out Data-Out CKS CKH CKS Valid Data-Out - 17 - W986416CH Valid Valid Data-in Data- Valid Valid Data-in Data- Valid Data-Out ...
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... Reserved Reserved A0 Single Write Mode Burst read and Burst write Burst read and single write A0 Publication Release Date: June, 1999 - 18 - W986416CH next command Interleave Reserved A0 ...
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... RAS t RCD RBb RAc RBb CBx RAc t AC aw0 aw1 aw2 aw3 bx0 t RRD Precharge Active Active Read - 19 - W986416CH RAS RCD RCD RBd CAy RBd t AC bx3 cy2 bx1 bx2 cy0 ...
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... RAS t RCD t RCD RAc CBx RAc aw0 aw1 aw2 aw3 bx0 t RRD AP* Active Read - 20 - W986416CH RAS RAS t RCD RBd CAy CBz RBd t AC bx1 bx2 bx3 ...
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Interleaved Bank Read (Burst Length=8, CAS Latency= CLK CS RAS CAS WE BS0 BS1 t RCD A10 RAa A0-A9 RAa CAx A11 DQM CKE DQ t RRD Read Active Bank #0 Bank #1 Precharge Bank ...
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Interleaved Bank Read (Burst Length=8, CAS Latency=3, Autoprecharge CLK CS RAS CAS WE BS0 BS1 t RCD A10 RAa A0-A9 CAx RAa DQM CKE DQ t RRD Read Bank #0 Active Bank #1 Bank #2 Idle ...
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... RC t RAS t RCD RBb RBb CBy ax4 ax5 ax6 ax7 by0 by1 by2 t RRD Precharge Active Write - 23 - W986416CH RAS t RAS t RCD RAc RAc CAz by3 by4 by5 by6 by7 CZ0 Active Write Publication Release Date: June, 1999 ...
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Interleaved Bank Write (Burst Length=8, Autoprecharge CLK CS RAS CAS WE BS0 BS1 t RCD RAa A10 A0-A9, CAx RAa A11 DQM CKE ax0 ax1 DQ t RRD Active Write Bank #0 Bank #1 Bank ...
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... RAS t RAS t RCD CBx CAy CAm bx0 Ay0 a2 bx1 Read Read Read * AP is the internal precharge start timing - 25 - W986416CH CCD t RP CBz am1 am2 bz0 bz1 bz2 Ay1 Ay2 am0 Precharge ...
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... Banks SDRAM (CLK = 100 MHz RAS t AC ax5 ax0 ax1 ax3 ax2 ax4 W986416CH CAy t WR ay1 ay0 ay2 ay4 ay3 Write Precharge Publication Release Date: June, 1999 21 ...
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... MHz RAb RAb t AC aw0 aw1 aw2 aw3 AP* Active * AP is the internal precharge start timing - 27 - W986416CH RAS t RCD CAx t AC bx0 bx1 Read AP* Publication Release Date: June, 1999 21 22 ...
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... MHz RCD RAb RAb CAx bx0 aw3 Active Write AP the internal precharge start timing - 28 - W986416CH RAS RP bx1 bx3 bx2 AP* Publication Release Date: June, 1999 RAc ...
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... CAS WE BS0,1 A10 A0-A9, A11 DQM CKE DQ All Banks Auto Prechage Refresh Revision 1 bit x 4 Banks SDRAM (CLK = 100 MHz W986416CH Auto Refresh (Arbitrary Cycle) Publication Release Date: June, 1999 22 23 ...
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... All Banks Self Refresh Precharge Entry Revision 1 bit x 4 Banks SDRAM (CLK = 100 MHz CKS t SB Self Refresh Cycle - 30 - W986416CH CKS Operation Cycle Publication Release Date: June, 1999 Arbitrary Cycle ...
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... MHz CBw t AC av0 av1 av3 aw0 av2 Single Write - 31 - W986416CH CBz CBx CBy t AC ax0 ay0 az1 az2 az0 Read Publication Release Date: June, 1999 21 ...
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... Banks SDRAM (CLK = 100 MHz CAa t CKS ax0 ax1 ax2 ax3 Wrate Precharge - 32 - W986416CH RAa RAa CKS NOPActive Precharge Standby Power Down mode Publication Release Date: June, 1999 22 23 ...
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... Act represents the Read with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command. (min). RAS - 33 - W986416CH Act Act AP Act Publication Release Date: June, 1999 ...
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... RP AP Act represents the Write with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command W986416CH Act AP Act Act Publication Release Date: June, 1999 ...
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... Note ) The Output data must be masked by DQM to avoid I/O conflict Revision 1 bit x 4 Banks SDRAM Read Write Read Write Read Write Read Write W986416CH Publication Release Date: June, 1999 11 ...
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... DQ (2) CAS Latency=3 Write ( a ) Command DQM DQ D0 Write ( b ) Command DQM D0 DQ Revision 1 bit x 4 Banks SDRAM Read Q0 Q1 Read D1 Q0 Read Q0 Read W986416CH Publication Release Date: June, 1999 10 11 ...
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... Read Command DQ (2) Write cycle Write Command BST Note ) Revision 1 bit x 4 Banks SDRAM BST BST BST represents the Burst stop command - 37 - W986416CH Publication Release Date: June, 1999 ...
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... Write Commad DQM D0 DQ Note ) Revision 1 bit x 4 Banks SDRAM PRCG PRCG PRCG PRCG PRCG represents the Precharge command - 38 - W986416CH Publication Release Date: June, 1999 11 ...
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... CKE DQM D1 DQ Revision 1 bit x 4 Banks SDRAM DQM MASK ( DQM MASK ( CKE MASK ( W986416CH CKE MASK CKE MASK Publication Release Date: June, 1999 ...
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... DQ 1 CLK cycle No. External CLK Internal CKE DQM Q1 DQ Revision 1 bit x 4 Banks SDRAM W986416CH Open Open Open Publication Release Date: June, 1999 ...
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Self Refresh/Power Down Mode Exit Timing Asynchronous Control Input Buffer turn on time ( Power down mode exit time ) is specified < t (min)+t CK CKS CLK CKE Command B) t >= t (min) ...
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Package Dimension 54L TSOP (II)-400 mil Controlling Dimension : Millimeters SYMBOL Revision 1 bit x 4 Banks SDRAM e ...