W78C31B-40 Winbond, W78C31B-40 Datasheet

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W78C31B-40

Manufacturer Part Number
W78C31B-40
Description
8-BIT MICROCONTROLLER
Manufacturer
Winbond
Datasheet

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W78C31B-40
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WINBOND
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GENERAL DESCRIPTION
The W78C31B microcontroller supplies a wider frequency range than most 8-bit microcontrollers on
the market. It is compatible with the industry standard 80C31 microcontroller series.
The W78C31B contains four 8-bit bidirectional parallel ports, two 16-bit timer/counters, and a serial
port. These peripherals are supported by a five-source, two-level interrupt capability. There are 128
bytes of RAM, and the device supports ROMless operation for application programs.
The W78C31B microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
FEATURES
8-bit CMOS microcontroller
Fully static design
Low standby current at full supply voltage
DC-40 MHz operation
128 bytes of on-chip scratchpad RAM
ROMless operation
64K bytes program memory address space
64K bytes data memory address space
Four 8-bit bidirectional ports
Two 16-bit timer/counters
One full duplex serial port
Boolean processor
Five
Built-in power management
Packages:
DIP 40: W78C31B-16/24/40
PLCC 44: W78C31BP-16/24/40
QFP 44: W78C31BF-16/24/40
TQFP 44: W78C31BM-16/24/40
-source, two-level interrupt capability
8-BIT MICROCONTROLLER
- 1 -
Publication Release Date: October 1997
W78C31B
Revision A3

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W78C31B-40 Summary of contents

Page 1

... The W78C31B microcontroller supplies a wider frequency range than most 8-bit microcontrollers on the market compatible with the industry standard 80C31 microcontroller series. The W78C31B contains four 8-bit bidirectional parallel ports, two 16-bit timer/counters, and a serial port. These peripherals are supported by a five-source, two-level interrupt capability. There are 128 bytes of RAM, and the device supports ROMless operation for application programs ...

Page 2

... ALE 12 29 INT0, P3.2 PSEN 13 28 P2.7, A15 INT1, P3.3 14 T0, P3.4 27 P2.6, A14 15 T1, P3.5 26 P2.5, A13 16 WR, P3.6 25 P2.4, A12 17 24 P2.3, A11 RD, P3 P2.2, A10 XTAL2 19 XTAL1 22 P2. VSS 21 P2.0, A8 44-Pin QFP/TQFP (W78C31BF/W78C31BM P1.5 P0.4, AD4 39 38 P1.6 P0.5, AD5 37 P1.7 P0.6, AD6 RST 36 P0.7, AD7 RXD, P3 TXD, P3.1 ...

Page 3

... P3.7 EA External Address Input, active low. This pin forces the processor to execute out of external ROM. This pin should be kept low for all W78C31B operations. RST Reset Input, active high. This pin resets the processor. It must be kept high for at least two machine cycles in order to be recognized by the processor. ...

Page 4

... Power Supplies. These are the chip ground and positive supplies. BLOCK DIAGRAM RAM 128 Bytes PSEN enables the external ROM onto the Port 0 PSEN goes to a high state during reset with a SFR CPU Data Bus CORE Interrupt - 4 - W78C31B Port 0 Port 1 Port 2 Port 3 Alternate Serial Port Timer 0 Timer 1 INT 0 INT 1 ...

Page 5

... The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to deglitch the reset line when the W78C31B is used with an external RC network. The reset logic also has a special glitch removal circuit that ignores glitches on the reset line ...

Page 6

... < V < 4.5V OL1 OL1 4.5V OL2 OL2 4.5V OH1 -100 A OH1 4.5V OH2 -400 A OH2 - 6 - W78C31B MAX. UNIT +7.0 -0 +150 SPECIFICATION MIN. TYP. MAX. 4 -75 - +10 - +184 +350 - 0.45 2 ...

Page 7

... 4.5V IL2 5.5V IH1 5.5V IH2 OP, CP SYMBOL MIN. TYP W78C31B SPECIFICATION MIN. TYP. MAX 0 0.8 2 +0 and actual parts will CP MAX. UNIT NOTES - 40 MHz - - Publication Release Date: October 1997 Revision A3 ...

Page 8

... DAD CP DWD CP DWR CP CP SYMBOL MIN. TYP PDS PDH PDA W78C31B MAX. UNIT NOTE MAX. UNIT NOTE S nS ...

Page 9

... Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to ALE, since it provides a convenient reference. Publication Release Date: October 1997 - 9 - W78C31B Revision A3 ...

Page 10

... Data Read Cycle S4 S5 XTAL1 ALE PSEN PORT 2 A0-A7 PORT ALW T APL T PSW T AAS A8-A15 T PDA T T PDH, PDZ A0-A7 A0-A7 Code A0-A7 Data A8-A15 DATA T T DAR DDA T DDH, T DRD - 10 - W78C31B Data A0- DDZ ...

Page 11

... XTAL1 ALE PSEN PORT 2 PORT 0 A0-A7 WR Port Access Cycle XTAL1 ALE T PDS PORT INPUT SAMPLE A8-A15 DATA OUT T T DWD DAD T T DAW DWR PDH - 11 - W78C31B PDA DATA OUT Publication Release Date: October 1997 Revision A3 ...

Page 12

... P2.6 P1.0 28 A15 P2.7 P1 P1.4 PSEN 29 P1.5 ALE 30 P1.6 TXD 11 P1.7 RXD 10 W78C31B Figure 30P 30P 15P 15P 10P 10P W78C31B O0 11 AD0 AD1 AD2 AD3 ...

Page 13

... A10 P2.2 23 A11 P2.3 24 74LS373 INT1 P2.4 25 A12 T0 P2.5 26 A13 T1 P2.6 27 A14 P2.7 28 P1 P1.3 29 P1.4 PSEN 30 P1.5 ALE 11 P1.6 TXD 10 P1.7 RXD W78C31B Figure W78C31B AD0 AD1 AD2 AD3 AD4 A4 ...

Page 14

... E Base Plane A 1 Seating Plane W78C31B Dimension in inch Dimension in mm Symbol Min. Nom. Max. Min. Nom. Max. 5.334 A 0.210 0.010 0.254 0.150 0.155 0.160 3.81 3.937 4.064 2 B 0.016 0.018 ...

Page 15

... See Detail F Seating Plane Detail Detail W78C31B Dimension in inch Dimension in mm Symbol Min. Nom. Max. Min. Nom. Max. A --- --- --- --- --- --- A 0.002 0.01 0.02 0.05 0.25 0 0.075 0.081 0.087 1.90 2.05 2. 0.01 0.014 0.018 ...

Page 16

... TEL: 886-2-7190505 FAX: 886-2-7197502 Note: All data and specifications are subject to change without notice. Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 - 16 - W78C31B ...

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