K4G323222M-QC60 Samsung, K4G323222M-QC60 Datasheet
K4G323222M-QC60
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K4G323222M-QC60 Summary of contents
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... DQMi SERIAL COUNTER GENERAL DESCRIPTION The K4G323222M is 33,554,432 bits synchronous high data rate Dynamic RAM organized 524,288 words by 32 bits, fabricated with SAMSUNG s high performance CMOS technol- ogy. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle ...
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... K4G323222M PIN CONFIGURATION (TOP VIEW) DQ29 SSQ DQ30 83 DQ31 N.C 86 N.C 87 N.C 88 N.C 89 N.C 90 N.C 91 N.C 92 N.C 93 N DQ0 97 DQ1 SSQ DQ2 100 PIN CONFIGURATION DESCRIPTION PIN NAME CLK System Clock CS Chip Select CKE Clock Enable A0 ~ A10 Address BA Bank Select Address ...
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... AC. The undershoot voltage duration Any input DDQ Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs. 4. Dout is disabled OUT 5. The VDD condition of K4G323222M-45/50/55/60 is 3.135V~3.6V. CAPACITANCE ( 3.3V DDQ Pin Clock RAS, CAS, WE, CS, CKE, DQM Address DQ ...
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... Unless otherwise notes, Input level is CMOS(V 2. Measured with outputs open. Addresses are changed only one time during tcc(min). 3. Refresh period is 32ms. Addresses are changed only one time during tcc(min). 4. K4G323222M-C* 5. K4G323222M-L* : Low Power version = Test Condition Burst Length =1 ...
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... Input rise and fall time Output timing measurement reference level Output load condition Output 870 (Fig Output Load Circuit Note : 1. The VDD condition of K4G323222M-45/50/55/60 is 3.135V~3.6V. OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter CAS Latency CLK cycle time Row active to row active delay ...
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... K4G323222M Parameter CLK cycle time Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time 2. Minimum delay is required to complete write. 3. This parameter means minimum CAS to CAS delay at block write cycle only case of row precharge interrupt, auto precharge and read burst stop. ...
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... K4G323222M SIMPLIFIED TRUTH TABLE COMMAND Register Mode Register Set Special Mode Register Set Refresh Auto Refresh Entry Self Refresh Exit Bank Active Write Per Bit Disable & Row Addr. Write Per Bit Enable Read & Auto Precharge Disable Column Auto Precharge Enable Address Write & ...
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... K4G323222M SIMPLIFIED TRUTH TABLE 3. Auto refresh functions as same as CBR refresh of DRAM. The automatical precharge without Row precharge command is meant by "Auto". Auto/Self refresh can be issued only at both precharge state Bank select address. If "Low" at read, (block) write, Row active and precharge, bank A is selected. ...
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... K4G323222M MODE REGISTER FIELD TABLE TO PROGRAM MODES Register Programmed with MRS Address Function RFU (Note 1) Test Mode A A Type Mode Register Set 0 1 Vendor Use 1 0 Only 1 1 Write Burst Length A Length 9 0 Burst 1 Single Bit Special Mode Register Programmed with SMRS ...
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... K4G323222M BURST SEQUENCE (BURST LENGTH = 4) Initial address BURST SEQUENCE (BURST LENGTH = 8) Initial address ...
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... K4G323222M DEVICE OPERATIONS CLOCK (CLK) The clock input is used as the reference for all SGRAM opera- tions. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between V and V . During operation with CKE high all inputs are ...
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... K4G323222M DEVICE OPERATIONS BANK ACTIVATE The bank activate command is used to select a random row in an idle bank. By asserting low on RAS and CS with desired row and bank addresses, a row access is initiated. The read or write operation can occur after a time delay bank activation. t ...
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... K4G323222M DEVICE OPERATIONS (Continued) Entry to Power Down, Auto refresh, Self refresh and Mode reg- ister Set etc. is possible only when both banks are in idle state. AUTO PRECHARGE The precharge operation can also be performed by using auto precharge. The SGRAM internally generates the timing to satisfy t (min) and " ...
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... K4G323222M DEVICE OPERATIONS (Continued) WRITE PER BIT Write per bit(i.e. I/O mask mode) for SGRAM is a function that selectively masks bits of data being written to the devices. The mask is stored in an internal register and applied to each bit of data written when the mask is enabled. Bank active command with DSF=High enables write per bit for associated bank ...
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... K4G323222M SUMMARY OF 4M Byte SGRAM BASIC FEATURES AND BENEFITS Features 512K SGRAM Interface Bank Page Depth / 1 Row Total Page Depth Burst Length(Read Full Page Full Page Burst Length(Write) Burst Type Sequential & Interleave CAS Latency ...
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... K4G323222M BASIC FEATURE AND FUNCTION DESCRIPTIONS 1. CLOCK Suspend 1) Clock Suspended During Write (BL=4) CLK CMD WR CKE Internal CLK DQ(CL2 DQ(CL3 Note : CKE to CLK disable/enable=1 clock 2. DQM Operation 1) Write Mask (BL=4) CLK WR CMD DQMi Note 1 DQ(CL2 DQ(CL3 ...
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... K4G323222M 3. CAS Interrupt (I) 1) Read interrupted by Read (BL=4) CLK CMD ADD DQ(CL2) QA DQ(CL3) t CCD Note 2 2) Write interrupted by(Block) Write (BL=2) CLK CMD CCD Note ADD CDL Note 3 4) Block Write to Block Write CLK CMD BW BW ...
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... K4G323222M 4. CAS Interrupt (II) : Read Interrupted by Write & DQM (1) CL=2, BL=4 CLK i) CMD RD DQM DQ RD ii) CMD DQM DQ iii) CMD RD DQM DQ iv) CMD RD DQM DQ (2) CL=3, BL=4 CLK i) CMD RD DQM DQ ii) CMD RD DQM DQ iii) CMD RD DQM DQ iv) CMD RD DQM DQ v) CMD RD DQM DQ *Note : 1. To prevent bus contention, there should be at least one gap between data in and data out. ...
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... K4G323222M 5. Write Interrupted by Precharge & DQM CLK CMD WR DQM *Note : 1. To inhibit invalid write, DQM should be issued. 2. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of dual banks operation. ...
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... K4G323222M 8. Burst Stop & Precharge Interrupt 1) Write Interrupted by Precharge (BL=4) CLK WR CMD DQM Read Interrupted by Precharge (BL=4) CLK CMD RD DQ(CL2) DQ(CL3) 9. MRS & SMRS 1) Mode Register Set CLK CMD PRE *Note : CLK, Last Data in to Row Precharge. RDL CLK, Last Data in to Burst Stop Delay. ...
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... K4G323222M 10. Clock Suspend Exit & Power Down Exit 1) Clock Suspend (=Active Power Down) Exit CLK CKE Internal Note 1 CLK CMD 11. Auto Refresh & Self Refresh Note 3 1) Auto Refresh CLK Note 4 CMD PRE CKE Note 6 2) Self Refresh CLK Note 4 CMD ...
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... K4G323222M 12. About Burst Type Control Sequential Counting Basic MODE Interleave Counting Pseudo- Decrement Sequential Counting Pseudo- MODE Pseudo- Binary Counting Random column Access Random t MODE = 1 CLK CCD 13. About Burst Length Control 1 2 Basic 4 MODE 8 Full Page BRSW Special MODE Block Write ...
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... K4G323222M 14. Mask Functions 1) Normal Write I/O masking : By Mask at Write Per Bit Mode, the selected bit planes keep the original data. If bit plane 15, 22, 24, and 31 keep the original value. i) STEP - SMRS(LMR) :Load mask[31-0]="0111, 1110, 1011,1111, 0111, 1101, 0111, 0110" - Row Active with DSF "H" :Write Per Bit Mode Enable - Perform Normal Write ...
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... K4G323222M (Continued) Pixel and I/O masking : By Mask at Write Per Bit Mode, the selected bit planes keep the original data. By Pixel Data issued through DQ pin, the selected pixels keep the original data. See PIXEL TO DQ MAPPING TABLE. Assume 8bpp, White = "0000,0000", Red="1010,0011", Green ="1110,0001", Yellow ="0000,1111", Blue ="1100,0011" ...
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... K4G323222M Power On Sequence & Auto Refresh CLOCK CKE High level is necessary CS tRP RAS CAS ADDR DSF DQM High level is necessary High-Z DQ Precharge Auto Refresh (All Banks tRC Auto Refresh CMOS SGRAM ...
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... K4G323222M Single Bit Read-Write-Read Cycle(Same Page) @CAS Latency=3, Burst Length CLOCK t CC CKE *Note RCD t SH RAS CAS ADDR *Note 2 *Note 2 *Note *Note 5 DSF t SS DQM t RAC DQ Row Active ...
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... K4G323222M *Note : 1. All input can be don't care when CS is high at the CLK high going edge. 2. Bank active & read/write are controlled by BA Enable and disable auto precharge function are controlled / /AP and BA control bank precharge when precharge command is asserted. ...
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... K4G323222M Read & Write Cycle at Same Bank @Burst Length CLOCK CKE CS t RCD RAS CAS Ra Ca0 ADDR / DSF DQM DQ (CL=2) t RAC *Note 3 DQ (CL=3) t RAC *Note 3 Row Active Read (A-Bank) (A-Bank) *Note : 1. Minimum row cycle times is required to complete internal DRAM operation. ...
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... K4G323222M Page Read & Write Cycle at Same Bank @Burst Length CLOCK CKE CS t RCD RAS CAS ADDR Ra Ca0 DSF DQM DQ (CL=2) DQ (CL=3) Row Active Read (A-Bank) (A-Bank) *Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus contention. ...
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... K4G323222M Block Write cycle(with Auto Precharge CLOCK CKE CS RAS CAS *Note 2 RAa CAa ADDR BA A /AP RAa 8 WE DSF DQM *Note 1 Pixel DQ Mask Row Active with Masked Write-per-Bit Block Write Enable (A-Bank) (A-Bank) Block Write with Auto Precharge *Note : 1. Column Mask(DQi=L : Mask, DQi=H :Non Mask) 2 ...
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... K4G323222M SMRS and Block/Normal Write @ Burst Length CLOCK CKE CS RAS CAS A RAa 0-2 A RAa 3,4,7,8 A RAa 5 A RAa 6 A /AP RAa DSF DQM I/O DQ Color Mask Load Color Load Mask Register Register Row Active with WPB* Enable (A-Bank) *Note : 1. At the next clock of special mode set command, new command is possible. ...
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... K4G323222M Page Read Cycle at Different Bank @Burst Length CLOCK CKE *Note 1 CS RAS CAS ADDR RAa CAa BA A /AP RAa 8 WE DSF DQM DQ (CL=2) DQ (CL=3) Row Active (A-Bank) Read (A-Bank) *Note : 1. CS can be don t care when RAS, CAS and WE are high at the clock high going edge. ...
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... K4G323222M Page Write Cycle at Different Bank @Burst Length CLOCK CKE CS RAS CAS RAa Key CAa ADDR BA A /AP RAa 8 WE DSF DQM DQ Mask DAa0 DAa1 DAa2 Load Mask Register Row Active with Masked Write Write-Per-Bit (A-Bank) enable (A-Bank ...
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... K4G323222M Read & Write Cycle at Different Bank @Burst Length CLOCK CKE CS RAS CAS ADDR RAa CAa BA A /AP RAa 8 WE DSF DQM DQ (CL=2) DQ (CL=3) Row Active Read (A-Bank) (A-Bank) t *Note : 1. should be met to complete write. CDL HIGH RBb RBb ...
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... K4G323222M Read & Write Cycle with Auto Precharge I @Burst Length CLOCK CKE CS RAS CAS RAa ADDR RBb BA A /AP RAa RBb 8 WE DSF DQMi DQ (CL=2) DQ (CL=3) Row Active (A-Bank) Row Active (B-Bank) *Note : t 1. should be controlled to meet minimum RCD (In the case of Burst Length=1 & 2, BRSW mode and Block write) ...
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... K4G323222M Read & Write Cycle with Auto Precharge II @Burst Length CLOCK CKE CS RAS CAS ADDR / DSF DQM DQ (CL=2) DQ (CL=3) Row Active (A-Bank) Row Active (B-Bank) *Note: 1. When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation. ...
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... K4G323222M Read & Write Cycle with Auto Precharge III @Burst Length CLOCK CKE CS RAS CAS ADDR / DSF DQM DQ (CL=2) DQ (CL=3) Row Active (A-Bank) *Note : 1. Any command to A-bank is not allowed in this period. tRP is determined from at auto precharge start point ...
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... K4G323222M Read Interrupted by Precharge Command & Read Burst Stop Cycle (@Full page Only CLOCK CKE CS RAS CAS ADDR RAa CAa BA *Note 1 A /AP RAa 8 WE DSF DQM DQ (CL=2) DQ (CL=3) Row Active Read (A-Bank) (A-Bank) *Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible. ...
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... K4G323222M Write Interrupted by Precharge Command & Write Burst Stop Cycle (@ Full page Only CLOCK CKE CS RAS CAS ADDR RAa CAa BA *Note 1 RAa A / DSF DQM DQ DAa0 DAa1 DAa2 DAa3 DAa4 Row Active Write (A-Bank) (A-Bank) *Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible. ...
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... K4G323222M Burst Read Single bit Write Cycle @Burst Length=2, BRSW CLOCK *Note 1 CKE CS RAS CAS ADDR RAa CAa BA A /AP RAa 8 WE DSF DQMi DQ DAa0 (CL=2) DQ DAa0 (CL=3) Row Active (A-Bank) Write (A-Bank) *Note : 1. BRSW mode is enabled by setting A At the BRSW Mode, the burst length at write is fixed to "1" regardless of programed burst length. ...
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... K4G323222M Clock suspension & DQM operation cycle @CAS Latency=2, Burst Length CLOCK CKE CS RAS CAS ADDR / DSF DQM DQ Row Active Read *Note : 1. DQM needed to prevent bus contention Qa0 Qa1 Qa2 Qa3 ...
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... K4G323222M Active/Precharge Power Down Mode @CAS Lantency=2, Burst Length CLOCK t SS *Note 1 CKE *Note 3 CS RAS CAS ADDR DSF DQM DQ Precharge Power-down Entry *Note : 1. All banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least "1CLK + 3 ...
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... K4G323222M Self Refresh Entry & Exit Cycle CLOCK *Note 2 *Note 1 CKE RAS *Note 7 CAS ADDR DSF DQM DQ Hi-Z Self Refresh Entry *Note : TO ENTER SELF REFRESH MODE 1. CS, RAS & CAS with CKE should be low at the same clock cycle. ...
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... K4G323222M Mode Register Set Cycle CLOCK HIGH CKE CS *Note 2 RAS *Note 1 CAS *Note 3 ADDR Key Ra WE DSF DQM DQ Hi-Z MRS New Command * Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle. MODE REGISTER SET CYCLE *Note : 1. CS, RAS, CAS, & ...
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... K4G323222M FUNCTION TRUTH TABLE(TABLE 1) Current CS RAS State IDLE Row L H Active Read ...
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... K4G323222M FUNCTION TRUTH TABLE(TABLE 1, Continued) Current CS RAS State Write Read with Auto L H Precharge Write with L H Auto L H Precharge Precharging ...
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... K4G323222M FUNCTION TRUTH TABLE (TABLE 1, Continued) ABBREVIATIONS RA = Row Address NOP = No Operation Command *Note : 1. All entries assume that CKE was active(High) during the preceding clock cycle and the current clock cycle. 2. Illegal to bank in specified state ; Function may be legal in the bank indicated by BA, depending on the state of that bank. ...
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... K4G323222M PACKAGE DIMENSIONS (TQFP) #100 #1 0.825 * All Package Dimensions of PQFP & TQFP are same except Height. - PQFP (Height = 3.0mmMAX) - TQFP (Height = 1.2mmMAX) 17.20 0.20 14.00 0.10 23.20 0.20 20.00 0.10 0.30 0.65 0.08 0.13 MAX 1.00 0.10 1.20 MAX * 0.10 MAX 0.05 MIN 0.80 0.20 CMOS SGRAM Dimensions in Millimeters 0.09~0.20 ...