PC87591L-VPCN01 National Semiconductor, PC87591L-VPCN01 Datasheet
PC87591L-VPCN01
Available stocks
Related parts for PC87591L-VPCN01
PC87591L-VPCN01 Summary of contents
Page 1
... BIOS architecture. “PC87591x” refers to all the devices. The PC87591x incorporates National’s CompactRISC CR16B core (a high-performance 16-bit RISC processor), on-chip flash (ROM for the PC87591L) and RAM memories, system support functions and a Bus Interface Unit (BIU) that directly interfaces with optional external memory (such as flash) and I/O devices ...
Page 2
... Mbyte address space Internal Memory — 128 Kbytes of on-chip flash memory (4 Kbytes of ROM in the PC87591L) — Supports BIOS (flash) memory sharing with PC host — On-chip flash is field upgradable by host, CR16B, parallel interface or JTAG — Boot blocks for both CR16B and Host Code — ...
Page 3
Features (Continued) Interrupt Control Unit (ICU) — 31 maskable vectored interrupts (of which 26 are ex- ternal) — General-purpose external interrupt inputs through MIWU — Enable and pending indication for each interrupt — Non-maskable interrupt input Multi-Input Wake-Up (MIWU) — ...
Page 4
Features (Continued) 15 IRQ routing options Legacy free support Real-Time Clock (RTC) — DS1287 and MC146818 compatible — 242-byte battery backed-up CMOS RAM — Calendar including century and automatic leap-year adjustment (Y2K compliant) — Optional adjustment for daylight saving time ...
Page 5
Revision Record Revision Date Status April 11, 00 0.13 December 25, 00 1.0 May 1, 01 1.02 May 8, 01 1.03 July 19, 01 1.04 October 28, 01 1.05 July 2002 1.06 April 2004 1.07 Revision 1.07 Comments External version ...
Page 6
Table of Contents Embedded Controller System Features ................................................................. 2 Host Controlled Functions Features ...................................................................... 3 Clocking, Supply and Package Information ........................................................... 4 Revision Record .................................................................................................... 5 1.0 Introduction 1.1 DOCUMENT ORGANIZATION .................................................................................................. 23 1.2 GENERAL DESCRIPTION ........................................................................................................ 23 1.2.1 System ...
Page 7
Table of Contents (Continued) 2.2.12 Mobile System Wake-Up Control (MSWC) .................................................................. 51 2.2.13 Timers and PWM ......................................................................................................... 51 2.2.14 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) ...................... 51 2.2.15 Internal Pull-Up and Pull-Down Resistors ................................................................... 52 2.3 STRAP PINS ............................................................................................................................. 53 Setting the ...
Page 8
Table of Contents (Continued) Control Signals .................................................................................................... 72 4.1.4 Early Write Bus Cycle .................................................................................................. 72 4.1.5 Late Write Bus Cycle ................................................................................................... 74 4.1.6 Normal Read Bus Cycle .............................................................................................. 76 4.1.7 Fast Read Bus Cycle ................................................................................................... 79 4.1.8 I/O Expansion Bus ...
Page 9
Table of Contents (Continued) Pending Interrupts ............................................................................................... 99 Interrupt Priorities ................................................................................................ 99 Power-Down Modes ............................................................................................ 99 External Interrupt Inputs ...................................................................................... 99 Interrupt Assignment ............................................................................................ 99 4.3.4 ICU Registers ............................................................................................................ 101 ICU Register Map .............................................................................................. 101 Interrupt Vector Register (IVCT) ........................................................................ ...
Page 10
Table of Contents (Continued) 4.5.5 GPIO Port Pw ............................................................................................................ 118 GPIO Port Signals Shared with Development System Signals ......................... 118 4.5.6 GPIO Port Registers .................................................................................................. 119 GPIO Register Map ........................................................................................... 119 Port Alternate Function Registers (PxALT, PyALT and PzALT) ........................ ...
Page 11
Table of Contents (Continued) Timer Interrupt Control Register (TnICTL) ......................................................... 145 Timer Interrupt Clear Register (TnICLR) ........................................................... 146 4.8 PULSE WIDTH MODULATOR (PWM) .................................................................................... 147 4.8.1 Features .................................................................................................................... 147 4.8.2 Functional Description ............................................................................................... 147 4.8.3 Cycle Time and Duty Cycle ...
Page 12
Table of Contents (Continued) Initializing the ADC ............................................................................................ 174 Enabling and Disabling the ADC ....................................................................... 174 Interrupt Structure .............................................................................................. 175 ADC Operating Principles .................................................................................. 175 Reading Measurement Results ......................................................................... 176 Failure Detection ................................................................................................ 177 4.11.6 ADC Registers ........................................................................................................... 177 ADC ...
Page 13
Table of Contents (Continued) DAC Output Protection ...................................................................................... 194 Output Voltage Accuracy ................................................................................... 194 Output Settling Time .......................................................................................... 195 Filtering Noise on Output Signals ...................................................................... 195 4.13 ACCESS.BUS (ACB) INTERFACE ......................................................................................... 196 4.13.1 Features .................................................................................................................... 196 4.13.2 Functional Description ............................................................................................... ...
Page 14
Table of Contents (Continued) 4.16.4 Flash Access and Control .......................................................................................... 224 4.16.5 Parallel Flash Interface .............................................................................................. 226 4.16.6 Flash Protection ......................................................................................................... 226 4.16.7 Flash Interface Registers ........................................................................................... 228 Information Block Access Index Register (IBAI) ................................................ 228 Information Block Data Register ...
Page 15
Table of Contents (Continued) 4.19.3 Debugger Interface Functional Description ............................................................... 249 Rx Data Link ...................................................................................................... 249 TX Data Link ...................................................................................................... 250 Debugger Reset Circuit ..................................................................................... 250 ISE Interrupt Control .......................................................................................... 250 Clock Synchronization ....................................................................................... 251 4.19.4 Flash Interface Functional Description ...
Page 16
Table of Contents (Continued) 4.20.8 CR16B Development Support Registers ................................................................... 275 Debug Configuration Register (DBGCFG) ......................................................... 275 Debug Freeze Enable Register (DBGFRZEN) .................................................. 276 5.0 Host Controller Interface Modules 5.1 KEYBOARD AND MOUSE CONTROLLER INTERFACE ....................................................... 277 5.1.1 Features .................................................................................................................... ...
Page 17
Table of Contents (Continued) 5.3.4 Locking Between Domains ........................................................................................ 300 5.3.5 Host Access Protection ............................................................................................. 301 Response to a Restricted Access ...................................................................... 302 5.3.6 Random Number Generator (PC87591S) ................................................................. 303 5.3.7 Signaling Interface ..................................................................................................... 303 5.3.8 Shared Memory Host Registers ...
Page 18
Table of Contents (Continued) MSWC Control Status Register 1 (MSWCTL1) ................................................. 329 MSWC Control Status Register 2 (MSWCTL2) ................................................. 330 MSWC Control Status Register 3 (MSWCTL3) ................................................. 330 Host Configuration Base Address Low (HCFGBAL) .......................................... 331 Host Configuration Base Address ...
Page 19
Table of Contents (Continued) Shared Memory Base Address High Byte Register ........................................... 351 Shared Memory Base Address Low Byte Register ............................................ 352 Shared Memory Size Configuration Register .................................................... 352 6.1.12 Real Time Clock (RTC) Configuration ....................................................................... 353 Logical Device 16 ...
Page 20
Table of Contents (Continued) 6.2.17 Usage Hints ............................................................................................................... 371 6.2.18 RTC General-Purpose RAM Map .............................................................................. 371 7.0 Device Specifications 7.1 GENERAL DC ELECTRICAL CHARACTERISTICS ............................................................... 372 7.1.1 Recommended Operating Conditions ....................................................................... 372 7.1.2 Absolute Maximum Ratings ....................................................................................... 372 7.1.3 Capacitance ...
Page 21
Table of Contents (Continued) 7.6.11 ICU/Development Timing .......................................................................................... 400 7.6.12 Asynchronous Edge Detected Signals Timing .......................................................... 401 7.6.13 Debugger Interface Timing ........................................................................................ 402 7.6.14 USART Timing ........................................................................................................... 404 7.6.15 LCLK and RESET1-2 ................................................................................................ 406 7.6.16 LPC and SERIRQ Signals ......................................................................................... ...
Page 22
Table of Contents (Continued) Power Management Channel 2 ......................................................................... 422 RTC ................................................................................................................... 422 A.3 CORE DOMAIN REGISTER LAYOUT .................................................................................... 424 A.3.1 Module Configuration ................................................................................................ 424 A.3.2 Bus Interface Unit (BIU) ............................................................................................. 424 A.3.3 DMA Controller .......................................................................................................... 424 A.3.4 General-Purpose I/O ...
Page 23
Introduction 1.1 DOCUMENT ORGANIZATION This document describes the PC87591x architecture and device specifications organized as follows: Chapter 1, Introduction, provides an overview of PC87591x modules, system connections, operating modes and configura- tion. Chapter 2, Signal/Pin Description and ...
Page 24
Introduction (Continued) External Keyboard Interface 32.768 KHz Crystal or Clock RTC Battery Configuration Inputs (Power-Up) Figure 1. PC87591x System Connection Diagram, 128-Pin and 176-Pin Packages www.national.com External Mouse Auxiliary PS/2 Interface 32KOUT/CLKOUT/CLK 32KX1/32KCLKIN 32KX2 V BAT LAD0-3 PC87591x LFRAME ...
Page 25
Introduction (Continued) The Keyboard Controller and the EC functions (core and associated peripherals) are powered long as the system has a power source (e.g., main battery or outlet). Using V and control the system even when ...
Page 26
Introduction (Continued) LPC Serial IRQ I/F Host Controlled Functions LPC Bus I/F Internal Bus KBC + PM Host I/F 32.768 KHz 1.3.1 Processing Unit The CompactRISC CR16B core (referred to in this datasheet as the “core” advanced, ...
Page 27
... See the CompactRISC mation on TMON program integration and specification of requirements. The PC87591L is equipped with a small pre-programed flash, which functions as a boot ROM. The devices are shipped pre- programed and may not be programed in the field. Some devices intended for development purpose may be programed via the JTAG interface ...
Page 28
Introduction (Continued) The ACB Interface is a two-wire serial interface compatible with the ACCESS.bus physical layer also compatible with 2 Intel’s SMBus and Philips’ This module can serve as a bus master or slave and ...
Page 29
... Once this is successfully done, the core may start executing from these parts as well. The External Memory, if available, can also be used to store code and/or data. The PC87591L is shipped with 4 Kbytes of on-chip boot code. The user is expected to use an external memory for most of the code and constant data. ...
Page 30
Introduction (Continued) See Figure 1 on page 24 for a system example in IRE environment. In this environment, the ENV0, ENV1 and TRIS strap pins do not need any external pull-up resistors. 1.4.2 OBD Environment OBD environment is used ...
Page 31
Introduction (Continued) External Keyboard Interface 32.768 KHz Crystal or Clock RTC Battery JTAG I/F to Debugger V CC Configuration Inputs (Power-Up) Figure 3. OBD Environment PC87591x System Connection Diagram, 128-Pin and 176-Pin Packages Revision 1.07 External Mouse Interface 32KOUT/CLKOUT/CLK ...
Page 32
Introduction (Continued) External Keyboard Interface 32.768 KHz Crystal or Clock RTC Battery JTAG I/F to Debugger Off-chip Base Memory (Flash emul. using SRAM) I/O PH Expansion PI Restored PJ Ports Development Support V CC Configuration Inputs ...
Page 33
... BIU Registers 1 DMA Controller Registers1 256 I/O Expansion 1K 1 On-chip Module Registers 64K Base Memory (cont.) Reserved Base Memory 2 Expansion Memory 33 Core Address Domain PC87591L 2M External Expansion Memory 1M External Expansion Memory 4K 0 (End of Core Memory Wrap-Around 2M) Description Environment IRE & OBD - Internal Flash ...
Page 34
... Shared BIOS and Security Registers 16 1 BIU Registers 1 DMA Controller Registers1 256 I/O Expansion 1K 1 On-chip Module Registers 960K Reserved Base Memory 2 Table 3. PC87591L Memory Map Description Size Purpose 4K Base Memory 52K 1 Expansion Memory 2K System RAM 1 Flash Control Registers 11 Shared BIOS and Security Registers ...
Page 35
... BIU Zone 2 configuration registers. In the PC87591L, the base memory is used for storing code and data required for basic boot operations. The rest of the code and data are stored in the Expansion Memory shared by the core firmware and host BIOS. Figure 7 on page 36 illustrates how on-chip and off-chip Base Memory are mapped to the PC87591L address space ...
Page 36
... Figure 8 shows the External Memory Address Range mapping to the core, in the PC87591E and PC87591S devices. Figure 9 shows the External Memory Address Range mapping to the core in the PC87591L device. Note that in PC87591L devices, the External Memory is aliased to low addresses of the core address space, enabling access to memory locations in the flash from both an address in the low memory and an address in the upper part of the memory ...
Page 37
... K 0 Core Address Map Figure 9. Expansion Memory (Zone 0) Address Range - PC87591L External Memory Mapping into Shared BIOS Memory When the shared BIOS memory is enabled using the SHBM strap input (SHBM=1) or the Shared Memory Configuration Registers (LDN=10h), the Expansion Memory address range is mapped into the address range of the host. The PC87591x uses the wrap-around effect of the core address space ( Mbyte boundary) using “ ...
Page 38
Introduction (Continued) The I/O expansion space is mapped to the address space 00 FB00 Addresses in the range 00 FB00 or in their off-chip implementation, while the chip is in DEV environment). Address 00 FBFE is used only in ...
Page 39
... IOPC0 IOPC1/SCL2 170 IOPC2/SDA2 IOPC3/TA1 IOPC4/TB1/EXWINT22 SEL0 SEL1 IOPC5/TA2 175 IOPC6/TB2/EXWINT23 1 5 176-pin Low Profile Plastic Quad Flatpack (LQFP) Order Number PC87591E-VPC / PC87591S-VPC / PC87591L-VPC Revision 1.07 120 115 110 105 125 PC87591x 176-pin LQFP (Top View Package Number VPC176 ...
Page 40
Signal/Pin Description and Configuration IOPE0/AD4 65 IOPE1/AD5 IOPE2/AD6 IOPE3/AD7 DP/AD8 DN/AD9 70 AVCC AGND DA0 DA1 DA2 75 DA3 TINT TCK TDO TDI 80 TMS IOPF0/PSCLK1 IOPF1/PSDAT1 IOPF2/PSCLK2 IOPF3/PSDAT2 85 IOPF4/PSCLK3 IOPF5/PSDAT3 IOPF6/PSCLK4 IOPF7/PSDAT4 GND 90 VCC IOPH0/A0/ENV0 IOPH1/A1/ENV1 ...
Page 41
Signal/Pin Description and Configuration 2.2 BUFFER TYPES AND SIGNAL/PIN DIRECTORY The following sections contain detailed functional descriptions and electrical DC characteristics for the PC87591x signals. The pin multiplexing and function selection criteria are described in Section 2.4 on page ...
Page 42
Signal/Pin Description and Configuration 2.2.1 ACCESS.bus (ACB1 and ACB2) Interface 128-Pin 176-Pin Signal LQFP LQFP SCL2-1 125, 169, 121 163 SDA2-1 126, 170, 122 164 2.2.2 Analog Interface 128-Pin 176-Pin Signal LQFP LQFP AD9-0 70-61 94-93, 90-87, 84-81 76-73 ...
Page 43
Signal/Pin Description and Configuration 2.2.4 Core Bus Interface Unit (BIU) 128-Pin 176-Pin Signal LQFP LQFP A3-0 95-92 127-124 A19-8 N/A 103-104 112-113 120-121 129-130 134-135 142-143 A7-4 99-96 133-131, 128 D7-4, 109- 147-144 D3-0 102 141-138 D15-14, N/A 149-148 ...
Page 44
Signal/Pin Description and Configuration 2.2.5 Development System Support 128-Pin 176-Pin Signal LQFP LQFP BE1-0 N/A 121,129 O BRKL_RSTO N/A 76 BST2-0 N/A 69, 63-62 CBRD N/A 120 PFS N/A 70 PLI N/A 75 TCK 78 106 TDI 80 108 ...
Page 45
Signal/Pin Description and Configuration 2.2.6 General-Purpose I/O (GPIO) and Internal Keyboard Scan 128-Pin 176-Pin Signal LQFP LQFP KBSIN7-0 60-53 80-77, 74-71 KBSOUT15-0 52-37 68-64, 61-56, 53-49 Revision 1.07 (Continued) Buffer Power I/O Type Well I IN /IN V Keyboard ...
Page 46
Signal/Pin Description and Configuration 128-Pin 176-Pin Signal LQFP LQFP IOPA7-0 33-26 43, 40-36, 33-32 IOPD1-0 23-22 29, 26 IOPB7-3 123, 165, 6-5, 6-5, 122-121 164-163 IOPC6-1 2-1, 176-175 172-169 128-125 IOPH3-0 95-92 127-124 IOPI7-0 109-102 147-144 141-138 IOPJ7-2 N/A ...
Page 47
Signal/Pin Description and Configuration 128-Pin 176-Pin Signal LQFP LQFP IOPE7-0 21-20, 25-24, 34, 44 68-65 90-87 Revision 1.07 (Continued) Buffer Power I/O Type Well General-Purpose Input Port. These pins serve input-only ...
Page 48
Signal/Pin Description and Configuration 2.2.7 Host Interface 128-Pin 176-Pin Signal LQFP LQFP CLKRUN 21 25 GA20 5 5 KBRST 6 6 LAD0-3 10-13 15-13, 10 LCLK 16 18 ECSCI 25 31 LDRQ 8 8 LFRAME 9 9 LPCPD 20 ...
Page 49
Signal/Pin Description and Configuration 2.2.8 Interrupt and Wake-Up Inputs (ICU and MIWU) 128-Pin 176-Pin Signal LQFP LQFP EXWINT20 22 26 EXWINT21 23 29 EXWINT22 128 172 EXWINT23 2 176 EXWINT24 24 30 EXWINT40 34 44 EXWINT45 20 24 EXWINT46 ...
Page 50
Signal/Pin Description and Configuration 2.2.10 PS/2 Interface 128-Pin 176-Pin Signal LQFP LQFP PSCLK4-1 88, 86, 118, 84, 82 116, 114, 110 PSDAT4-1 89, 87, 119, 85, 83 117, 115, 111 2.2.11 Strap Configuration 128-Pin 176-Pin Signal LQFP LQFP BADDR1-0 ...
Page 51
Signal/Pin Description and Configuration 2.2.12 Mobile System Wake-Up Control (MSWC) 128-Pin 176-Pin Signal LQFP LQFP RING 123 165 RI1 22 26 RI2 23 29 2.2.13 Timers and PWM 128-Pin 176-Pin Signal LQFP LQFP TA2 1 175 TA1 127 171 ...
Page 52
Signal/Pin Description and Configuration 2.2.15 Internal Pull-Up and Pull-Down Resistors The signals listed in Table 5 can optionally support internal pull-up (PU) and/or pull-down (PD) resistors. See Section 7.3 on page 377 for the values of each resistor type. ...
Page 53
Signal/Pin Description and Configuration 2.3 STRAP PINS During V Power-Up reset, the ENV(0-1), TRIS, SHBM and BADDR strap input signals are sampled. Internal pull-down CC resistors set these signals to 0. These resistors are active only during V nected ...
Page 54
Signal/Pin Description and Configuration Strap Pin Status Register (STRPST) The STRPST register is a byte-wide, read-only register. It enables the software to read the value set to strap pins during Power-Up reset. STRPST bits provide the value of their ...
Page 55
Signal/Pin Description and Configuration Table 8. Alternate Function Selection (Continued) PKG GPIO 128/176 Name Type Module 128/176 IOPB5 I/O GA20 and KBRST 128/176 IOPB6 I/O 128/176 IOPB7 I/O MSWC 128/176 IOPC1 I/O ACCESS.bus 128/176 IOPC2 I/O 128/176 IOPC3 I/O ...
Page 56
Signal/Pin Description and Configuration Table 8. Alternate Function Selection (Continued) PKG GPIO 128/176 Name Type Module 128/176 IOPH0 I/O Core BIU 128/176 IOPH1 I/O 128/176 IOPH2 I/O 128/176 IOPH3 I/O 128/176 IOPH4 I/O 128/176 IOPH5 I/O 128/176 IOPH6 I/O ...
Page 57
Signal/Pin Description and Configuration Table 8. Alternate Function Selection (Continued) PKG GPIO 128/176 Name Type Module 176 IOPK0 I/O Core BIU 176 IOPK1 I/O 176 IOPK2 I/O 176 IOPK3 I/O 176 IOPK4 I/O 176 IOPK5 I/O 176 IOPK6 I/O ...
Page 58
Signal/Pin Description and Configuration 2.4.2 System Configuration Registers For a summary of the abbreviations used for Register Type, see Section 2 on page 34. Register Map Mnemonic MCFG EICFG IOEE1 and IOEE2 Module Configuration Register (MCFG) The MCFG register ...
Page 59
Signal/Pin Description and Configuration Bit 2 EXMEM16 (16-bit-Wide Expansion Memory). Enables the use of the 16-bit-wide Expansion memory, when the ENEMEM is set. The bus width indicated in this register should be the same as the bus width defined ...
Page 60
Signal/Pin Description and Configuration Table 9. GPIO Echo Functions Routing and Echo Enable Bit Assignments Output Port IOPA0 IOPA1 IOPA2 IOPA3 IOPA4 IOPC0 IOPB0 IOPB1 IOPB2 IOPD3 Input to Output Echo Enable Register 1 and 2 (IOEE1 and IOEE2) ...
Page 61
Signal/Pin Description and Configuration The format of IOEE2 is: IOEE2 Location: 00 FF04 16 Type: R/W Bit 7 6 Name Reserved Reset 0 0 Bit 0 EEPB0. 0: Echo Disabled 1: Echo Enabled 1 EEPB1. 0: Echo Disabled 1: ...
Page 62
Power, Reset and Clocks 3.1 POWER 3.1.1 Power Planes The PC87591x has four power planes (wells), as shown in Table 10. Power Plane Powers the LPC interface and host controlled functions (except for RTC and MSWC) and Host Domain ...
Page 63
Power, Reset and Clocks The following table summarizes the power states described in relation with the PC87591x power planes. Table 11. PC87591x Power States and Related Power Planes Power State Battery Fail Power Fail Active and Idle Host Power ...
Page 64
Power, Reset and Clocks Both AV and V should be applied for correct operation; and although the PC87591x is protected against damage if op erated with only one of them (AV CC cause current leakage. Therefore, ADC ...
Page 65
Power, Reset and Clocks Analog Power (3.3V VOUT0 VOUT3 ZL L 10-100 + Analog Ground Plane 3.2 RESET SOURCES AND TYPES The PC87591x has several input reset types: V Power-Up reset (for V supplied ...
Page 66
Power, Reset and Clocks In DEV environment, the PC87591x outputs to the BRKL_RSTO signal an indication that a reset occurred at the core domain. See Section 4.20.3 on page 272 for the implementation and usage of RSTO. The following ...
Page 67
Power, Reset and Clocks During a Warm reset, the PC87591x responds as follows: Terminates core executed instructions Discards results not yet written to memory Eliminates any pending core interrupts and traps Clears the internal latch for the core domain’s ...
Page 68
Power, Reset and Clocks 3.3 CLOCK DOMAINS The PC87591x has three clock domains, as shown in Table 12. Clock Domain Frequency See Section 4.18 Core on page 239 LPC MHz RTC 32 KHz 1. See Section ...
Page 69
Embedded Controller Modules 4.1 BUS INTERFACE UNIT (BIU) The BIU directly interfaces with a wide variety of devices, including ROM, SRAM and flash memory devices and I/O devices. It interfaces via address, data and control buses without the need ...
Page 70
Embedded Controller Modules Number of Bytes Number of Bytes Burst bus cycle, if burstable; otherwise, the core transaction is broken into “basic” bus cycles. On write cycles of a single ...
Page 71
Embedded Controller Modules 4.1.3 Clock Cycles Basic Bus Cycle A basic bus cycle comprises one to three clock cycles (depending on the type of bus cycle). Adding extra wait or hold clock cycles extends the data transfer bus cycles. ...
Page 72
Embedded Controller Modules Burst Read Cycles A read bus cycle consisting of the basic bus cycle plus additional clock cycles called “burst bus cycles”. The burst bus cycles occur if the bus is burstable (BRE in SZCFGn register is ...
Page 73
Embedded Controller Modules WAIT field in SZCFGn reg. 0 Internal waits corresponding to Wait field in SZCFGn register. TIW Data placed on D0-15, SELn: active Internal waits completed HOLD field in SZCFGn reg. T hold Hold cycles completed Note: ...
Page 74
Embedded Controller Modules Bus State CLK A0-19 SELx (x y) SELy (y x) D0-15 RD WR0-1 BST0-2 Figure 13. Early Write Following Normal Read with 0 Wait Bus State CLK A0-19 SELn D0-15 RD WR0-1 BST0-2 Figure 14. Early ...
Page 75
Embedded Controller Modules At the first TIW or T2 (when there are no TIW cycles), the data is placed on the data bus. The bus cycle is completed at T2; at this point, WR0-1 are deactivated. The address and ...
Page 76
Embedded Controller Modules Bus State CLK A0-19 SEL0-1, SELIO D0-15 RD WR0-1 BST0-2 Figure 16. Late Write Bus Cycle Between Normal Read Bus Cycles with 0 Wait Bus State CLK A0-19 SELn D0-15 RD WR0-1 BST0-2 Figure 17. Late ...
Page 77
Embedded Controller Modules When no T cycles are specified, SELn is deactivated in the clock cycle that follows T2, unless another read from the hold same zone follows. The RD signal is always deactivated in the clock cycle following ...
Page 78
Embedded Controller Modules WAIT field in SZCFGn reg. 0 Internal waits corresponding to WAIT field in SZCFGn register. TIW RD: active Internal waits completed In SZCFGn reg.: {BW,WBR,BRE} = 001 Core attempts to read a word In SZCFGn reg.: ...
Page 79
Embedded Controller Modules Bus State CLK A0-19 SELn D0-7 RD WR0-1 BST0-2 Figure 21. Normal Read Bus Cycle with 0 Wait on Burst T1 Bus State CLK A0-19 SELn D0-7 RD WR0-1 BST0-2 Figure 22. Normal Read Bus Cycle ...
Page 80
Embedded Controller Modules The fast read bus cycle cannot be extended by adding wait cycles (WAIT field in SZCFGn register is ignored during this bus cycle). Additionally, hold cycles cannot be added (HOLD field in SZCFGn register is also ...
Page 81
Embedded Controller Modules I/O Expansion Read/Write Bus Cycle These cycles are always preceded Bus State T Idle CLK A0-19 SELIO D0-15 RD WR0-1 BST0-2 Figure 24. I/O Expansion Bus Cycles (EWR bit in BCFG Register = ...
Page 82
Embedded Controller Modules Core Bus Monitoring The core bus monitoring cycle is a non-data transfer bus cycle. It takes a single clock cycle - T1. On this cycle: The address pins display the address of the internal device accessed ...
Page 83
Embedded Controller Modules 4.1.10 BIU Registers For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 34. BIU Register Map Mnemonic BCFG BIU Configuration IOCFG I/O Zone Configuration SZCFGn Static Zone Configuration ...
Page 84
Embedded Controller Modules I/O Zone Configuration Register (IOCFG) The IOCFG register controls the configuration of the I/O zone. On reset initialized to 069F Location: 00 F982 16 Type: R/W Bit Name Reserved Reset 0 ...
Page 85
Embedded Controller Modules Static Zone Configuration Register (SZCFGn) The SZCFGn register (where controls the configuration of zone n. On reset, SZCFGn is initialized to 069F Location: Zone F984 16 Zone ...
Page 86
Embedded Controller Modules Bit 10 IPRE (Idle Before Bus Cycle). Inserts an idle cycle before the current bus cycle when this bus cycle new zone idle cycle inserted 1: Idle cycle inserted 11 FRE ...
Page 87
Embedded Controller Modules 4.2 DMA CONTROLLER (DMAC) The DMAC transfers blocks of data between memory and I/O devices along four independent channels, with minimal inter- vention by the core. The source and destination addresses and the block size to be ...
Page 88
Embedded Controller Modules Channel 0 USART Receive 1 USART Transmit 2 3 4.2.4 Transfer Types The DMAC uses two data transfer modes, direct (fly-by) and indirect (memory-to-memory). The choice of mode depends on the correlation between the source and destination ...
Page 89
Embedded Controller Modules Indirect (Memory-to-Memory) Transfers Bus State CLK DMRQi ADDR DMACKi Figure 28. Indirect Bus Cycle (DIR=0) - External Bus Bus State CLK DMRQi ADDR DMACKi Figure 29. Indirect Bus Cycle (DIR=1) - External Bus In Indirect (Memory-to-Memory) mode, ...
Page 90
Embedded Controller Modules 4.2.5 Bus Policy Intermittent Operation Mode Bus State T1 CLK DMRQi ADDR ADCA DMACKi Figure 30. DMAC Direct Bus Cycles in Intermittent Mode, DMRQ Asserted Constantly. When BPC bit in DMACNTLn is 0, channel ...
Page 91
Embedded Controller Modules 4.2.6 Operation Modes The DMAC operates in three different block transfer modes - single transfer, double buffer and auto-initialize. Select the ap- propriate mode according to the character of the block transfer. Single Transfer Operation This mode ...
Page 92
Embedded Controller Modules Auto-Initialize Operation This mode allows the DMAC to continuously fill the same memory area without software intervention. Initialization 1. Write the two block addresses and byte count into the ADCAn, ADCBn and BLTCn counters, respectively (the BLTCn ...
Page 93
Embedded Controller Modules Device A Address Counter Register (ADCAn) A double-word, read/write register. Holds the current address of either the source data item or the destination location, ac- cording to DIR bit in DMACNTLn register. ADCAn is updated after each ...
Page 94
Embedded Controller Modules Block Length Counter Register (BLTCn) A double-word, read/write register. Holds the current number of DMA transfers to be executed in the current block. BLTCn is decremented by one after each transfer cycle. A DMA transfer may consist ...
Page 95
Embedded Controller Modules Bit 1 ETC (Enable Interrupt on Terminal Count). Enables a level interrupt, when TC bit is set. 0: Interrupt masked 1: Interrupt enabled 2 EOVR (Enable Interrupt on OVR). Enables a level interrupt, when OVR bit is ...
Page 96
Embedded Controller Modules DMA Status Register (DMASTATn) A byte-wide, read with write 1 to clear register that holds the status information for the DMAC channel. On reset, the imple- mented bits are initialized to 0. The reserved bits always return ...
Page 97
Embedded Controller Modules 4.2.9 Usage Hints Do not write to ADCAn, ADCBn or BLTCn and do not change the value of TCS, IND, DIR, OT, ADA, INCA, ADB and INCB fields of DMACNTLn register while the associated channel is active ...
Page 98
Embedded Controller Modules 4.3 INTERRUPT CONTROL UNIT (ICU) The ICU has 31 channels. It interfaces between the different modules’ interrupt requests and external interrupt requests and also generates the core interrupt. It generates both maskable and non-maskable interrupts. The ICU ...
Page 99
Embedded Controller Modules Pending interrupts, enabled or disabled, can be polled using the Status registers. The CR16B core supports INT0, but the ICU reserves INT0 so that it is not connected to any interrupt source. Maskable Interrupt Vectors Interrupt vector ...
Page 100
Embedded Controller Modules Table 16. ICU Interrupt Assignments (Continued) INT Source Number INT8 Internal Level-High INT9 Internal Level-High INT10 Internal Level-High INT11 MIWU Level-High INT12 Internal/MIWU Level-High INT13 Internal/MIWU Edge Rising INT14 External/MIWU Level-High INT15 Reserved INT16 Internal Level-High INT17 ...
Page 101
Embedded Controller Modules 4.3.4 ICU Registers For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 34. ICU Register Map Mnemonic IVCT NMISTAT PFAIL ISTAT0 ISTAT1 IENAM0 IENAM1 IECLR0 IECLR1 Interrupt Vector Register ...
Page 102
Embedded Controller Modules Power Fail Interrupt Control and Status Register (PFAIL) The PFAIL register holds the current value of the PFAIL signal and controls the NMI interrupt generation based on a falling edge of the PFAIL signal. EN and ENLCK ...
Page 103
Embedded Controller Modules Interrupt Status Register 1 (ISTAT1) This register indicates which maskable interrupts are pending regardless of the state of the corresponding IENA bits. Location: 00 FE0C 16 Type: RO Bit Name Reset 0 0 ...
Page 104
Embedded Controller Modules Edge Interrupt Clear Register 0 (IECLR0) The IECLR register is used to clear pending, edge-triggered interrupts. Location: 00 FE12 16 Type: WO Bit Name Bit 0 Reserved. 15-1 IEC15-1 (Edge Interrupt Clear). Each ...
Page 105
Embedded Controller Modules 4.4 MULTI-INPUT WAKE-UP (MIWU) The Multi-Input Wake-Up Unit (MIWU) allows the PC87591x to exit Idle mode. In addition, it provides signal conditioning and grouping of external interrupt sources. It supports a total of 32 internal and/or external ...
Page 106
Embedded Controller Modules Name KBSIN0 KBSIN1 KBSIN2 KBSIN3 KBSIN4 KBSIN5 KBSIN6 KBSIN7 EXWINT40 Reserved Host Access Wake-Up ACCESS.bus 1 Wake-Up ACCESS.bus 2 Wake-Up EXWINT45 EXWINT46 Analog Comparators (ACMI) 1. Program the input to detect the rising edge of the input ...
Page 107
Embedded Controller Modules WUI10 to WUI17 WKEDG1 WKUP Inputs Group 1 (Uses registers WKEDG2, WKPND2 and WKEN2) WUI20 to WUI27 WKUP Inputs Group 3 (Uses registers WKEDG3, WKPND3 and WKEN3) WUI30 to WUI37 WKUP Inputs Group 3 (Uses registers WKEDG4, ...
Page 108
Embedded Controller Modules Pending Flags An occurrence of a trigger condition for the Multi-Input Wake-Up input is latched into the respective pending bit in WKPNDx register. The respective bits of WKPNDx are set on an occurrence of the selected trigger ...
Page 109
Embedded Controller Modules 4.4.3 MIWU Registers For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 34. MIWU Register Map Mnemonic WKEDG1 WKEDG2 WKEDG3 WKEDG4 WKPND1 WKPND2 WKPND3 WKPND4 WKEN1 WKEN2 WKEN3 WKEN4 ...
Page 110
Embedded Controller Modules Edge Detection Register (WKEDG2) Byte-wide read/write register that configures the trigger condition of the input signals WUI20 to WUI27. The functionality of the register is identical to the WKEDG1 register described above. Location: 00 FFC2 16 Type: ...
Page 111
Embedded Controller Modules Pending Register (WKPND4) Byte-wide read/write register that latches the occurrence of a selected trigger condition associated with the input signals WUI40 to WUI47. For a detailed description of the register see the above description of the WKPND1 ...
Page 112
Embedded Controller Modules Pending Clear Register (WKPCL2) Controls the clearing (0) of the pending bits associated with the WUI20 through WUI27 inputs. For a detailed description of the register see, the above description of the WKPCL1 register. Location: 00 FFCE ...
Page 113
Embedded Controller Modules 4.5 GENERAL-PURPOSE I/O (GPIO) PORTS The PC87591x includes four types of General-Purpose I/O (GPIO) ports: Px, Py, Pz and Pw. Px signals: Each signal is bidirectional and can be configured as input or output. An internal weak ...
Page 114
Embedded Controller Modules 4.5.1 Features General-Purpose Input/Output (GPIO) Port (Px). — Each pin functions as input or output signal. — Direction register controls the port direction. — Weak pull-up. — Read-back on all registers. General-Purpose Input (GPI) Port (Py). — ...
Page 115
Embedded Controller Modules Output Buffer The output buffer is a TRI-STATE buffer. The output type (i.e., CMOS or TTL) and its driving capabilities are described in Section 2.2 on page 41. Input Buffer The I/O port input buffer characteristics are ...
Page 116
Embedded Controller Modules Weak Pull-Up Register Alt Device Direction Direction Register To MIWU Data Out Register PIN Data In Register Alt Device Data Input Data In Read Alternative Function Register Figure 34. GPIO Port Px Output with ...
Page 117
Embedded Controller Modules Input Buffer The input buffer characteristics are defined in Section 2.2 on page 41. The input buffer has an enable input. When enabled, the buffer inputs the pin’s logic level to the on-chip modules. When disabled, the ...
Page 118
Embedded Controller Modules Data Output The Data Out (PzDOUT) register holds the data to be driven onto the pin. 4.5.5 GPIO Port Pw GPIO Port Signals Shared with Development System Signals The Pw GPIO port enables access to input and ...
Page 119
Embedded Controller Modules When the signal’s direction is set as output (1), a value forced. When the direction is set for input (0), the signal is in TRI-STATE and is not forced low. 4.5.6 GPIO Port Registers ...
Page 120
Embedded Controller Modules Port Direction Registers (PxDIR and PwDIR) These registers configure the direction of the Px and Pw pins. When cleared (0), each bit in PxDIR or PwDIR defines the corresponding pin as input. When set (1), each pin ...
Page 121
Embedded Controller Modules Port Weak Pull-Up Registers (PxWPU, PyWPU) These registers control the pull-up for the related pin, when it used either as GPIO or in its alternate function. The pull-up is enabled when the corresponding bit of PxWPU or ...
Page 122
Embedded Controller Modules 4.6 PS/2 INTERFACE The PS/2 protocol is an industry-standard, PC-AT-compatible interface for keyboards. It uses a two-wire bidirectional TTL interface for data transmission. Several vendors also supply PS/2 mouse products and other pointing devices that employ the ...
Page 123
Embedded Controller Modules PS/2 I/F Registers Channel 3 Channel 2 Channel 1 RDAT1 WDAT1 RCLK1 CLK1 EN1 EN2 ENSM Quasi-Bidirectional Drivers The quasi-bidirectional drivers have an open-drain output (Q2), an internal pull-up (Q3) and a low-impedance pull-up(Q1). Q2 pulls the ...
Page 124
Embedded Controller Modules EOT bit (PSTAT) EOTIE bit (PSIEN) SOT bit (PSTAT) SOTIE bit (PSIEN) PSCLK1 PSCLK2 PSCLK3 PSCLK4 DSMIE bit (PSIEN) Power Modes The PS/2 interface is active only when the PC87591x is in Active mode. The shift mechanism ...
Page 125
Embedded Controller Modules 4.6.4 Operating With the Shift Mechanism Enabled The shift mechanism is designed to off load the bit level handling of the data transfer from the firmware to a hardware scheme; this improves system tolerance to interrupt latency. ...
Page 126
Embedded Controller Modules Shift Status The PSTAT register indicates the current status of the shift mechanism. The data transfer process may be in one of the following three states: Shifter Empty: The shift mechanism is in Receive Inactive, Receive Idle, ...
Page 127
Embedded Controller Modules 1st CLK CLK DATA Start Bit End of Receive When the stop-bit is detected, the shift mechanism enters the “End-Of-Reception” state. In this state, the shift mechanism: Disables all the clock signals by forcing them low Sets ...
Page 128
Embedded Controller Modules I/O Inhibit CLK DATA Start Bit After each of the next seven falling edges of the clock line, one more data bit (bits 1 through 7) is driven on the data line of the active channel (either ...
Page 129
Embedded Controller Modules PS/2 Register Map Mnemonic PSDAT PSTAT PSCON PSOSIG PSISIG PSIEN PS/2 Data Register (PSDAT) The PSDAT register is a byte-wide read/write register. In Receive mode, PSDAT holds the data received in the last message from the PS/2 ...
Page 130
Embedded Controller Modules Bit 5-3 ACH (Active Channel). Defines which of the PS/2 channels is currently active (i.e., a start bit was detected). In case more than one channel become active simultaneously, only the one with the highest priority (lowest ...
Page 131
Embedded Controller Modules Bit 6-4 IDB (Input Debounce). Defines the number of PC87591x clock cycles during which the clock input is expected to be stable before the shift mechanism identifies its new value. This protects the shift mechanism from false ...
Page 132
Embedded Controller Modules Bit 3 CLK1 (Enable Channel 1) 0: Forces the PSCLK1 pin low (0) and disables channel 0 of the shift mechanism. 1: Depends on whether or not the shift mechanism is enabled. When the shift mechanism is ...
Page 133
Embedded Controller Modules PS/2 Interrupt Enable Register (PSIEN) The PSIEN register is an 8-bit read/write register. It enables/disables the various interrupts generated by the PS/2 module. Bits in PSIEN register may be cleared to 0 only when interrupts are disabled ...
Page 134
Embedded Controller Modules 4.7 MULTI-FUNCTION 16-BIT TIMER (MFT16) The PC87591x includes two Multi-Function Timer (MFT) modules. The registers of each module are prefixed with Tn and the signals are suffixed with an n (where n is the module’s number, i.e., ...
Page 135
Embedded Controller Modules 4.7.2 Clock Source Unit The clock source unit, as shown in Figure 45, contains two clock selectors for each counter and a 5-bit clock pre-scaler. Pre-Scaler The 5-bit clock pre-scaler consists of a pre-scaler register and a ...
Page 136
Embedded Controller Modules Pre-Scaler Output TBn Counter Clock Counter Clock Source Select The clock source unit contains two clock source selectors that allow the clock source to be selected independently for each of the two 16-bit counters from one of ...
Page 137
Embedded Controller Modules Figure 47 shows a block diagram of the timer operating in mode 1. In PWM mode, counter 1, TnCNT1, functions as the time base for the PWM timer. Counter 1 counts down at the clock rate selected ...
Page 138
Embedded Controller Modules In this case, the current value of the counter is transferred to the corresponding capture register; following this, the counter is preset to FFFF . Using this approach enables an external signal’s on-time, off-time or period to ...
Page 139
Embedded Controller Modules Timer/counter 1 (TnCNT1) counts down at the rate of the selected clock (see “Counter Clock Source Select” on page 136 for additional details). On underflow, TnCNT1 is reloaded from TnCRA register and counting proceeds. If enabled, the ...
Page 140
Embedded Controller Modules Note that TnCNT2 can not operate in the Pulse Accumulate or External Event Counter modes since TBn input is used as a capture input. Selecting either Pulse Accumulate mode or External Event Counter mode for TnCNT2 causes ...
Page 141
Embedded Controller Modules 4.7.5 Timer I/O Functions There are two I/O pins associated with each of the MFT16 modules: TAn and TBn, where n denotes the module on a given device. The functionality of TA and TB depends on the ...
Page 142
Embedded Controller Modules 4.7.7 MFT16 Registers For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 34. MFT16 Register Map Mnemonic TnPRSC TnCKC TnCNT1 TnCNT2 TnCRA TnCRB TnCTRL TnICTL TnICLR Timer/Counter Register 1 ...
Page 143
Embedded Controller Modules Timer/Counter Register 2 (TnCNT2) The TnCNT2 register is a word-wide read/write register that is not altered by reset. The power-up value is unknown. Location: MFT16 1: 00 FD86 16 MFT16 2: 00 FDA6 16 Type: R/W Bit ...
Page 144
Embedded Controller Modules Bit 5-3 C2CSEL (Counter 2 Clock Select). Defines the clock mode for timer/counter 2. Bits Description Clock (Counter 1 stopped Prescaled system clock External ...
Page 145
Embedded Controller Modules Bit 6 TAOUT (TAn Output Data). Contains the value of TAn output when TAn is used as a PWM output. 0: TAn is low 1: TAn is high This bit is set and cleared by hardware and ...
Page 146
Embedded Controller Modules Timer Interrupt Clear Register (TnICLR) The TnICLR register is a byte-wide write-only register. It controls the clear of pending flags TAPND, TBPND, TCPND and TDPND, which are located in TnICTRL register. Location: MFT16 1: 00 FD90 16 ...
Page 147
Embedded Controller Modules 4.8 PULSE WIDTH MODULATOR (PWM) The PWM module generates eight 8-bit PWM outputs; each may have a different duty cycle. A common 8-bit clock pre-scaler and an 8-bit down-counter determine the cycle time, the minimal possible pulse ...
Page 148
Embedded Controller Modules 4.8.3 Cycle Time and Duty Cycle Calculation The PWM module supports duty cycles in the range 100%. The PWMi output signal cycle time is: (PRSC + 1) x (CTR + CLK ...
Page 149
Embedded Controller Modules Cycle Time Register (CTR) The CTR register controls the cycle time and duty cycle steps, CTR is set (FF Location: 00 FD02 16 Type: R/W Bit 7 6 Name Reset 1 1 Bit 7-0 Cycle Time Value. ...
Page 150
Embedded Controller Modules PWM Polarity Register (PWMPOL) This register controls the polarity of PWM0 to PWM7. The register is cleared (00 Location: 00 FD04 16 Type: R/W Bit 7 6 Name Reset 0 0 Bit 7-0 Inverse PWM Outputs. Each ...
Page 151
Embedded Controller Modules 4.9 UNIVERSAL SYNCHRONOUS/ASYNCHRONOUS RECEIVER-TRANSMITTER (USART) The USART is a full-duplex synchronous/asynchronous receiver-transmitter that supports a wide range of software program- mable baud rates and data formats. It handles automatic parity generation and several error detection schemes. DMA ...
Page 152
Embedded Controller Modules Control and Error Detection Parity Generator/Checker Each functional unit is described briefly in this section. Transmitter The Transmitter consists of an 8-bit transmit shift register and an 8-bit transmit buffer. Data is loaded in parallel from the ...
Page 153
Embedded Controller Modules 4.9.3 Operation The USART has two basic modes of operation; Synchronous and Asynchronous. In addition, two special Synchronous and Asynchronous modes, attention and diagnostic, are available. This section describes the operating modes of the USART. Asynchronous Mode ...
Page 154
Embedded Controller Modules USCLK UTXD URXD Figure 54. USART Synchronous Communication In Synchronous mode, Transmit Shift register (TSFT) and Transmit Buffer register (UTBUF) double buffer data for transmis- sion. To transmit a character, a data byte is loaded into TBUF ...
Page 155
Embedded Controller Modules START 1 BIT START 1a BIT START 1b BIT START 1c BIT The format shown in Figure 56 consists of one start bit, eight data bits (excluding parity) and one or two stop bits. If parity bit ...
Page 156
Embedded Controller Modules Pre-Scaler Select 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 A pre-scaler factor of zero corresponds to NO CLOCK. The NO CLOCK condition is the USART Power-Down mode. In ...
Page 157
Embedded Controller Modules Figure 58 shows a diagram of the interrupt sources and associated enable bits. FE DOE PE The interrupts can be individually enabled or disabled using Enable Transmit Interrupt (ETI), Enable Receive Interrupt (ERI) and Enable Receive Error ...
Page 158
Embedded Controller Modules 4.9.4 USART Registers For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 34. USART Register Map Mnemonic URBUF UTBUF UPSR UBAUD UFRS UMDSL USTAT UICTRL Receive Data Buffer Register ...
Page 159
Embedded Controller Modules Frame Select Register (UFRS) This byte-wide read/write register controls the selection of the frame format, including number of data bits, number of stop bits and parity. The register is cleared (00 Location: 00 FD28 16 Type: R/W ...
Page 160
Embedded Controller Modules Mode Select Register (UMDSL) This byte-wide read/write register controls the selection of the clock source, Synchronous mode, Attention mode and line break generation. It contains the enable bits for the DMA channels. The register is cleared (00 ...
Page 161
Embedded Controller Modules Status Register (USTAT) This byte-wide, read-only register contains the receive and transmit status bits. The register is cleared (00 Location: 00 FD26 16 Type: RO Bit 7 6 Name Reserved XMIP Reset 0 0 Bit 0 PE. ...
Page 162
Embedded Controller Modules Interrupt Control Register (UICTRL) This byte-wide register contains the interrupt enable bits and the interrupt status flags. The register is set to 01 Location: 00 FD24 16 Type: Varies per bit Bit 7 6 Name EEI ERI ...
Page 163
Embedded Controller Modules The baud rate register is programed with a baud rate divisor baud rate divisor +1). This produces a baud clock of (5x10 )/(16x5x6.5) = 9615.385 % error = (9615.385-9600)/9600 = ...
Page 164
Embedded Controller Modules 4.10 TIMER AND WATCHDOG (TWD) The Timer and WATCHDOG module (TWD) generates the clocks and interrupts used for timing periodic functions in the system. It also provides WATCHDOG protection over software execution. The TWD provides flexibility in ...
Page 165
Embedded Controller Modules Pre-Scale A pre-scale counter divides the input clock (32.768 KHz factor of 2 through 5 (i.e., divide ratio of 1:1 through 1:32). The pre-scaled output is used as an input clock for a 16-bit timer ...
Page 166
Embedded Controller Modules 4.10.3 TWD Registers For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 34. TWD Register Map Mnemonic TWCFG Timer and WATCHDOG Configuration Register TWCP Timer and WATCHDOG Clock Pre-Scaler ...
Page 167
Embedded Controller Modules Bit 5 WDSDME. Selects the WATCHDOG touch mechanism 0: Disables the WATCHDOG service using WDSDM register. In this case, the WATCHDOG should be serviced by writing a value to WDCNT register. When this bit is cleared, write ...
Page 168
Embedded Controller Modules TWDT0 Control and Status Register (T0CSR) The T0CSR register is a read/write register. It controls the operation and provides the status of the T0 timer. The non-re- served bits of T0CSR are cleared (0) on reset. Location: ...
Page 169
Embedded Controller Modules 4.10.4 Usage Hints The TWD protects WATCHDOG operation from software tampering. To achieve the highest level of protection, proceed as follows: 1. Program the TWDT0 pre-scale and TMWT0 timers to the desired values. 2. Configure the WATCHDOG ...
Page 170
Embedded Controller Modules 4.11 ANALOG TO DIGITAL CONVERTER (ADC) The Analog to Digital Converter (ADC) monitors various voltages and temperatures in the system and reports their values to the core. The ADC can measure external voltage inputs ...
Page 171
Embedded Controller Modules Temperature Sensor Interface (TSI). The TSI generates the diode current and converts the voltage drop to a single-ended voltage. In addition, the TSI of the remote diode enables open/short detection for the diode connection cable and sets ...
Page 172
Embedded Controller Modules AD0 AD9 VDD VCC AVCC VBAT Remote Diode DP Sensor DN Interface Temp Sensor Interface Local Diode Analog Power 3.3V AVCC AGND www.national.com (Continued) AI0 AI1 AI2 AI3 AI4 AI5 AI6 AI7 AI8 AI9 16:1 AI10 Analog ...
Page 173
Embedded Controller Modules 4.11.3 Voltage Measurement The ADC performs a linear conversion of the input voltage signal to a 10-bit, unsigned digital representation. The input signal should be applied relative to the AGND pin and should range from 0V to ...
Page 174
Embedded Controller Modules To change the diode selection for a new measurement, the input is switched between inputs at different voltage levels. The temperature input interface circuits of the ADC require a settling time to reach the new voltage value ...
Page 175
Embedded Controller Modules In this state, all ADC activities are halted and ADC current consumption from the AV ADC causes an activation delay recommended to disable the ADC only after the buffer registers of all four channels have ...
Page 176
Embedded Controller Modules See Section 7.4 on page 378 for the values page 173 for t calculation. VC Temperature inputs from remote and local diodes are measured by alternating the remote and local diodes in each succes- ...
Page 177
Embedded Controller Modules An interrupt is expected from EOCEV when using the sequence listed in the EOCEV-driven ADC operation sequence (see above). The EOCEV interrupt indicates that all four channels contain valid data and may be read. Interrupts from the ...
Page 178
Embedded Controller Modules ADC Status Register (ADCSTS) This register indicates the global status of the ADC module. ADCSTS is cleared (00 resets, bit 2 is unchanged and other bits are cleared. Location: 00 FF20 16 Type: Varies per bit Bit ...
Page 179
Embedded Controller Modules ADC Configuration Register (ADCCNF) This register controls the operation and global configuration of the ADC module. ADCCNF is cleared (00 Location: 00 FF22 16 Type: R/W Bit 7 6 Name Reserved Reset 0 0 Bit 0 ADCEN ...
Page 180
Embedded Controller Modules ADC Delay Control Register (ADLYCTL) This register controls the delay between “input switching” and “conversion start” for the voltage and temperature channels. ADLYCTL is set reset. 16 Location: 00 FF26 16 Type: R/W Bit ...
Page 181
Embedded Controller Modules Local Diode Overtemperature Limit Register (TLOCOTL) This register holds the limit value used for overtemperature detection. TLOCOTL is set to 7F Location: 00 FF28 16 Type: R/W Bit 7 6 Name Reset 0 1 Bit 7-0 OTSLIM ...
Page 182
Embedded Controller Modules Temperature Channel Control Register (TCHANCTL) This register both controls the operation and indicates the status of the Temperature channel. TCHANCTL is set to 10 reset. Location: 00 FF30 16 Type: Varies per bit Bit 7 6 Name ...
Page 183
Embedded Controller Modules Voltage Channel 1 Control Register (VCHN1CTL) This register both controls the operation and indicates the status of Voltage Channel 1. VCHN1CTL is set to 1F Location: 00 FF34 16 Type: Varies per bit Bit 7 6 Name ...
Page 184
Embedded Controller Modules Voltage Channel 1 Data Buffer (VCHN1DAT) This register (buffer) holds the data measured by Voltage Channel 1. Location: 00 FF36 16 Type: RO Bit Name Reserved Bit 9-0 VCHDAT (Voltage Channel 1 Data). Selected ...
Page 185
Embedded Controller Modules Voltage Channel 3 Control Register (VCHN3CTL) This register controls the operation and indicates the status of Voltage Channel 3. VCHN3CTL is set to 1F Location: 00 FF3C 16 Type: Varies per bit Bit 7 6 Name DATVAL ...
Page 186
Embedded Controller Modules For positive input voltages higher than V The divider should be calculated so that its output is lower than the full-scale value (V voltage. For negative input voltages, a resistive level-shifter should be used in front of ...
Page 187
... Thermal mass can seriously degrade the temperature sensor’s effective accuracy. The use of smaller packages for remote sensors, such as SOT23s, improves the situation. Table 25. Remote Sensor Transistor Manufacturers National Semiconductor (USA) Filtering the Noise on Temperature Input Signals Noise may be coupled to the input signal for various reasons, including close proximity to digital circuits. The ADC conver- sion technology has good noise rejection especially for low-frequency signals, such as power supply hum ...
Page 188
Embedded Controller Modules Q1 2N3904 Calculating the Temperature Channel Delay The delay time is the period between diode selection and the A/D conversion start. Due to the switched diode current, this delay should be long enough to guarantee the voltage ...
Page 189
Embedded Controller Modules 10 mil 10 mil Twisted Pair and Shielded Cables For remote sensor distances longer than 8 inches or in particularly noisy environments, a twisted pair cable is recommended. Its practical length is 6 feet to 12 feet ...
Page 190
Embedded Controller Modules 4.12 DIGITAL TO ANALOG CONVERTER (DAC) The DAC converts digital input values to analog signals. The DAC support four channels for handling up to four independent conversions in parallel. 4.12.1 Features 8-bit resolution Independent 4-channel D/A converter ...
Page 191
Embedded Controller Modules Voltage Ratio to AV Figure 66. Channel Data to Output Voltage Ratio Conversion When the value of DACDATA7 DACDATn register the respective output has an output signal of (255/256) 16 Figure 66: ...
Page 192
Embedded Controller Modules PC87591x 4.12.4 Operation Initializing the DAC The PC87591x wakes up after power-up with all the D/A channels disabled (DACEN0-3 bits in DACCTRL register are cleared to 0). In this state, all DAC activities are halted, and its ...
Page 193
Embedded Controller Modules All DAC channels are automatically disabled when entering Idle mode if ENIDLE bit in DACCTRL register is cleared to 0. This happens regardless of the state of DACENn (n bit in DACCTRL register. In this ...
Page 194
Embedded Controller Modules DAC Data Channel 0-3 Registers (DACDAT0-3) These registers hold the data to be loaded into Channels 0-3 of the DAC. These registers are not affected by reset or disable of the respective channel. Location: Channel 0 - ...
Page 195
Embedded Controller Modules Output Settling Time The DAC output settling time depends on the external load characteristics and the required accuracy. Figure 68 shows the equivalent circuit used for evaluating DAC behavior. Each DAC output has a typical output impedance ...
Page 196
Embedded Controller Modules 4.13 ACCESS.BUS (ACB) INTERFACE The PC87591x includes two ACCESS.bus interface modules. The registers of each module are prefixed with ACBn, where ‘n’ is module number The signal names are suffixed with ‘n’. Each ACCESS.bus ...
Page 197
Embedded Controller Modules At each clock cycle, the slave can stall the master while it handles the previous data or prepares new data. The slave does this, for each bit transferred byte boundary, by holding SCLn low ...
Page 198
Embedded Controller Modules Transmitter Data Output Receiver Data Output SCLn S Start Condition “Acknowledge After Every Byte” Rule The master generates an Acknowledge clock pulse after each byte transfer. The receiver sends an Acknowledge signal after every byte is received. ...
Page 199
Embedded Controller Modules Arbitration on the Bus Multiple master devices on the bus require arbitration between their conflicting bus access demands. Control of the bus is initially determined according to address bits and clock cycle. If more than one master ...
Page 200
Embedded Controller Modules Master Transmit After becoming the bus master, the device can start transmitting data on the ACCESS.bus. To transmit a byte, the software should: 1. Check that BER and NEGACK bits in ACBnST register are cleared and SDAST ...