BT8960EPF Conexant Systems, Inc., BT8960EPF Datasheet
BT8960EPF
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BT8960EPF Summary of contents
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Bt8960 Single-Chip 2B1Q Transceiver The Bt8960 is a full-duplex 2B1Q transceiver based on Rockwell’s HDSL technol- ogy. It supports Nx64 kbps transmission of more than 18,000 feet over 26 AWG copper telephone wire without repeaters. Small size and low power ...
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... Ordering Information Order Number Bt8960EPF 100-Pin Plastic Quad Flat Pack (PQFP) Copyright © 1997 Rockwell Semiconductor Systems, Inc. All rights reserved. Print date: December 1997 Rockwell Semiconductor Systems, Inc. reserves the right to make changes to its products or specifications to improve performance, reliability, or manufacturability. Information furnished is believed to be accurate and reliable. However, no responsibility is assumed for its use ...
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Table of Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 2.2.4 Echo Canceler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Bt8960 Single-Chip 2B1Q Transceiver 3.2.10 0x09—Nonlinear Echo Canceller Modes Register (nonlinear_ec_modes 3.2.11 0x0A—Decision Feedback Equalizer Modes Register (dfe_modes 3.2.12 0x0B—Transmitter Modes Register (transmitter_modes) ...
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Table of Contents 3.2.49 0x46, 0x47—Signal Level Meter Register (slm_low, slm_high 3.2.50 0x48, 0x49—Far-End Level Meter Register (felm_low, felm_high ...
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Bt8960 Single-Chip 2B1Q Transceiver List of Figures Figure 1-1. 2B1Q Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures viii Single-Chip 2B1Q Transceiver N8960DSB Bt8960 ...
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Bt8960 Single-Chip 2B1Q Transceiver List of Tables Table 1-1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables x Single-Chip 2B1Q Transceiver N8960DSB Bt8960 ...
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System Overview 1.1 Functional Summary The Bt8960 2B1Q transceiver is an integral component of Rockwell's telecom- munications product line. The major building blocks of a 2B1Q terminal are shown in Figure 1-1. Figure 1-1. 2B1Q Terminal Receive Data Framer/ ...
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System Overview 1.1 Functional Summary The Bt8960 comprises five major functions: a transmit section, a receive sec- tion, a timing recovery and clock interface, a microcomputer interface, and a test and diagnostic interface. Figure 1-2 details the connections within ...
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Bt8960 Single-Chip 2B1Q Transceiver 1.1.1 Transmit Section The source of transmitted symbols is programmable through the microcomputer interface. The primary choices include external 2B1Q-encoded data presented to the TQ[1,0]/TDAT pins of the channel unit interface, internally looped-back receive symbols from ...
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System Overview 1.1 Functional Summary 1.1.4 Microcomputer Interface The Microcomputer Interface (MCI) provides access to a 256-byte address space within the transceiver. A combination of direct and indirect addressing methods are used to access all internal locations. The MCI ...
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Bt8960 Single-Chip 2B1Q Transceiver 1.2 Applications 1.2.1 Voice/Data Pairgain A well-established market exists for voice pairgain systems. These systems trans- port several simultaneous phone conversations over a single twisted pair. They are used by telecommunications service providers to maximize the ...
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System Overview 1.2 Applications Figure 1-3. PCM6 Voice Pairgain Block Diagram SLIC SLIC SLIC SLIC SLIC SLIC 1.2.2 Internet Connectivity Transport The growth of the Internet has created a tremendous demand for additional band- width in the local loop. ...
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Bt8960 Single-Chip 2B1Q Transceiver 1.2.3 ISDN Basic Rate Interface Concentrator Since many telecommunications service providers are positioning BRI service as residential Internet or telecommuter connectivity, the lack of installed copper pairs into the residence could be a serious limitation to ...
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System Overview 1.3 Pin Descriptions 1.3 Pin Descriptions The Bt8960 is packaged in a 100-Pin Plastic Quad Flat Pack (PQFP). The pin assignments are shown in Figure 1-4. A listing of pin labels, numbers, and I/O assignments is given ...
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Bt8960 Single-Chip 2B1Q Transceiver Table 1-1. Pin Descriptions Pin Pin Label I/O Pin 1 VDD1 – RD/ WR/R ALE IRQ READY OD ...
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System Overview 1.3 Pin Descriptions Table 1-2. Hardware Signal Definitions ( Pin Label Signal Name MOTEL Motorola/Intel ALE Address Latch Enable CS Chip Select RD/DS Read/Data Strobe WR / R/W Write/ Read/Write AD[7:0] Address- Data[7:0] ADDR[7:0] Address ...
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Bt8960 Single-Chip 2B1Q Transceiver Table 1-2. Hardware Signal Definitions ( Pin Label Signal Name RQ[1]/ Receive Quat 1/ RDAT Receive Data RQ[0]/ BCLK Receive Quat 0/ Bit Clock TQ[1]/ TDAT Transmit Quat 1/ Transmit Data TQ[0] Transmit Quat ...
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System Overview 1.3 Pin Descriptions Table 1-2. Hardware Signal Definitions ( Pin Label Signal Name TXP, TXN Transmit Positive, Negative TXLDIP, Transmit Line TXLDIN Driver In Positive, Negative TXPSP, Transmit Pulse- TXPSN Shaping Filter Positive, Negative RXP, ...
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Bt8960 Single-Chip 2B1Q Transceiver Table 1-2. Hardware Signal Definitions ( Pin Label Signal Name TDI JTAG Test Data Input TMS JTAG Test Mode Select TDO JTAG Test Data Output TCK JTAG Test Clock Input SMON Serial Monitor DTEST[1:4] ...
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System Overview 1.3 Pin Descriptions 14 Single-Chip 2B1Q Transceiver N8960DSB Bt8960 ...
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Functional Description 2.1 Transmit Section The transmit section is illustrated in Figure 2-1. It comprises four major func- tions: a symbol source selector/scrambler, a variable gain digital-to-analog con- verter (DAC), a pulse-shaping filter, and a line driver. Figure 2-1. ...
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Functional Description 2.1 Transmit Section 2.1.1 Symbol Source Selector/Scrambler The input source selector/scrambler can be configured through the Transmitter Modes Register [transmitter_modes; 0x0B] data_source [2:0] bits to select the source of the data to be transmitted and determine whether ...
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Bt8960 Single-Chip 2B1Q Transceiver The bit stream is converted into symbols for the four-level cases as shown in Table 2-2. Table 2-2. Four-Level Bit-to-Symbol Conversions In two-level mode, the magnitude bit is forced to a zero. This forces the sym- ...
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Functional Description 2.1 Transmit Section 2.1.2 Variable Gain Digital-to-Analog Converter A four-level Digital-to-Analog Converter (DAC) is integrated into the Bt8960 to accurately convert the output of the symbol source to analog form. The normal- ized values of these four ...
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Bt8960 Single-Chip 2B1Q Transceiver 2.2 Receive Section Like the transmit section, the receive section consists of both analog and digital circuitry. The VGA provides the interface to the analog signals received from the line and the hybrid. The Analog-to-Digital Converter ...
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Functional Description 2.2 Receive Section 2.2.2 Analog-to-Digital Converter The ADC provides 16 bits of resolution. The analog input from the variable gain amplifier is converted into digital data and output at the symbol rate. 2.2.3 Digital Signal Processor The ...
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Bt8960 Single-Chip 2B1Q Transceiver 2.2.3.1 Digital Prior to the main signal processing, the input signal must be adjusted for any DC Front-End offset. The front-end module also monitors the input signal level, which includes measuring DC and AC input signal ...
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Functional Description 2.2 Receive Section 2.2.3.2 Offset A nonzero DC level on the input can be corrected offset value Adjustment [dc_offset_low, dc_offset_high; 0x26, 0x27] which is subtracted from the input. The DC offset is a 16-bit ...
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Bt8960 Single-Chip 2B1Q Transceiver 2.2.4 Echo Canceler The EC removes images of the transmitted symbols from the received signal and consists of two blocks: a linear and nonlinear echo canceler. The organization of the blocks is displayed in Figure 2-3. ...
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Functional Description 2.2 Receive Section 2.2.5.2 Feed Forward The Feed Forward Equalizer (FFE) removes precursors from the received signal. Equalizer (FFE) The FFE may be operated in a special adapt last mode. In this mode, which is useful during ...
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Bt8960 Single-Chip 2B1Q Transceiver 2.2.6.2 Peak Detector The PKD is only used during the two-level transmission part of startup. It oper- (PKD) ates on the echo-free signal. A signal is detected + higher than ...
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Functional Description 2.2 Receive Section The LFSR operates in the same way in both cases, except in the two-level case it is clocked once-per-symbol and in the four-level case it is clocked twice-per- symbol. When operating as a scrambler, ...
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Bt8960 Single-Chip 2B1Q Transceiver The SNR alarm provides a rapid indication of impulse noise disturbances and loss of signal so that corrective action can be taken. The alarm is based on a sec- ond noise level meter. The meter is ...
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Functional Description 2.3 Timing Recovery and Clock Interface 2.3 Timing Recovery and Clock Interface The timing recovery and clock interface block diagram consists of the timing recovery circuit and the crystal amplifier, as detailed in Figure 2-5. The main ...
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Bt8960 Single-Chip 2B1Q Transceiver 2.3.0.7 Timing The timing recovery circuit uses the Bt8960’s internal detected symbol and equal- Recovery Circuit izer error signals to regenerate the received data symbol clock (QCLK). The HCLK output is synchronized with the edges of ...
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Functional Description 2.4 Channel Unit Interface 2.4 Channel Unit Interface The quaternary signals of the channel unit interface have four modes which are programmable through bits 0 and 1 of the Channel Unit Interface Modes Register [cu_interface_modes; 0x06]. They ...
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Bt8960 Single-Chip 2B1Q Transceiver Parallel slave mode uses RBCLK and TBCLK inputs to synchronize data transfer. RBCLK and TBCLK must be frequency-locked to QCLK, though the use of two internal FIFOs allow an arbitrary phase relationship to QCLK. TQ[1] and ...
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Functional Description 2.5 Microcomputer Interface 2.5 Microcomputer Interface The microcomputer interface provides operational mode control and status through internal registers. A microcomputer write sets the operating modes to the appropriate registers. A read to a register verifies the operating ...
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Bt8960 Single-Chip 2B1Q Transceiver 2.5.2.1 RAM Access The internal RAMs of the transmit filter, LEC, NEC, DFE, equalizer, and micro- Registers code are accessed indirectly. They all share a common data register which is used for both read and write ...
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Functional Description 2.5 Microcomputer Interface 2.5.4 Reset The reset input (RST active-low input that places the transceiver in an inac- tive state by setting the mode bit (0) in the Global Modes and Status Register [global_modes; 0x00]. ...
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Bt8960 Single-Chip 2B1Q Transceiver A prescaler may precede the timer. This increases the time span available at the expense of resolution. Only the startup timers have prescalers. Table 2-7 pro- vides summary information on the timers. Table 2-7. Timers General ...
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Functional Description 2.6 Test and Diagnostic Interface (JTAG) 2.6 Test and Diagnostic Interface (JTAG) As the complexity of communications chips increases, the need to easily access individual chips for PCB verification is becoming vital result, special cir- ...
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Registers 3.1 Conventions Unless otherwise noted, the following conventions apply to all applicable register descriptions: • For storage of multiple-bit data fields within a single byte-wide register, the Least Significant Bits (LSBs) of the field are located at the ...
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Register Summary Table 3-1. Register Table ( ADDR Register Read (hex) Label Write hw_revision[ 0x00 global_modes R/W 0x01 serial_monitor_source R/W hclk_freq[1] 0x02 mask_low_reg R/W 0x03 mask_high_reg R/W 0x04 timer_source R/W 0x05 irq_source R/W 0x06 cu_interface_modes R/W 0x07 ...
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Table 3-1. Register Table ( ADDR Register Read (hex) Label Write 0x0F reserved2 R/W D[7] 0x10 sut1_low R/W D[7] 0x11 sut1_high R/W D[15] 0x12 sut2_low R/W D[7] 0x13 sut2_high R/W D[15] 0x14 sut3_low R/W D[7] 0x15 sut3_high R/W ...
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Table 3-1. Register Table ( ADDR Register Read (hex) Label Write 0x23 reserved10 R/W D[7] 0x24 pll_phase_offset_low R/W D[7] 0x25 pll_phase_offset_high R/W D[15] 0x26 dc_offset_low R/W D[7] 0x27 dc_offset_high R/W D[15] 0x28 tx_calibrate R/W 0x29 tx_gain R/W 0x2A ...
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Table 3-1. Register Table ( ADDR Register Read (hex) Label Write 0x38 dagc_target_low R/W D[7] 0x39 dagc_target_high R/W D[15] enable_peak_ 0x3A detector_modes R/W detector 0x3B peak_detector_delay R/W 0x3C dagc_modes R/W 0x3D ffe_modes R/W 0x3E ep_modes R/W 0x40 pdm_low ...
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Table 3-1. Register Table ( ADDR Register Read (hex) Label Write 0x4C ber_meter_low R/W D[7] 0x4D ber_meter_high R/W D[15] 0x4E symbol_histogram R/W D[7] 0x50 nlm_low R/W D[23] 0x51 nlm_high R/W D[31] 0x5E pll_frequency_low R/W D[22] 0x5F pll_frequency_high R/W ...
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Table 3-1. Register Table ( ADDR Register Read (hex) Label Write 0x7A eq_microcode_add_read R/W 0x7B eq_microcode_add_write R/W 0x7C access_data_byte0 R/W D[7] 0x7D access_data_byte1 R/W D[15] 0x7E access_data_byte2 R/W D[23] 0x7F access_data_byte3 R/W D[31 — ...
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Registers 3.1 Conventions 3.2.1 0x00—Global Modes and Status Register (global_modes hw_revision[3] hw_revision[2] hw_revision[1] Chip Revision Number—Read-only unsigned binary field encoded with the chip revision hw_revision[3:0] number. Smaller values represent earlier versions while larger values represent later versions. ...
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Bt8960 Single-Chip 2B1Q Transceiver Serial Monitor Source Select—Read/write binary field selects the Serial Monitor (SMON) out- smon[5:0] put source. smon[5:0] Decimal 0 – 0000 – 10 1111 3.2.3 0x02—Interrupt Mask Register Low ...
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Registers 3.1 Conventions 3.2.4 0x03—Interrupt Mask Register High (mask_high_reg) Independent read/write mask bits for each of the IRQ Source Register [irq_source; 0x05] interrupt flags. Indi- vidual mask bit behavior is identical to that specified for Interrupt Mask Register Low ...
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Bt8960 Single-Chip 2B1Q Transceiver 3.2.6 0x05—IRQ Source Register (irq_source) Independent read/write (zero only) interrupt flags, one for each of four internal sources. Each flag bit is set and stays set when its corresponding source indicates that a valid interrupt condition ...
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Registers 3.1 Conventions Interface mode Mode [1:0] 00 Parallel Master —Parallel quat transfer synchronized to QCLK out. 01 Parallel Slave—Parallel quat transfer synchronized to separate TBCLK and RBCLK inputs. 10 Serial, Magnitude First. Serial quat transfer synchronized to BCLK ...
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Bt8960 Single-Chip 2B1Q Transceiver Zero Output—Read/write control bit which, when set, zeros the echo replica before subtrac- zero_output tion from the input signal. Achieves the affect of disabling or bypassing the echo cancellation function. Does not disable coefficient adaptation. When ...
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Registers 3.1 Conventions 3.2.11 0x0A—Decision Feedback Equalizer Modes Register (dfe_modes – – Adapt Coefficients—Read/write control bit which enables coefficient adaptation when set; dis- adapt_coefficents ables/freezes adaptation when cleared. Coefficient values are preserved when adaptation is dis- abled. ...
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Bt8960 Single-Chip 2B1Q Transceiver data_source [2:0] 000 001 010 011 100 101 110 111 Transmitter Mode Isolated pulse. Level selected by isolated_pulse[1:0]. The meter timer must be enabled and in the continuous mode. The pulse repetition interval is determined by ...
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Registers 3.1 Conventions 3.2.13 0x0C—Timer Restart Register (timer_restart) Independent read/write restart bits, one for each of the eight internal timers. Setting an individual bit causes the associated timer to be reloaded with the contents of its interval register. For ...
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Bt8960 Single-Chip 2B1Q Transceiver 3.2.15 0x0E—Timer Continuous Mode Register (timer_continuous) Independent read/write mode bits, one for each of the eight internal timers. When any individual bit is set, the corresponding timer is placed in the continuous count mode. While in ...
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Registers 3.1 Conventions 3.2.22 0x20—Test Register (reserved9) A 1-byte read/write register used for device testing by Rockwell. This register is automatically initialized to 0x00 upon RST assertion and initial power application. This register must be initialized according to the ...
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Bt8960 Single-Chip 2B1Q Transceiver 3.2.26 0x21—ADC Control Register (adc_control – – loop_back[1] Loopback Control—Read/write binary field specifying if loopback is enabled, and the type of loop_back[1,0] loopback that is enabled. During transmitting loopback, the differential receiver inputs ...
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Registers 3.1 Conventions 3.2.27 0x22—PLL Modes Register (pll_modes clk_freq[1] clk_freq[0] negate_symbol Clock Frequency Select—Read/write binary field specifies one of four data rate ranges for clk_freq[1,0] Bt8960 operation. The 00 state is automatically selected by RST assertion and ...
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Bt8960 Single-Chip 2B1Q Transceiver 3.2.28 0x23—Test Register (reserved10) A 3-byte read/write register used for device testing by Rockwell. This register is automatically initialized to 0x000000 upon RST assertion and initial power application. This register must be initialized according to the ...
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Registers 3.1 Conventions 3.2.32 0x29—Transmitter Gain Register (tx_gain – – tx_gain[3] Transmit Gain—A 4-bit, 2’s-complement, read/write field controlling the transmitter gain. tx_gain[3:0] Upon initialization, the value in the Transmitter Calibration Register [tx_calibrate; 0x28] may be written into ...
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Bt8960 Single-Chip 2B1Q Transceiver 3.2.33 0x2A, 0x2B—Noise-Level Histogram Threshold Register (noise_histogram_th_low, noise_histogram_th_high) Two-byte read/write register interpreted as a 16-bit, 2’s-complement number. The range of meaningful values is limited to positive integers between 0x0000 and 0x7FFF. The value of this register ...
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Registers 3.1 Conventions 3.2.38 0x34, 0x35—SNR Alarm Threshold Register (snr_alarm_th_low, snr_alarm_th_high) A 2-byte read/write register interpreted as a 16-bit, 2’s-complement number. The range of meaningful values is limited to positive integers between 0x0000 and 0x7FFF. The value of this ...
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Bt8960 Single-Chip 2B1Q Transceiver 3.2.41 0x3A—Symbol Detector Modes Register (detector_modes enable_peak_det output_mux_con output_mux_con ector trol[1] trol[0] enable_peak_ Enable Peak Detector—Read/write control bit that enables the peak detection function when detector set; disables the function when cleared. When ...
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Registers 3.1 Conventions not be cleared while lfsr_lock remains high.) After 128 cycles, if the threshold is not exceeded, the accumulator is cleared, the scrambler/descrambler re-enters the descrambler mode for another 23 cycles, and the process repeats until either ...
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Bt8960 Single-Chip 2B1Q Transceiver 3.2.44 0x3D—Feed Forward Equalizer Modes Register (ffe_modes – – – Adapt Last Coefficient—Read/write control bit enables adaptation of the last (oldest) coeffi- adapt_last_coeff cient only when set; allows all coefficient adaptation when cleared. ...
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Registers 3.1 Conventions 3.2.46 0x40, 0x41—Phase Detector Meter Register (pdm_low, pdm_high) A 2-byte read-only register containing the 16 MSBs of the 26-bit, 2’s-complement phase detector meter accu- mulator. This meter sums the output of the timing recovery module’s phase ...
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Bt8960 Single-Chip 2B1Q Transceiver 3.2.49 0x46, 0x47—Signal Level Meter Register (slm_low, slm_high) A 2-byte read-only register containing 16 MSBs of the 32-bit unsigned signal-level meter accumulator. This meter sums the absolute value of the receive signal input path—after format conversion ...
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Registers 3.1 Conventions 3.2.52 0x4C, 0x4D—Bit Error Rate Meter Register (ber_meter_low, ber_meter_high) A 2-byte read-only register containing all 16 bits of the unsigned bit-error-rate meter accumulator. This meter counts the number of error-free bits recovered by the detector during ...
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Bt8960 Single-Chip 2B1Q Transceiver 3.2.55 0x5E, 0x5F— PLL Frequency Register (pll_frequency_low, pll_frequency_high) A 2-byte read/write register comprising the 16 MSBs of the 31-bit, 2’s-complement timing recovery loop com- pensation filter accumulator. Treated much like a meter register, the frequency register ...
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Registers 3.1 Conventions 3.2.59 0x73—NEC Write Tap Select Register (nonlinear_ec_tap_select_write) A 6-bit read/write register representing an unsigned binary address defined over a range decimals. When written, it causes the lowest-order 14 bits of the Access ...
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Bt8960 Single-Chip 2B1Q Transceiver 3.2.63 0x77—Scratch Pad Write Tap Select (sp_tap_select_write) A 6-bit read/write register representing an unsigned binary address defined over a range decimals. When written, it causes the lowest-order 8 bits of the Access ...
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Registers 3.1 Conventions 3.2.65 0x79—Equalizer Write Select Register (eq_add_write) A 6-bit read/write register representing an unsigned binary address defined over a range decimals. When written, it causes the lowest-order 16 bits of the Access Data ...
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Electrical & Mechanical Specifications 4.1 Absolute Maximum Ratings Stresses above those listed may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those listed ...
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Electrical & Mechanical Specifications 4.2 Recommended Operating Conditions 4.2 Recommended Operating Conditions Table 4-2. Recommended Operating Conditions Symbol V Digital Core-Logic Supply Voltage DD1 V Digital I/O-Buffer Supply Voltage DD2 V Analog Supply Voltage AA V High-Level Input Voltage ...
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Bt8960 Single-Chip 2B1Q Transceiver 4.3 Electrical Characteristics Typical characteristics measured at nominal operating conditions: T mum characteristics guaranteed over extreme operating conditions: min T Table 4-3. Electrical Characteristics Symbol Parameter V High-Level Output Voltage @ Low-Level Output ...
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Electrical & Mechanical Specifications 4.4 Clock Timing 4.4 Clock Timing Table 4-4. External Clock Timing Requirements (MCLK) Symbol Parameter 1 MCLK Period (T ) (1) MCLK 2 MCLK Pulse-Width Low 3 MCLK Pulse-Width High Note: (1 external ...
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Bt8960 Single-Chip 2B1Q Transceiver Table 4-6. Symbol Clock (QCLK) Switching Characteristics Symbol 9 QCLK Period (T ) (1) QCLK 10 QCLK Pulse-Width High 11 QCLK Pulse-Width Low 12 QCLK Hold after HCLK Rising Edge 13 QCLK Delay after HCLK High ...
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Electrical & Mechanical Specifications 4.5 Channel Unit Interface Timing 4.5 Channel Unit Interface Timing Table 4-7. Channel Unit Interface Timing Requirements, Parallel Master Mode Symbol 14 TQ[1,0] Setup prior to QCLK Falling Edge 15 TQ[1,0] Hold after QCLK Low ...
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Bt8960 Single-Chip 2B1Q Transceiver Table 4-9. Channel Unit Interface Timing Requirements, Parallel Slave Mode Symbol 18 (1) TBCLK, RBCLK Period 19 TBCLK RBCLK Pulse-Width High , 20 TBCLK RBCLK Pulse-Width Low , 21 TQ[1,0] Setup prior to TBCLK Active Edge ...
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Electrical & Mechanical Specifications 4.5 Channel Unit Interface Timing Table 4-11. Channel Unit Interface Timing Requirements, Serial Mode Symbol 25 TDAT Setup prior to BCLK Falling Edge 26 TDAT Hold after BCLK Low Table 4-12. Channel Unit Interface Switching ...
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Bt8960 Single-Chip 2B1Q Transceiver 4.6 Microcomputer Interface Timing Table 4-13. Microcomputer Interface Timing Requirements Symbol Parameter 34 ALE Pulse-Width High 35 Address Setup prior to ALE Falling Edge 36 (1) Address Hold after ALE Low 37 ALE low prior to ...
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Electrical & Mechanical Specifications 4.6 Microcomputer Interface Timing Table 4-14. Microcomputer Interface Switching Characteristics Symbol 49 Data Out Enable (Low Z) after Read Strobe Falling Edge 50 Data Out Valid after Read Strobe Low 51 Data Out Hold after ...
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Bt8960 Single-Chip 2B1Q Transceiver Figure 4-6. MCI Write Timing, Intel Mode (MOTEL = 0) AD[7:0] Address or ADDR[7:0] 35 Write Strobe 34 ALE READY Figure 4-7. MCI Write Timing, Motorola Mode (MOTEL = 1) Address AD[7:0] or ADDR[7:0] 35 Write ...
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Electrical & Mechanical Specifications 4.6 Microcomputer Interface Timing Figure 4-8. MCI Read Timing, Intel Mode (MOTEL = 0) AD[7:0] Address or ADDR[7:0] 35 Read Strobe 34 ALE READY Figure 4-9. MCI Read Timing, Motorola Mode (MOTEL = 1) AD[7:0] ...
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Bt8960 Single-Chip 2B1Q Transceiver Figure 4-10. Internal Write Timing Write Strobe IRQ Internal Register Internal RAM Access Data Register 4.0 Electrical & Mechanical Specifications 4.6 Microcomputer Interface Timing N8960DSB 83 ...
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Electrical & Mechanical Specifications 4.6 Microcomputer Interface Timing 4.6.1 Test and Diagnostic Interface Timing Table 4-15. Test and Diagnostic Interface Timing Requirements Symbol 56 TCK Pulse-Width High 57 TCK Pulse-Width Low 58 TMS, TDI Setup prior to TCK Rising ...
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Bt8960 Single-Chip 2B1Q Transceiver Figure 4-11. JTAG Interface Timing TDO 62 TCK 58 TDI TMS Figure 4-12. SMON Timing HCLK 64 SMON 4.0 Electrical & Mechanical Specifications N8960DSB 4.6 Microcomputer Interface Timing 63 85 ...
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Electrical & Mechanical Specifications 4.6 Microcomputer Interface Timing 4.6.2 Analog Specifications Table 4-17. Receiver Analog Requirements and Specifications Parameter Input Signals RXP, RXN, RXBP, and RXBN Input Voltage Range Balanced Differential Input Resistance MHz Common Mode ...
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Bt8960 Single-Chip 2B1Q Transceiver Table 4-18. Transmitter Analog Requirements and Specifications Parameter Transmit Symbol Rate (f ) QCLK Frequency (Data Rate/2) qclk (1, 2,3) See Figure 4-13, R Pulse Template (1, 2, 2xF Average Power setting Gain Adjustment ...
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Electrical & Mechanical Specifications 4.6 Microcomputer Interface Timing Figure 4-13. Transmitted Pulse Template –0. 0.93 1.25T –0.01 –1.2T –0.6T 0.5T Table 4-19. Transmitted Pulse Template ...
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Bt8960 Single-Chip 2B1Q Transceiver 4.6.3 Test Conditions Figure 4-14. Transmitter Test Circuit 1 k TXPSP (67 TXPSN (68) 16.2 16.2 Note: See Table 4-20 for C8 and transformer values. 4.0 Electrical & Mechanical Specifications 1 k TXLDIP (69) ...
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Electrical & Mechanical Specifications 4.6 Microcomputer Interface Timing Table 4-20. Transmitter Test Circuit Component Values L (Primary Inductance - Line Side) Figure 4-15. Standard Output Load (Totem Pole and Three-State Outputs) Figure 4-16. Open-Drain Output Load (IRQ) 90 Component ...
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Bt8960 Single-Chip 2B1Q Transceiver 4.7 Timing Measurements The input waveforms are shown in Figure 4-17. Output waveforms are displayed in Figures 4-18 and 4-19. Figure 4-17. Input Waveforms for Timing Tests 3 V Input high Figure 4-18. Output Waveforms for ...
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Electrical & Mechanical Specifications 4.8 Mechanical Specifications Figure 4-19. Output Waveforms for Three-state Enable and Disable Tests 1.5 V Output Disabled 4.8 Mechanical Specifications 92 V 1 Output Output Disabled Enabled N8960DSB Bt8960 Single-Chip 2B1Q ...
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Bt8960 Single-Chip 2B1Q Transceiver Figure 4-20. 100-Pin Plastic Quad Flat Pack 4.0 Electrical & Mechanical Specifications N8960DSB 4.8 Mechanical Specifications 93 ...
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