BT848AKPF Conexant Systems, Inc., BT848AKPF Datasheet
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BT848AKPF
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BT848AKPF Summary of contents
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Advance Information This document contains information on a product under development. The parametric information contains target parameters that are subject to change. Bt848/848A/849A Single-Chip Video Capture for PCI Bt848 is a complete, low NTSC/PAL/SECAM video capture on the PCI bus. ...
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... Ordering Information Model Number Bt848KPF 160-pin PQFP Bt848AKPF 160-pin PQFP Bt849AKPF 160-pin PQFP Copyright © 1997 Brooktree Corporation. All rights reserved. Print date: February 1997 Brooktree reserves the right to make changes to its products or specifications to improve performance, reliability, or manufacturability. Information furnished by Brooktree Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Brooktree Corporation for its use ...
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T ABLE OF C ONTENTS List Of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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T C ABLE OF ONTENTS Video Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Bt848/848A/849A Single-Chip Video Capture for PCI PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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T C ABLE OF ONTENTS Horizontal Scaling Register, Lower Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Control Register Digital Video In Support (Bt848A/849A Only) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . ...
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IST F IGURES List Of Figures Figure 1. Bt848/848A/849A Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Figure 35. The Relationship between SCL and SDA ...
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L T IST OF ABLES List of Tables Table 1. PCI Video Decoder Product Family . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Video Capture Over PCI Bus Supports Intel Intercast™ Brooktree ® F UNCTIONAL D ESCRIPTION Functional Overview The Bt848/848A/849A integrates an NTSC/PAL/SECAM composite & S-Video decoder, scaler, DMA controller, and PCI Bus master on a single device. Bt848/848A/849A can place video ...
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F D UNCTIONAL ESCRIPTION Functional Overview Table 1. PCI Video Decoder Product Family Composite, S-Video multi-standard Video Decoder and PCI bus master Peaking, single crystal operation, digital camera support WST (Teletext) decoding support Bt848A Analog Video and The Bt848A provides ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Figure 1. Bt848/848A/849A Detailed Block Diagram Brooktree ® L848A_A F D UNCTIONAL ESCRIPTION Functional Overview 3 ...
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F D UNCTIONAL ESCRIPTION Functional Overview Figure 2. Bt848 Video Decoder and Scaler Block Diagram YREF+ YIN YREF– CLEVEL CREF+ CIN CREF– Notes: (1). Bt848 only. (2). Bt848A and Bt849A only. PCI Bus Interface Bt848/848A/849A is designed to efficiently utilize ...
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Bt848/848A/849A Single-Chip Video Capture for PCI UltraLock The Bt848/848A/849A employs a proprietary technique known as UltraLock to lock to the incoming analog video signal. It will always generate the required num- ber of pixels per line from an analog source ...
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F D UNCTIONAL ESCRIPTION Functional Overview Vertical Blanking Interval Bt848/848A/849A provides a complete solution for capturing and decoding Verti- Data Capture cal Blanking Interval (VBI) data. The Bt848/848A/849A can operate in a VBI Line Output Mode, in which the VBI ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Pin Descriptions Table 2 provides a description of pin functions, grouped by common function, Table list of pin names in pin-number order, and Figure 3 shows the pinout diagram. Pins with ...
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F D UNCTIONAL ESCRIPTION Pin Descriptions Table 2. Pin Descriptions Grouped by Pin Function ( Pin # Pin Name I/O Signal 51 PAR I/O Parity 42 FRAME I/O Cycle Frame 43 IRDY I/O Initiator Ready 44 TRDY I/O ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Table 2. Pin Descriptions Grouped by Pin Function ( Pin # Pin Name I/O Signal 82–89, GPIO[23:0] I/O General Purpose 92–99, I/O 110–117 GPIO[23] O Clkx1 GPIO[22] O Field GPIO[21] O Vactive ...
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F D UNCTIONAL ESCRIPTION Pin Descriptions Table 2. Pin Descriptions Grouped by Pin Function ( Pin # Pin Name I/O Signal 133 REFOUT O REFOUT O 137 YREF+ I 150 YREF– I 151 CREF+ I 157 CREF– I ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Table 2. Pin Descriptions Grouped by Pin Function ( Pin # Pin Name I/O Signal 104 NUMXTAL I 3 TCK I 5 TMS I 7 TDI I 6 TDO O 2 TRST ...
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F D UNCTIONAL ESCRIPTION Pin Descriptions Table 2. Pin Descriptions Grouped by Pin Function ( Pin # Pin Name I/O Signal 90, 109, VDDG +5V P 123 12, 19, GND G 26, 34, 41, 48, 57, 64, 71, ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Pin Assignments Figure 3. Bt848/848A/849A Pinout Diagram 1 VDD TRST 2 TCK 3 PVREF 4 TMS 5 TDO 6 TDI 7 INTA 8 RST 9 VDDP 10 CLK 11 GND 12 GNT 13 REQ ...
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F D UNCTIONAL ESCRIPTION Pin Assignments Table 3. Bt848 Pin List Pin Pin Pin Pin # Name # Name 1 VDD 33 VDDP 2 TRST 34 GND 3 TCK 35 AD[19] 4 PVREF 36 AD[18] 5 TMS 37 AD[17] 6 ...
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Bt848/848A/849A Single-Chip Video Capture for PCI UltraLock The Challenge The line length (the interval between the midpoints of the falling edges of succeed- ing horizontal sync pulses) of analog video sources is not constant. For a stable source such as ...
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F D UNCTIONAL ESCRIPTION UltraLock decoded for square pixel NTSC output. The first line is shorter than the nominal NTSC line time interval of 63 this first line, a line time of 63.2 s sampled at 4*Fsc (14.32 ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Composite Video Input Formats Bt848 supports several composite video input formats. Table 4 shows the different video formats and some of the countries in which each format is used. Table 4. Video Input Formats ...
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F D UNCTIONAL ESCRIPTION Composite Video Input Formats Table 5. Register Values for Video Input Formats Register Bit NTSC-M IFORM XTSEL 01 (0x01) [4:3] FORMAT 001 [2:0] Cropping: [7:0] in all Set to desired HDELAY, five cropping VDELAY, registers values ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Y/C Separation and Chroma Demodulation Y/C separation and chroma decoding are handled as shown in Figure 5. Bandpass and notch filters are implemented to separate the composite video stream. The fil- ter responses are ...
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F D UNCTIONAL ESCRIPTION Y/C Separation and Chroma Demodulation Figure 6. Y/C Separation Filter Responses Luma Notch Filter Frequency Responses for NTSC and PAL/SECAM NTSC Figure 7. Filtering and Scaling Horizontal Scaler – 1 – Luminance = ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Video Scaling, Cropping, and Temporal Decimation The Bt848 provides three mechanisms to reduce the amount of video pixel data in its output stream; down-scaling, cropping, and temporal decimation. All three can be controlled independently. ...
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F D UNCTIONAL ESCRIPTION Video Scaling, Cropping, and Temporal Decimation Figure 8. Optional Horizontal Luma Low-Pass Filter Responses QCIF ICON Figure 9. Combined Luma Notch, 2x Oversampling and Optional Low-Pass Filter Response (NTSC) QCIF ICON CIF Figure 10. Combined Luma ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Figure 11. Frequency Responses for the Four Optional Vertical Luma Low-Pass Filters Figure 12. Combined Luma Notch and 2x Oversampling Filter Response Brooktree ® Video Scaling, Cropping, and Temporal Decimation 2-tap 3-tap 4-tap 5-tap ...
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F D UNCTIONAL ESCRIPTION Video Scaling, Cropping, and Temporal Decimation Peaking (Bt848A and The Bt848A enables four different peaking levels by programming the PEAK bit Bt849A Only) and HFILT bits in the SCLOOP register. The filters are shown in Figures ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Figure 14. Luma Peaking Filters with 2x Oversampling Filter and Luma Notch (Bt848A/849A only) Enhanced Resolution of Passband HFILT = 10 HFILT = 11 Brooktree ® Video Scaling, Cropping, and Temporal Decimation HFILT = ...
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F D UNCTIONAL ESCRIPTION Video Scaling, Cropping, and Temporal Decimation Chrominance Scaling A 2-tap, 32-phase interpolation filter is used for horizontal scaling of chrominance. Vertical scaling of chrominance is implemented through chrominance comb filter- ing using a line store, followed ...
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Bt848/848A/849A Single-Chip Video Capture for PCI tical scaling ratio. It defines the number of vertical lines output by the Bt848. The following formula should be used to determine the value to be entered into this 13-bit register. The loaded value ...
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F D UNCTIONAL ESCRIPTION Video Scaling, Cropping, and Temporal Decimation to use a single field as opposed to using both fields. Using a single field will ensure there are no inter-field motion artifacts on the scaled output. When performing sin- ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Figure 15. Effect of the Cropping and Active Registers Video frame Horizontally Inactive Video frame Horizontally Inactive HRESET Brooktree ® Video Scaling, Cropping, and Temporal Decimation Cropped image Horizontally Active Cropped image scaled to ...
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F D UNCTIONAL ESCRIPTION Video Scaling, Cropping, and Temporal Decimation Cropping Registers The Horizontal Delay Register (HDELAY) is programmed with the delay be- tween the falling edge of HRESET and the rising edge of ACTIVE. The count is programmed with ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Figure 16. Regions of the Video Signal tween the rising edge of VRESET and the start of active video lines. It determines how many lines to skip before initiating the ACTIVE signal ...
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F D UNCTIONAL ESCRIPTION Video Scaling, Cropping, and Temporal Decimation When changing the programming in the temporal decimation register, 0x00 should be loaded first, and then the decimation value. This will ensure that the decimation counter is reset to zero. ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Video Adjustments The Bt848 provides programmable hue, contrast, saturation, and brightness. The Hue Adjust Register The Hue Adjust Register is used to offset the hue of the decoded signal. In NTSC, (HUE) the hue ...
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F D UNCTIONAL ESCRIPTION Low Color Detection and Removal Low Color Detection and Removal If a color-burst of 25 percent (NTSC percent (PAL/SECAM) or less of the nominal amplitude is detected for 127 consecutive scan lines, the color-difference ...
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Bt848/848A/849A Single-Chip Video Capture for PCI VBI Data Output Interface A frame of video is composed of 525 lines for NSTC and 625 for PAL/SECAM. Figure 18 illustrates an NTSC video frame, in which there are a number of distinct ...
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F D UNCTIONAL ESCRIPTION VBI Data Output Interface abled for the even field and CAPTURE_ODD register bit is enabled for the odd field. The VBI data is sampled at a rate of 8*Fsc and is stored in the FIFO as ...
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Bt848/848A/849A Single-Chip Video Capture for PCI region and includes all the horizontal blank/sync information in the data stream. The data is vertically bound beginning at the first line during VACTIVE and ending after a fixed number of packets. The data ...
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F D UNCTIONAL ESCRIPTION Video Data Format Conversion Video Data Format Conversion Pixel Data Path The video decoder/scaler portion of the Bt848 generates a video data stream in packed 4:2:2 YCrCb format. The video data is then color space converted ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Figure 21. Video Data Format Converter From Bt848 Video Decoder/Scaler 4:4:4 Up-sample Chroma Packed 4:2:2 Packed 4:2:2 Packed 4:2:2 Packed to Planar Conversion Internal Control Signals from Bt848 Video Decoder Brooktree ® RGB Gamma ...
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F D UNCTIONAL ESCRIPTION Video Data Format Conversion Table 7. Color Formats Format DWORD dw0 RGB32 (1) dw0 RGB24 dw1 dw2 dw0 RGB16 dw0 RGB15 dw0 YUY2—YCrCb 4:2:2 (2) dw1 dw0 BtYUV—YCrCb 4:1:1 dw1 dw2 dw0 Y8 (Gray Scale) dw0 ...
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Bt848/848A/849A Single-Chip Video Capture for PCI YCrCb to RGB The 4:2:2 YCrCb data stream from the video decoder portion of the Bt848 must be Conversion converted to 4:4:4 YCrCb before the RGB conversion occurs, using an interpola- tion filter on ...
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F D UNCTIONAL ESCRIPTION Video Data Format Conversion Byte Swapping Before the data enters the FIFO it passes through a 4-way mux to allow swapping of the bytes to support Macintosh (big endian) color data formats. The pixel DWORD PD[31:0] ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Video and Control Data FIFO The FIFO block accepts data from the video data format conversion process, buff- ers the data in FIFO memory, then outputs DWORDs to the DMA Controller to be burst ...
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F D UNCTIONAL ESCRIPTION Video and Control Data FIFO FIFO Data Interface Loading data into the FIFO can begin only when valid pixels are present during the even or the odd field. The pixel DWORD PD[31:0] is stored in FI[31:0], ...
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Bt848/848A/849A Single-Chip Video Capture for PCI VDFC has no responsibility for FIFO overruns. The DMA Controller will be able to resynchronize to data streams that are shorter or longer than expected. same time if a bus access latency persists across ...
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F D UNCTIONAL ESCRIPTION Video and Control Data FIFO Table 10. Table of PCI Bus Access Latencies Video Format Resolution NTSC 30 fps 640 x 480 NTSC 30 fps 320 x 240 PAL/SECAM 25 fps 768 x 576 PAL/SECAM 25 ...
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Bt848/848A/849A Single-Chip Video Capture for PCI DMA Controller The Bt848 incorporates a unique DMA controller architecture which gives the capture system great flexibility in its ability to deliver data to memory archi- tected as a small RISC engine ...
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F D UNCTIONAL ESCRIPTION DMA Controller Figure 23. RISC Block Diagram FIFO Read Signals FIFO Status RISC Bits Decoder Number of Bytes From Available FIFO in FIFO FIFO Output [31:0] RISC Program Start Address Target Memory The Bt848’s FIFO DWORDs ...
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Bt848/848A/849A Single-Chip Video Capture for PCI RISC Program Setup and There are two independent sets of RISC instructions in the host memory, one for Synchronization the odd field and the other for the even field. The first field begins with ...
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F D UNCTIONAL ESCRIPTION DMA Controller Table 11. RISC Instructions ( Instruction Opcode DWORDs WRITE 0001 2 WRITE123 1001 5 50 Description Write packed mode pixels to memory from the FIFO beginning at the specified target address. DWORD0: ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Table 11. RISC Instructions ( Instruction Opcode DWORDs WRITE1S23 1011 3 WRITEC 0101 1 Brooktree ® Description Write pixels to memory in planar mode from the FIFO1 beginning at the speci- fied ...
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F D UNCTIONAL ESCRIPTION DMA Controller Table 11. RISC Instructions ( Instruction Opcode DWORDs SKIP 0010 1 SKIP123 1010 2 52 Description Skip pixels by discarding byte count # of bytes from the FIFO. This may start and ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Table 11. RISC Instructions ( Instruction Opcode DWORDs JUMP 0111 2 SYNC 1000 2 Brooktree ® Description Jump the RISC program counter to the jump address. This allows uncondi- tional branching of ...
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F D UNCTIONAL ESCRIPTION DMA Controller relay information such as the opcode, target address, status codes, synchronization codes, byte count/enables, and start/end of line codes. struction is the first instruction of the scan line. The EOL bit in the WRITE ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Complex Clipping It is necessary to be able to clip the video image before it is put onto the PCI bus when writing video data directly into on-screen display memory. The Bt848 sup- ports ...
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F D UNCTIONAL ESCRIPTION DMA Controller Executing Instructions Once the DMA controller has achieved synchronization between the FIFO and the RISC program, it proceeds with executing the RISC instructions. The data in the FIFO will be aligned with the data ...
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Bt848/848A/849A Single-Chip Video Capture for PCI have some headroom in the FIFO to allow for more data to enter, while the PCI ini- tiator is waiting for the target to respond. Hence, the Bt848 monitors the FIFO Al- most Full ...
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F D UNCTIONAL ESCRIPTION DMA Controller FIFO Data Stream The Bt848 DMA controller is constantly monitoring whether there is a mismatch Resynchronization between the amount of data expected by the RISC instruction and the amount of data being provided by ...
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Analog Signal Selection Multiplexer Considerations Autodetection of NTSC or PAL/SECAM Video Brooktree ® E LECTRICAL I NTERFACES Input Interface The Bt848 contains an on-chip 3:1 mux while the Bt848A/849A includes an on-chip 4:1 mux. This mux can be used to ...
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E I LECTRICAL NTERFACES Input Interface Flash A/D Converters The Bt848 uses two on-chip flash A/D converters to digitize the video signals. YREF+, CREF+ and YREF–, CREF– are the respective top and bottom of the in- ternal resistor ladders. connected ...
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Bt848/848A/849A Single-Chip Video Capture for PCI fundamental cut crystals or third overtone mode crystals, parallel resonant. If sin- gle-ended oscillators are used they must be connected to XT0I and XT1I. The clock source options and circuit requirements are shown in ...
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E I LECTRICAL NTERFACES Input Interface Figure 25. Typical External Circuitry VAA 2 K REFOUT Not Required YREF+ on Bt848A/849A CREF+ 0 CLEVEL 30 K 0.1 F YREF– CREF– 0.1 F MUX0 75 75 Termination 0.1 F ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Figure 26. Clock Options 28.63636 MHz 0.1 F 2.7 H NTSC Third Overtone Mode Crystal Oscillator Osc 28.63636 MHz NTSC Single-ended Oscillator 28.63636 MHz ...
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E I LECTRICAL NTERFACES Input Interface Single Crystal Operation The Bt848A/849A includes an internal phase locked loop that may be used to de- (Bt848A/849A Only) code NTSC and PAL using only a single crystal. When using the PLL, a 28.636363 ...
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Bt848/848A/849A Single-Chip Video Capture for PCI 2X Oversampling and Digitized video needs to be bandlimited in order to avoid aliasing artifacts. Be- Input Filtering cause the Bt848 samples the video data at 8xFsc (over twice the normal rate), no filtering ...
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E I LECTRICAL NTERFACES PCI Bus Interface PCI Bus Interface The PCI local bus is an architectural, timing, electrical, and physical interface that allows the Bt848 to interface to the local bus of a host CPU. Bt848 is fully com- ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Figure 28. PCI Block Diagram FIFO Data FIFO Control Signals PCI Config. Registers Local Registers Video Decoder Interrupts Brooktree ® DMA PCI Controller Initiator Master GPIO Interrupts L848A_A E I LECTRICAL ...
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E I LECTRICAL NTERFACES General Purpose I/O Port General Purpose I/O Port The Bt848 provides a 24-bit wide general purpose I/O port. There are two modes of operation for the GPIO port: normal mode and synchronous pixel interface (SPI) mode. ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Figure 31. GPIO SPI Output Mode Video Scaler Decoder GPIO Normal Mode In the GPIO normal mode, each of the general purpose I/O pins can be pro- grammed individually. An internal register (GPOE) can ...
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E I LECTRICAL NTERFACES General Purpose I/O Port Table 13. Synchronous Pixel Interface (SPI) GPIO Signals GPIO Signal [23] HRESET A 64-clock-long active low pulse output following the rising edge of CLKx1. The falling edge of HRESET indicates ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Figure 32. Video Timing in SPI Mode HRESET VRESET FIELD HACTIVE VACTIVE VBISEL HRESET VRESET FIELD HACTIVE VACTIVE VBISEL Notes: (1). HRESET precedes VRESET by two clock cycles at the beginning of fields 1, ...
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E I LECTRICAL NTERFACES General Purpose I/O Port Figure 33. Basic Timing Relationships for SPI Mode Y[7: [7: DVALID ACTIVE GPCLK C FLAG B Digital Video in Support This section describes how to use the Bt848A/849A ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Table 14. Pin Definition of GPIO Port When Using Digital Video-In Mode GPIO Signal [23] CLKx1 Output signals for synchronizing to input video. [22] FIELD [21] VACTIVE [20] VSYNC [19] HACTIVE [18] HSYNC [17] ...
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E I LECTRICAL NTERFACES General Purpose I/O Port This interface is the same as CCIR 656 but the clock runs at 24.54 MHz, and there Modified SMPTE-125 are 640 active pixels on a 780 pixel line. This clock rate difference ...
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Bt848/848A/849A Single-Chip Video Capture for PCI 2 I The Inter-Integrated Circuit (I and data lines, SCL and SDA, are used to transfer data between the bus master and the slave device. ter devices, but many slaves may be in the ...
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E I LECTRICAL NTERFACES Interface data (checking for a receiver acknowledge after each byte), and a STOP signal. The write data is supplied from a 24-bit register with bytes I2CDB0, I2CDB1, and I2CDB2. This 24-bit register is ...
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Bt848/848A/849A Single-Chip Video Capture for PCI JTAG Interface Need for Functional As the complexity of imaging chips increases, the need to easily access individual Verification chips for functional verification is becoming vital. The Bt848 has incorporated special circuitry that allows ...
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E I LECTRICAL NTERFACES JTAG Interface Optional Device ID The Bt848 has the optional device identification register defined by the JTAG spec- Register ification. This register contains information concerning the revision, actual part number, and manufacturers identification code specific to ...
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Ground Planes Brooktree ® OARD AYOUT C ONSIDERATIONS The layout should be optimized for lowest noise on the Bt848 power and ground lines by shielding the digital inputs/outputs and providing good decoupling. The lead length between groups ...
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OARD AYOUT ONSIDERATIONS Power Planes Power Planes The power plane area should encompass all Bt848 power pins, voltage reference circuitry, power supply bypass circuitry for the Bt848, the analog input traces, any input amplifiers, and all ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Latch-up Avoidance Latch- failure mechanism inherent to any CMOS device triggered by static or impulse voltages on any signal input pin exceeding the voltage on the power pins by more ...
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OARD AYOUT ONSIDERATIONS Latch-up Avoidance Figure 40. Typical Power and Ground Connection Diagram and Parts List PCI VIO + Ground Location Description (1) C1–3 0.1 F ceramic capacitor C4–6 ( tantalum capacitor ...
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Brooktree ® ONTROL EGISTER D EFINITIONS Bt848 supports two types of address spaces. The configuration address space in- cludes the pre-defined PCI configuration registers, while the memory address space includes all the local registers used by Bt848 to ...
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ONTROL EGISTER EFINITIONS PCI Configuration Space Figure 41. PCI Configuration Space Header cycles. The configuration space registers are stored in dwords and defined by byte addresses. Therefore a register one byte in length can have a bit ...
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Bt848/848A/849A Single-Chip Video Capture for PCI bits of the PCI bus. The 8-bit byte-address for each of the following register loca- tions is {AD[7:2], 00 single-function device, Bt848 ignores bits AD[10:8 Bt848. User-definable features, BIST, Cache ...
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ONTROL EGISTER EFINITIONS PCI Configuration Registers PCI Configuration Registers Vendor and Device ID Register PCI Configuration Header Location 0x00 Bits Type Default Name [31:16] RO 0x0350 Device ID (Bt848/848A) 0x351 Device ID (Bt849A) [15:0] RO 0x109E Vendor ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Command and Status Register PCI Configuration Header Location 0x04 The Command[15:0] register provides control over ability to generate and respond to PCI cycles. When a zero is writ- ten to this register, Bt848 is ...
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ONTROL EGISTER EFINITIONS Revision ID and Class Code Register Revision ID and Class Code Register PCI Configuration Header Location 0x08 Bits Type Default Name [31:8] RO 0x040000 Class Code [7:0] RO 0x0X Revision ID Latency Timer Register ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Interrupt Line, Interrupt Pin, Min_Gnt, Max_Lat Register PCI Configuration Header Location 0x3C Bits Type Default Name [31:25] RO 0x28 Max_Lat [24:16] RO 0x10 Min_Gnt [15:8] RO 0x01 Interrupt Pin [7:0] RW Interrupt Line Min_Gnt ...
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ONTROL EGISTER EFINITIONS Local Registers Local Registers Bt848’s local registers reside in the 4KB memory addressed space. All of the reg- isters correspond to dwords or a subset thereof. The local registers may be written to or ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Device Status Register Memory Mapped Location 0x000 – (DSTATUS) Upon reset it is initialized to 0x00. COF is the least significant bit. The COF and LOF status bits hold their values until reset to ...
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ONTROL EGISTER EFINITIONS Input Format Register Input Format Register Memory Mapped Location 0x004 – (IFORM) Upon reset it is initialized to 0x58. FORMAT(0) is the least significant bit. Bits Type Default Name [ Reserved [6:5] ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Temporal Decimation Register Memory Mapped Location 0x008 – (TDEC) Upon reset it is initialized to 0x00. DEC_RAT(0) is the least significant bit. This register enables temporal decimation by discarding a finite number of fields ...
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ONTROL EGISTER EFINITIONS Vertical Delay Register, Lower Byte Vertical Delay Register, Lower Byte Memory Mapped Location 0x010 – Even Field (E_VDELAY_LO) Memory Mapped Location 0x090 – Odd Field (O_VDELAY_LO) Upon reset it is initialized to 0x16. VDELAY_LO(0) ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Horizontal Active Register, Lower Byte Memory Mapped Location 0x01C – Even Field (E_HACTIVE_LO) Memory Mapped Location 0x09C – Odd Field (O_HACTIVE_LO) Upon reset it is initialized to 0x80. HACTIVE_LO(0) is the least significant bit. ...
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ONTROL EGISTER EFINITIONS Brightness Control Register Brightness Control Register Memory Mapped Location 0x028 – (BRIGHT) Upon reset it is initialized to 0x00. Bits Type Default Name [7:0] RW 0x00 BRIGHT BRIGHT Hex Value 0x80 0x81 . . ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Miscellaneous Control Register Memory Mapped Location 0x02C – Even Field (E_CONTROL) Memory Mapped Location 0x0AC – Odd Field (O_CONTROL) Upon reset it is initialized to 0x20. SAT_V_MSB is the least significant bit. Bits Type ...
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ONTROL EGISTER EFINITIONS Luma Gain Register, Lower Byte Luma Gain Register, Lower Byte Memory Mapped Location 0x030 – (CONTRAST_LO) Upon reset it is initialized to 0xD8. CONTRAST_LO(0) is the least significant bit. Bits Type Default Name [7:0] ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Chroma (U) Gain Register, Lower Byte Memory Mapped Location 0x034 – (SAT_U_LO) Upon reset it is initialized to 0xFE. SAT_U_LO(0) is the least significant bit. SAT_U_MSB in the CONTROL regis- ter, and SAT_U_LO concatenate ...
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ONTROL EGISTER EFINITIONS Chroma (V) Gain Register, Lower Byte Chroma (V) Gain Register, Lower Byte Memory Mapped Location 0x038 – (SAT_V_LO) Upon reset it is initialized to 0xB4. SAT_V_LO(0) is the least significant bit. SAT_V_MSB in the ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Hue Control Register Memory Mapped Location 0x03C – (HUE) Upon reset it is initialized to 0x00. HUE(0) is the least significant bit. An asterisk indicates the default option. Bits Type Default Name [7:0] RW ...
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ONTROL EGISTER EFINITIONS SC Loop Control Register SC Loop Control Register Memory Mapped Location 0x040 – Even Field (E_SCLOOP) Memory Mapped Location 0x0C0 – Odd Field (O_SCLOOP) Upon reset it is initialized to 0x00. Reserved(0) is the ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Output Format Register Memory Mapped Location 0x048 – (OFORM) Upon reset it is initialized to 0x00. OFORM(0) is the least significant bit. Bits Type Default Name [ RANGE [6: CORE ...
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ONTROL EGISTER EFINITIONS Vertical Scaling Register, Upper Byte Vertical Scaling Register, Upper Byte Memory Mapped Location 0x04C – Even Field (E_VSCALE_HI) Memory Mapped Location 0x0CC – Odd Field (O_VSCALE_HI) Upon reset it is initialized to 0x60. Bits ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Test Control Register Memory Mapped Location 0x054 – (TEST) This control register is reserved for putting the part into test mode. Write operation to this register may cause unde- termined behavior and should not ...
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ONTROL EGISTER EFINITIONS ADC Interface Register ADC Interface Register Memory Mapped Location 0x068 – (ADC) Upon reset initialized to 0x82. CRUSH is the least significant bit. Bits Type Default Name [7: Reserved [5] ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Video Timing Control Memory Mapped Location 0x6C – Even Field (E_VTC) Memory Mapped Location 0xEC – Odd Field (O_VTC) Upon reset initialized to 0x00. VFILT(0) is the least significant bit. Bits Type ...
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ONTROL EGISTER EFINITIONS Software Reset Register Software Reset Register Memory Mapped Location 0x07C – (SRESET) This command register can be written at any time. Read cycles to this register return an undefined value. A data write cycle ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Color Control Register Memory Mapped Location 0x0D8 – (COLOR_CTL) A value of 1 enables byte swapping of data entering the FIFO. B3[31:24] swapped with B2[23:16] and B1[15:8] swapped with B0[7:0]. Bits Type Default Name ...
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ONTROL EGISTER EFINITIONS Capture Control Capture Control Memory Mapped Location 0x0DC – (CAP_CTL) Bits Type Default Name [7:5] RW 000 Reserved [ DITH_FRAME [ CAPTURE_VBI_ODD [ CAPTURE_VBI_EVEN [ CAPTURE_ODD ...
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Bt848/848A/849A Single-Chip Video Capture for PCI PLL Reference Multiplier - PLL_F_LO (Bt848A/849A only) Memory Mapped Location - 0x0F0 Upon reset it is initialized to 00 Bits Type Default Name [7:0] RW 0x00 PLL_F_LO PLL Reference Multiplier - PLL_F_HI (Bt848A/849A only) ...
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ONTROL EGISTER EFINITIONS Interrupt Status Interrupt Status Memory Mapped Location 0x100 – (INT_STAT) This register provides status of pending interrupt conditions. To clear the interrupts, read this register, then write the same data back ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Bits Type Default Name [11 RISCI [10 Reserved [ GPINT [ I2CDONE [7: Reserved [ VPRES [ HLOCK [3] RR ...
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ONTROL EGISTER EFINITIONS Interrupt Mask Interrupt Mask Memory Mapped Location 0x104 – (INT_MASK) Bits Type Default [22:0] RW 0x000000 [23 RISC Program Counter Memory Mapped Location 0x120 – (RISC_COUNT) Bits Type Default Name [31:0] RO ...
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Bt848/848A/849A Single-Chip Video Capture for PCI GPIO and DMA Control Memory Mapped Location 0x10C – (GPIO_DMA_CTL) Bits Type Default Name [15 GPINTC [14 GPINTI [13 GPWEC [12:11 GPIOMODE [10 GPCLKMODE ...
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ONTROL EGISTER EFINITIONS GPIO Output Enable Control GPIO Output Enable Control Memory Mapped Location 0x118 – (GPIO_OUT_EN) Bits Type Default Name [23:0] RW 0X000000 GPOE GPIO Registered Input Control Memory Mapped Location 0x11C – (GPIO_REG_INP) Bits Type ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Data/Control Memory Mapped Location 0x110 Bits Type Default Name [31:24] RW I2CDB0 [23:16] RW I2CDB1 [15:8] RW I2CDB2 [7:4] RW 00000 I2CDIV [ I2CSYNC [ I2CW3B [1] ...
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ONTROL EGISTER EFINITIONS Data/Control 118 Single-Chip Video Capture for PCI L848A_A Bt848/848A/849A Brooktree ® ...
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Introduction The registers in this section are only required when using the GPIO port to input digital video signal. These registers are included to enable the GPIO port to seamlessly connect to digital video cameras. Digital Video Signal Interface Format ...
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ONTROL EGISTER IGITAL IDEO N Timing Generator Load Byte Timing Generator Load Byte Memory Mapped Location 0x080 – (TGLB) Upon reset initialized to 00. Bits Type Default Name [7: TGLB Timing ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Luma Gain Register, Lower Byte Memory Mapped Location 0x030 – (CONTRAST_LO) This is the alternate definition for the CONTRAST_LO register when using the Bt848A/849A. Upon reset it is initialized to 0xD8 (this must be ...
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ONTROL EGISTER IGITAL IDEO N Chroma (V) Gain Register, Lower Byte Chroma (V) Gain Register, Lower Byte Memory Mapped Location 0x038 – (SAT_V_LO) This is the alternate definition for the SAT_V_LO register when using the ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Chroma (U) Gain Register, Lower Byte Memory Mapped Location 0x034 – (SAT_U_LO) This is the alternate definition for the SAT_U_LO register when using the Bt848A/849A. Upon reset it is initialized to 0xFE (this must ...
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ONTROL EGISTER IGITAL IDEO N HDELAY/HSCALE HDELAY/HSCALE HDELAY = 128 * (#DesiredPixels/#Hactive Pixels) HSCALE = 4096 * (#HactivePixels/#DesiredPixels –1) This is the alternate usage for the HDELAY and HSCALE registers when using the Bt848A/849A. The ...
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DC Electrical Parameters Table 16. Recommended Operating Conditions Parameter Power Supply — Analog Power Supply — Digital Maximum |V – MUX0, MUX1, MUX2, and MUX3 Input Range (AC coupling required) YIN, CIN Amplitude Range (AC coupling ...
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P I ARAMETRIC NFORMATION DC Electrical Parameters Table 18. DC Characteristics Parameter Digital Inputs PCI Inputs Input High Voltage (TTL) Input Low Voltage (TTL) 2 GPIO/I C Input High Voltage Input Low Voltage Input High Voltage (XT0I, XT1I) Input Low ...
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Bt848/848A/849A Single-Chip Video Capture for PCI AC Electrical Parameters Table 19. Clock Timing Parameters Parameter NTSC: 8*F Rate (50 PPM source required) SC PAL: 8*F Rate (50 PPM source required) SC XT0 and XT1 Inputs: Cycle Time High Time Low ...
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P I ARAMETRIC NFORMATION AC Electrical Parameters Table 21. Power Supply Current Parameters Parameter Supply Current V =V =5.0V, F =28.64 MHz, T=25˚ =5.25V, F =35.47 MHz, T=70˚ =5.25V, F ...
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Bt848/848A/849A Single-Chip Video Capture for PCI Table 24. Decoder Performance Parameters Parameter Horizontal Lock Range Fsc, Lock-in Range Gain Range NOTE: Test conditions (unless otherwise specified): “Recommended Operating Conditions.” TTL input values are 0–3 V, with input rise/fall times 3 ...
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P I ARAMETRIC NFORMATION Package Mechanical Drawing Package Mechanical Drawing Figure 45. 160-pin PQFP Package Mechanical Drawing Datasheet Revision History Table 25. Bt848 Datasheet Revision History Revision Date Description A 02/07/97 Initial Release 130 Single-Chip Video Capture for PCI L848A_A ...
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Brooktree ® Brooktree Division Rockwell Semiconductor Systems, Inc. 9868 Scranton Road San Diego, CA 92121-3707 (619) 452-7580 1(800) 2-BT-APPS FAX: (619) 452-1249 Internet: apps@brooktree.com L848A_A printed on recycled paper ...